herbert zirath*#, harald jacobsson#, m. bao#, mattias...

IEEE MMIC seminar Bergen 2006 10 06 H Zirath

Designing low phase noise integrated VCOs

Herbert Zirath*#, Harald Jacobsson#, M. Bao#, Mattias Ferndahl*, Rumen Kozhuharov*

*Chalmers University of Technology, Microwave Electronics Laboratory, MC2, Göteborg, Sweden# Ericsson AB, Microwave and High Speed Electronics Research Centre, Mölndal, Sweden

[email protected]


Content

-Motivation-Design issues for low phase noise

1. Technology choice 2. Tank design3. Varactor design4. Current waveform5. Oscillator combining

-Some realizations:1. Combined crosscoupled differential pair2. Balanced Colpitt3. Second harmonic Balanced Colpitt4. Hartley

-Conclusions

G

Iee

+ V0 -


-120

-110

-100

-90

-80

-70

-60

-50

-40

1 10 100Frequency (GHz)

Phas

e no

ise

(dB

c)

GaAs HBT SiGe HBT MESFET PHEMT CMOS InP HBT

24

14

FECFET

16

thth

24

18

18

13

15

15 22

1721

23

20

27

19

26.126.2

26.3

25

1313

13

60

Slope: 20 log N

Published data phase noise versus frequency @100kHz offset frequency


-120

-110

-100

-90

-80

-70

-60

-50

-40


Phas

e no

ise

(dB

c)


24

14

FECFET

16

thth

24

18

18

13

15

15 22

1721

23

20

27

19

26.126.2

26.3

25

1313

13

See IEEE JSSC, Vol. 40, no 10, October 2005.

X1 Colpitt X2 Colpitt

Typical demand for digital radio links w. complex modulation format

60


Leeson’s model for phasenoise

Leeson described the variation of the phase noise 1966

( )⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛

Δ

Δ+⋅

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛Δ⋅⋅

+⋅⋅⋅

⋅=Δω

ω

ωωω

312

0 12

12log10 f

QPsigTkFL

F represents various noise mechanismsPsig is the power in the resonatorQ is the Q-value of the resonance circuitΔω is the offset frequencyΔω 1/f

3 is the 1/f3 the corner frequency


Technologies used in this work and associated critical parameters

Technology BV fT GHz fmax GHz manufacturer

InGaP-GaAsHBT

10 60 110 K*ON

SiGe HBT 2.5 70 90 STM

SiGe HBT 3.3 48 65 IBM

CMOS 1.2 170 240 IMEC

PHEMT 8 70 180 OMMIC

MHEMT 8 90 210 WIN


Tank design: Choice of L and C: High tank energy design

Maximize the tank energy for lowest phase noise*

*D Ham, A Hajimiri, IEEE JSSC Vol 36,no. 6, pp. 896-909, June 2001

Vtank is set by the breakdown voltage of the transistor, maximize C

->L have to be decreased to maintain the oscillation frequency->Itank have to be increased in order to increase the tank energy

For high tank energy design, it becomes critical that the transistor can deliver a high current, depends on the Q-value of the tank

Don’t forget to design the tank for large circulating currents, be careful not exceeding the current density specs for transmission lines, coupling capacitors etc

2tank

2tanktank 2

121 ILVCE ⋅=⋅=

CL ⋅=

10ω


Example 1: 5 GHz SiGe Balanced Colpitt oscillator

CbCb

VbaseRb2

Rb1

Rb2

Rb1

ReRe

LtankLtankLvar Lvar

Cvar Cvar

C1

Cout CoutC2

C1

Vvar Vdd

Vout2Vout1


Why Colpitt ?

-Can be designed for high efficiency -> VCO-operation at a lower temperature for a certain tank energy, less dc-power consumption

-excellent impulse sensitivity characteristics* -> favorable for low phase noise

However:

-frequency dependent negative resistance

-amplitude control not straightforward

*Ali Hajimiri, Thomas H. Lee,’Low noise oscillators’, ISBN 0-7923-8455-5, 1999, Kluver Academic Publishers


-105

-100

-95

-90

-85

1 10 100Current IBIAS (mA)

Phas

e no

ise

(dB

c)

0.33nH0.15nH0.66nH

Example: Simulation of a single Colpitt oscillator

The tank inductor for the Colpitt oscillator is varied from 0.15 nH to 0.66nH, the oscillation frequency is kept constant.The dc-current IBIAS, controls the ac amplitude of the oscillation and at some current, the ac tank voltage gets voltage limited, the phase noise is increasing at this bias (1). By increasing the maximum tank energy i e by decreasing the tank inductance and increasing the tank-capacitance, we can reach a new, lower level of minimum phase noise at the onset of voltage saturation (2 and 3)

1

23

inductancenH

Series -resistance of inductor

Inductor Q-value

transistorsize

0.15 0.41 11.5 6x20

0.33 0.9 11.5 3x20

0.66 1.8 11.5 2x20


Phase noise versus current, Vcc=3.2 V

-110

-108

-106

-104

-102

-100

10 100Icore (mA)

Phas

e no

ise

(dB

c)

-15

-14

-13

-12

-11

-10

Out

put p

ower

(dB

m)

Vcc=3.2VVcc=4VVcc=4.5Vpower

Simulated phase noise @100kHz offset for the coupled SiGe oscillator versus the biascurrent(emitter current in one of the transistors).

g p

-105

-104

-103

-102

-101

-100

-99

-98

-97

1 10 100

IBIAS (m A)

Phas

e no

ise

(dB

c)

M MIC

Measured phase noise @100kHz offset for the coupled SiGe oscillator versus the bias current (sum of the emitter currents for both transistors).

A minimum of -109dBc is obtained at Vcc=4.5V


CbCb

VbaseRb2

Rb1

Rb2

Rb1

ReRe

LtankLtankLvar Lvar

Cvar Cvar

C1

Cout CoutC2

C1

Vvar Vdd

Vout2Vout1

C2_1 C2_2

Cout

C1C1

Vout1

CbCb

VbaseRb2

Rb1

Rb2

Rb1

ReRe

LtankLtankLvar Lvar

Cvar Cvar

Vvar Vdd

Example 2: InGaP-GaAs Coupled Colpitt VCO with interdigitated varactorFundamental frequency, VCO1 Second harmonic, VCO2


Varactor design 6x10x100 um B-C junction for optimized Q-value

-0.5 0.0 0.5 1.0 1.5 2.0 2.5-1.0 3.0

10

15

20

25

5

30

2

3

4

5

1

6

Varactor voltage [V]

C [pF]

Q


m1freq=dB(S(1,2))=-36.386Vcb=0.000000

7.200GHz

2 3 4 5 6 7 8 91 10

-30

-20

-10

-40

0

freq, GHz

dB(S

(1,2

))

m1

2 3 4 5 6 7 8 91 10

-10

-8

-6

-4

-2

-12

0

freq, GHz

dB(S

(1,1

))

-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8-1.0 1.0

freq (1.000GHz to 10.00GHz)

S(1

,2)

DeLoach varactor test circuit for C and Q-value evaluation


2.2 2.4 2.6 2.8 3.0 3.2 3.42.0 3.6

0.010

0.015

0.020

0.025

0.005

0.030

Vbias

IcdcIcrf

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.41.4 3.6

0.005

0.010

0.015

0.020

0.025

0.000

0.030

Vbias

IcdcIcrf

2 4 6 80 10

-0.02

0.00

0.02

0.04

-0.04

0.06

vcet

2 4 6 80 10

-0.02

0.00

0.02

0.04

-0.04

0.06

vcet

RF and DC collector current versus bias voltage, Ic-Vce trajectories

X2 (VCO2)Fundamental (VCO1)

dc

rf


2.2 2.4 2.6 2.8 3.0 3.2 3.42.0 3.6

-106

-105

-104

-103

-102

-107

-101

Vbias

L

2.5 3.02.0 3.5

0.05

0.10

0.15

0.20

0.00

0.25

2

4

6

8

0

10

Vbias

mag

(iLta

nk.i[

::,1]

)

Vtank

The simulated tank inductor current and the tank voltage (dashed line) versus Vbias.

The simulated phase noise at an offsetfrequency of 100kHz (fundamental VCO).

400 ohm

Tr2

Tr1

4 kohm

1600 ohm

to base1

to base2

Vbias

R=50 OhmL=10 um

KON_TFR_lTFR_L4

met2=IMmet1=IMw2=10 umw1=10 um

HS_F1x2x20HS_F1x1x2

scale=40temp=25

R=50 OhmL=10 um

KON_TFR_lTFR_L3


R=50 OhmL=10 um

KON_TFR_lTFR_L2


R=50 OhmL=10 um

KON_TFR_lTFR_L1


HS_F1x2x20HS_F1x1x1

scale=40temp=25

The base-current bias circuit

1.5 2.0 2.5 3.0 3.5 4.0 4.51.0 5.0

2

4

6

8

10

0

12

Vbias

Att

Attenuation of a noise signal at the bias terminal versus Vbias


-130

-120

-110

-100

-90

-80

2,4 2,6 2,8 3 3,2 3,4 3,6Vbias (V)

-120

-115

-110

-105

-100

-95

-90

200

250

300

350

400

2,6 2,8 3 3,2 3,4 3,6 3,8

Vbias (V)

Phase noise and core current versus base bias voltage for VCO1 and VCO2.


PHEMT and mHEMT technologies are very suitable for mm-wave systems but HEMT-based VCOs have usually high phase noise ?

Example 3: PHEMT Coupled Colpitt VCO with interdigitated varactor


14.9-15.8 GHz, Pout= -2 to 2dBmLmin=-104 dBc @100kHz at 14.9 GHz, PDC=150 mW, large L-variation

7.5-7.88 GHz, Pout >4 dBmLmin=-90 to -95 dBc @100kHzPDC=150 mW

-3 -2.5 -2 -1.5 -1 -0.5 0 0.5

500

1000

1500

2000

Varactor voltage [V]

Cap

acita

nce

[fF]

-3 -2.5 -2 -1.5 -1 -0.5 0 0.520

30

40

50

60

Q-v

alue

High Q-values of varactor achieved: 40-50 for Vvar< -1V20 parallel gate-fingers Lw=100um


Example 4: InGaP-GaAs HBT Coupled Hartley VCO

0.67 mm

0.99

mm

Bao


Single-ended Hartley VCO

At high frequency, a Hartley VCO has a better phase noise performance than a Colpitts VCO, because― the resonator of Hartley VCO consists of

two inductors and one capacitor, instead of two capacitors and one inductor for Colpitts VCO

― Inductors has higher Q value than that of capacitors, thus, the reasonator of Hartley VCO has higher Q value than that of Colpitts VCO.

The π-network in a Hartley VCO▬ acts as a resonator▬ offers 180-phase shift to compensate

phase shift between base-collector▬ transforms impedance.

Re

C

LcLb

(a)

Rin

π−network

V

I

Rp

Bao


• Transistor in common-emitter configurationis used, which has high collector resistance and moderate base resistance

loading resonator slightly comparing to CB or CC configuration where a small emitter resistor would load resonator heavily.

• The transistor in CE configuration also has the highest gain comparing with other configurations

less DC current is needed to sustain an oscillation, and less noise isgenerated by active device

Re

C

LcLb

(a)

Rin

π−network

V

I

Rp

Bao


• Two single-ended Hartley VCOs consists of a balanced Hartley VCO

• The differential output signals are taken from emitters– outside load does not connect

with resonator directly– transistors acts as a buffers

reducing load-pull effect and phase noise

Bao


0.67 mm

0.99

mm

A 25GHz VCO in InGaP/GaAs HBT technology

Bao


Pdc=90 mWIc=10 mA,Vc=9 VFOM=-195 dBc/Hz

-140-130-120-110-100

-90-80-70-60-50-40

1 10 100 1000Offset Frequency (KHz)

Pha

se N

oise

(dB

c/H

z)

-140

-130

-120

-110

-100

-90

-80

0 0,5 1 1,5 2 2,5 3 3,5

Vtune (V)

Pha

se N

oise

(dB

c/H

z) Offset@100KHz Offset@1MHz

Phase noise at 100 KHz and 1 MHz offset versus Vtune

-4

-2

0

2

4

0 0,5 1 1,5 2 2,5 3 3,5Vtune (V)

Out

put P

ower

(dB

m)

25,3

25,4

25,5

25,6

25,7

25,8Fr

eque

ncy

(GH

z)

Oscillation frequency and output power versus Vtune

Dr Ming X Bao

Phase noise versus offset frequency at Vtune=2V

)log(10log20)( DCoff

ooff P

fffLFOM +

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛−=


• Cross-coupled differential amplifier generates negative conductance

• Wide frequency band negative conductance

• Similar for CMOS

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛−= −

TVV

VIG

T

ee

2cosh

402

-4 -2 0 2 4

Con

duct

ance

Vo/ V

T

0

-Iee

/ 4VT

G

Iee

+ V0-

2msmall gG −=

Example 5: SiGe HBT CCDP VCO


SiGe VCO Measurements• Single differential VCO

– Tuning: 5.56 GHz - 5.78 GHz– Power consumption: 30 mW (excluding buffers)– -3dBm output power (differential from buffers, PDC=135mW incl buffers)

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

1k 10k 100k 1 000k 10 000k

Offset frequency (Hz)

Phas

e no

ise

(dBc

/Hz)

-107 dBc/Hz

5.7 GHz

Dr Harald Jacobsson et al


10-12 GHz CMOS VCO (i)

• Cross-coupled differential pair nmos-only with DC-feedback

• Nmos varactor• Inductor ”current source”• ~20 % tuning range• Vsupply down to 0.6 V

• Pout=-13dBm at PDC = 1.6 mW• Pout=-8dBm at PDC = 5 mW

VDD

Vtune

10,0

10,5

11,0

11,5

12,0

12,5

13,0

0 0,2 0,4 0,6 0,8 1 1,2Tuning voltage (V)

Freq

uenc

y (G

Hz)

MeasuredSimulated

Example 6: CMOS CCDP VCO



10-12 GHz VCO (ii)

• moderate phase noise, -81 to -91dBc/Hz @100kHz offset• Very clean noise spectrum – no spurioses• Record F.O.M. = 197• Phase noise deteriorates with tuning voltage

reduced Q of nmos varactor in inversion

-160-150-140-130-120-110-100-90-80-70-60-50-40-30-20

1k 10k 100k 1 000k 10 000k


Pha

se n

oise

(dB

c/H

z)

Meas. vctrl=0VMeas. vctrl=1.2V

f=12.7 GHz

f=10.5 GHz

Vdd=0.6 V

F.O.M. = 197



How can phase noise be further reduced with one and the same technology?

• Couple N VCOs - the phase noise is reduced to 1/N

Why?

• Signal power increases as N2

• Noise power increases as N (uncorrelated)

• S/N ratio increases as N


Coupled CCDP VCOs

1. Inductive coupling2. Superharmonic coupling

VCO 1

VCO 2

VDD VDD



-150-140-130-120-110-100

-90-80-70-60-50

1k 10k 100k 1 000k 10 000k


Phas

e no

ise

(dBc

/Hz)

SingleDoubleQuadruple

• Four coupled VCOs– Tuning: 10.0 GHz - 11.9 GHz– Continuous tuning: 500 MHz– Power consumption: 110 mW

(excluding buffers)

Example 7: Coupled SiGe HBT CCDP VCO



-120

-110

-100

-90

-80

-70

-60

-50

-40


Phas

e no

ise

(dB

c)


24

14

FECFET

16

thth

24

18

18

13

15

15 22

1721

23

20

27

19

26.126.2

26.3

25

1313

13

0.67 mm

0.99

mm

Summary of presented oscillators: Phase noise at 100kHz offset

.


Conclusion

Low noise VCOs based on Colpitt, Hartley, and crosscoupled differential pairs have been presented utilizing PHEMT, SiGe HBT, InGaP-GaAs HBT, and CMOS technologies

-Lowest phase noise obtained by InGaP-GaAs HBT based Colpitt design-InGaP-GaAs HBT Hartley excellent at higher frequencies

-Excellent performance also by SiGe HBT Colpitt and CCDP VCOs

Future work:

-extended tuning range-optimized varactors-amplitude stabilization-increased tankenergy for lower PN-investigate symmetry and second harmonic sensitivity on phase noise

herbert zirath*#, harald jacobsson#, m. bao#, mattias...

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