high efficiency residential photovoltaic system

High Efficiency ResidentialPhotovoltaic system

Det Teknisk-Naturvidenskabelige Fakultet

Institut for elektroniske systemer

Fredrik Bajers Vej 7 A1

9220 Aalborg Ø

Danmark

http://ies.aau.dk

Synopsis:Dette projekt omhandler design,dimensionering og konstruktion afen energieffektiv hi-fi-forstærker medet G-trin. I private hjem findes etbetydeligt antal hi-fi-forstærkere,som ofte har en stor maksimal ud-gangseffekt i forhold til det normalebrugsniveau. Dette giver anledningtil en ringe virkningsgrad. Derfor erder konstrueret en hi-fi-forstærker,som er optimeret efter forbedretvirkningsgrad i en driftssituation.Med udgangspunkt i standarderneIEC 268 og IEC 581 er relevantekrav opstillet til en mono-forstærker,der kan levere en udgangseffekt pa10 W. Forstærkeren er konstrueret,saledes denne kan handtere signalerfra en mikrofon samt fra en CD- ellerAUX-enhed. En digital volumenkon-trol med 16 trin tillader indstillingaf lydniveauet og giver brugerenen visuel indikation af dette. Forat give brugeren en indikation afudgangstrinnets virkningsgrad er derkonstrueret en effektivitetsindikator,som udlæser et udtryk for effektivi-teten pa et display. Udgangstrinneter opbygget ved at stakke ud-gangstransistorerne, saledes en højforsyningsspænding kun indkobles,nar dette er nødvendigt.Den konstruerede hi-fi-forstærkeroverholder overordnet set de opstil-lede krav. Det er dog kun muligtat afsætte 9,1 W i en 8 Ω-højttalerog ikke 10 W som krævet. I for-stærkeren indgar et G-trin, som ervelfungerende, og giver mulighed forat opna en højere virkningsgrad enden traditionel klasse AB forstærker.

Titel:Energieffektiv hi-fi-forstærker

Tema:Analog og digital teknik

Projektperiode:E3 2005

Projektgruppe:317

Gruppemedlemmer:Thomas EsbensenJan Fisker Bruun JørgensenRasmus SkjøttChristoffer SlothMorten Burchard Tychsen

Vejleder:Søren Krarup Olesen

Oplag:8

Sideantal:Rapport: 101Appendikser: 31Bilag: 19Samlet: 151

Afsluttet:19. december 2005

Master of Science in Energy Technology

10th Semester, fall 2011, Group PED4-1040

Department of Energy Technology, Aalborg University

Title: High Efficiency Residential Photovoltaic system

Semester: 10th.

Semester theme: M.Sc. project

Project period: 01st.09.11 to 01st.02.12

ECTS: 30

Supervisor: Tamas Kerekes

Co-supervisors: Remus Teodorescu and Pedro Rodriguez

Project group: PED4-1040

Cam Pham

Abstract:

In this report a novel high efficiency topology has been pro-

posed, which is using low voltage switches and manage

bidirectional power flow in 700V applications.

A methodology has been established to perform analytic

calculations of power losses.

A thermal model in Plecs has been created to predict the

losses.

As the result, the simulation confirms the analytical calcu-

lations, the worst case efficiency is 97% at 3 kW in boost

mode and 98.3% in buck mode.

The converter has been designed and built. Due to time

constraint the verification of high efficiency is postponed to

after the report submit.

Number printed: 5 pcs.

Number of pages: 51 pages

Appendix: 3

Annexe: 1 CD

Titel: Høj virkningsgrad solcelleanlæg til boliger

Semester: 10.

Semester tema: Kandidat projekt

Projektperiode: 01.09.11 til 01.02.12

ECTS: 30

Vejleder: Tamas Kerekes

Bi-vejleder: Remus Teodorescu og Pedro Rodriguez

Projektgruppe: PED4-1040

Cam Pham

SYNOPSIS:

En ny højvirkningsgrad topologi er blev foreslaet i denne

rapport, som kan anvende med lav spænding elektronisk

kontakter og handtere tovejs effekt flow i 700 Vs applika-

tioner.

En metodologi er etableret til at fortage analytisk bereg-

ninger af effekttab.

En termisk model er blev fremstillet i Plecs til at forudsige

tab.

Resultatet er, at simulering bekræfter de analytisk bereg-

ninger, hvor værst tænkelig virkningsgrad er 97% ved 3 kW

i boost tilstand og 98.3% i buck tilstand.

Omformer er blev designet og bygget. Pa grund af tids-

begræsning, verifikation af højvirkningsgrad er udskudt til

efter rapport aflevering.

Oplag: 5 stk.

Antal sider: 51 sider

Appendiks: 3

Bilag: 1 CD

Preface

The project report on a dual phases bidirectional DC-DC converter. It has been written by

group PED4-1040 at the Department of Energy Technology at Aalborg University. It was conducted

during the 1st of September to 1st of Febuary 2012.

The target groups of this report are the fellow student in the department and for those who has

the intrested in power electronic.

Literature references are given in [] and they can be found in bibliography at the end of this

report, e.g. [1] is the number one in the reference list. Equations are numbered in format (x.y) and

figures are numbered in format Figure x.y, where x is the chapter number and y is the number of the

item.

The enclosed CD-ROM contains the project written in Adobe PDF format and the simulation

files. All the simulations used in this project were performed in MATLAB/SIMULINK 32-bit.

I would like to thanks my supervisors Tamas Kerekes, Remus Teodorescu and Pedro Rodriguez

for the contructive comments an idea. A special thank to Cristian Nicolae from the 9th semester who

has helped me when I need most. At last, thanks to my wife Nga thi Thuy Nguyen, my daugther

Lyly Cam Tien Pham and my son Isaac An Pham for being a part of me. Thuong 2 con va em nhieu.

Cam Pham.

VI

Table of contents

List of Figures 1

List of Tables 2

1 Introduction 4

1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1.1 Smart PV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1.1.1 Electricity price . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1.1.2 Residential consumption and PV generation . . . . . . . . . . . . 7

1.1.1.3 Smart PV configuration . . . . . . . . . . . . . . . . . . . . . . . 8

1.2 Problem formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3 Project limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4 Report outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 Bi-directional DC-DC converters for batteries 11

2.1 Dual phases bidirectional split converter . . . . . . . . . . . . . . . . . . . . . . 13

2.1.1 Select of semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.2 Boost and filter inductor . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1.3 Interleaved dual phases bidirection split converter . . . . . . . . . . . . . 17

3 Thermal modelling with PLECS 19

3.1 Modelling of the boost part of the converter . . . . . . . . . . . . . . . . . . . . 20

3.2 Modelling of the buck part of converter . . . . . . . . . . . . . . . . . . . . . . 22

4 Converter design and practical results 23

TABLE OF CONTENTS

4.1 Miscellaneous circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1.1 Sensing circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1.2 Current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1.3 Gate drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1.4 Output filter capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.1 Gate and drive protection . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.2 Heat sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.3 Thermal sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2.4 Onboard protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3 Practical works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3.1 PCB routing strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.3.2 Efficiency report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5 Conclusion and future work 30

5.1 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

references 30

A Methodology 34

A.1 Losses in the converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

A.1.1 Losses in semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . 34

A.1.1.1 MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

A.1.1.2 Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

A.1.2 Losses in the inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

A.1.3 Others losses in the converter . . . . . . . . . . . . . . . . . . . . . . . 41

B Inductor design step by step 42

B.1 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

C Schematics of the converter 47

VIII

List of Figures

1.1 The infrastructure of a Smart Grid, where generations and loads are connected in a

network, that operates in parallel with utility grid [1]. . . . . . . . . . . . . . . . . . 4

1.2 The world market for standard and smart inverters[2] . . . . . . . . . . . . . . . . . 5

1.3 The sharing of unit price for private consumer with 4000 kWh per year[3]. . . . . . . 6

1.4 24-hours average of electricity energy Spot price in July. . . . . . . . . . . . . . . . 6

1.5 24-hours average of electricity energy consumption and PV generation in July. . . . . 7

1.6 24-hours average of electricity energy consumption and doubled PV generation sce-

nario. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.7 A potential PV installation with battery storage for Smart Grid solution with energy

management system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 The boost and the buck converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 The proposed bidirectional DC-DC converter for batteries. . . . . . . . . . . . . . . 12

2.3 Waveform of the inductor current over a switching cycle (Ts. . . . . . . . . . . . . . 13

2.4 The bidirectional split converter(BSC), where lower blocking voltage switches are

utilised. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5 Modification of CP device with two SiC diodes to block the slow body diode and

improve the switching charateristics. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6 Interleaved dual phases bidirectional split interleaved converter (IDPBSC). . . . . . . 17

3.1 Screen dump in PLECS of the modelled IDPBSC in boost mode. . . . . . . . . . . . 20

3.2 The transient in the modelled converter. . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3 Efficiency plot in boost mode where solid blue line is for Vin = 168 and the solid

green line is Vin = 224. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4 Efficiency plot in buck mode where solid blue line is for Vout = 168 and the solid

green line is Vout = 224. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

LIST OF FIGURES

4.1 Electrical analog of the thermal process. . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2 Observed problem in boost mode; 140ns oscillation and too slow turn off time. . . . 27

4.3 Observed problem in buck mode without RC snubber; high voltage ringing and slow

turn off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.4 Section of PCB traces in version 2. where some routing strategies is visible. . . . . . 28

4.5 The sketch of laboratory setup for testing efficiency. . . . . . . . . . . . . . . . . . . 29

A.1 RDSonas function of junction temperature for IPW60R099CP[4]. . . . . . . . . . . 36

A.2 RDSoncharateristic for IPW60R099CP[4] at 150C. . . . . . . . . . . . . . . . . . 37

A.3 Switch-on waveform of the MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . 37

A.4 Switch-off waveform of the MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . 38

A.5 Diode forward charateristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

C.1 Battery sensing circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

C.2 DC link sensing circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

C.3 Current sensing circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

C.4 Gate drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

C.5 Thermal sensing circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

C.6 On board programmable protection circuit. . . . . . . . . . . . . . . . . . . . . . . . 50

2

List of Tables

1.1 Eletrical parameters of Saft Synerion 48 E[5]. . . . . . . . . . . . . . . . . . . . . . 9

2.1 Properties of the converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 Comparision of parameters between 1200 V SiC MOSFET with IPW65R110CFD

and the modified CP device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3 Power losses in Boost-buck, BSC and IDPBSC. . . . . . . . . . . . . . . . . . . . . 18

Chapter 1

Introduction

1.1 Background

To slow down the climate change and reduce the carbondioxide emmision caused by human

activity, worldwide goverments work on a common goal - to reduce carbondioxide emmision.

The goal of the Danish energy policy in year 2020 for power system is; 50 percents of power

production is to be generated from renewable sources, mainly from wind power. The ambition is to

become independent of fossil fuels in the year 2050 [1]. To overcome challenges like; fluctuating

production from wind power and the extra load from Electric vehicles (EVs) in the future, huge

imbalancing of generation and demand etc., worldwide researchers believe that Smart Grids can be

the solution. The infrastructure of a Smart Grid can be seen in Figure 1.1. It can be seen, besides

the primary substainable generations and storages, the end users have also similiar facilities, all

connected in a network.

Smart Grid is an IT infrastructure parallel with the grid

Figure 1.1: The infrastructure of a Smart Grid, where generations and loads are connected in a network, that

operates in parallel with utility grid [1].

CHAPTER 1 - Introduction

Among different renewable energy sources that can be connected to the grid, one which is ex-

panding fast worldwide is the Photovotaic (PV) technology [6]. PV panels are discrete and often

installed at place like rooftop, some are also a part of modern architecture. Statisticly, the price of

PV modules has been reduced by half for every seven years since 1980s [7]. To increase the interest

of PV in Denmark, the incentive at the moment for the residential installation up to 6 kW is; to store

the energy in the grid, this means for every kWh to the grid can be used again within a year[citation:

ens.dk] for free, this is a saving of a little bit more than 2 kr/kWh. This incentive is not permanent,

but the storage concept can also be realized with batteries. This smart PV solution with storage is

called Smart PV for the rest of the report and in the next subchapter will introduced why Smart PV

is economically attractive.

1.1.1 Smart PV

The main goal of a Smart PV is to promote the use of a classical grid connected PV. In this way the

importances of the inverter are moved from a simple power conversion unit into an essential compo-

nent of grid infrastructure.

Beside the functionalities of grid connected PV, further can be achieved: reactive power compen-

sation, energy storage and smart grid interaction[8]. Through communication with the distribution

system operator (DSO), the smart PV inverters can ease the grid imbalances.

According to IMS Research (see Figure 1.2), Smart PV inverters will take over in 2014 and grow

from 20% of the market in 2010 up to almost 60% in 2015 (27GW).

Figure 1.2: The world market for standard and smart inverters[2]

To highlight the benefits of Smart PV, the following case study is based on PV generation from

the 1.8 kW system in Green Power Lab at AAU, the shown case is from July 2008. More detailed

analysis can also be found in [9]. From the economic point of view, it is more fair to analyze in the

case of Spot price; where energy is payed hourly, electricity tranding is available and storing energy

5


”in the grid” is no longer valid.

1.1.1.1 Electricity price

For a household with a consumption of 4000 kWh per year, the average unit price of electricity is

1.98Kr./kWh. This is included tariffs, subscription ect. and is distributed as shown in the pie chart

below.

1%7%

2%

3%< 1%

4%

24% 58%

Subscription payment, trading

Subscription payment, network

Public service obligation

Energinet.dk transmission

Regional transmission

Distribution network tariff

Electric energy

VAT. and tax.

Figure 1.3: The sharing of unit price for private consumer with 4000 kWh per year[3].

It can be seen that the average Spot price of electric energy is only a quater of the totalt price,

by in house generation of the consumed electricity the dominate part of electricity can be cut away

and only few small subscription fees plus their tax. remain.

Electricity price dependeds on generation and demand. Due to the consumption pattern and the

fluctuation in mostly wind power, Spot price is different from hour to hour but has a 24-hours cycle

as consumption, based on the estimation of the two mentioned, the price is given 24 hours ahead.

Figure 1.4 shows the plot of 24-hours average Spot price of electricity in July. The average Spot

price during the day is 0.492 Kr./kWh and swings more than double from 0.266 Kr./kWh at

4AM till 0.664 Kr./kWh at 11 AM .

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 230

0.1

0.2

0.3

0.4

0.5

0.6

Time

DK

R

Spot sprice July 2008

Figure 1.4: 24-hours average of electricity energy Spot price in July.

6


1.1.1.2 Residential consumption and PV generation

The 24-hours average electricity energy consumption of a resisdential house in DK for July was

25.65 kWh and is distributed as plotted in Figure 1.5 with the green solid line. The minimun

consumption was 0.45 kWh and was between 2 and 3 AM. The maximun was 1.73 kWh and was

between 9 and 10 AM. Based on the mentioned unit price, this cost 51.79 Kr per day.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23-2

-1.5

-1

-0.5

0

0.5

1

1.5

Pow

er[k

W]

Time

PV generationResidential consumptionGross power

Figure 1.5: 24-hours average of electricity energy consumption and PV generation in July.

Based on the data from the 1.8 kW PV setup from the Green Power lab, a 24-hours average

power generation in July is plotted in Figure 1.5 with blue solid line. The average sunny hour in July

was 9 hours and due to different in irradiance and temperature the average of peak energy generation

from a 1.8 kW PV setup was only 1.1 kWh and was between 11 and 12 AM. The total production

was 9.92 kWh per day. PV generation has the advantage, that the distribution of generation pattern

is to a certain degree similiar to the consumption pattern. The solid red line in Figure 1.5 show the

difference between generation and demand, where gross power is more steady, which confirms this

correlation.

From the gross power plot in Figure 1.5, it is obvious that 1.8 kW PV system is too small for

residental households, but what if the setup is doubled to 3.6 kW PV installation?

Figure 1.6 show the power curve for this scenario, where PV generation has been scaled by a factor

of two.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

Pow

er [k

W]

Time

2 x PV generationResidential consumptionGross power

Figure 1.6: 24-hours average of electricity energy consumption and doubled PV generation scenario.

From the macroscopic/day scale the imbalance between generation and demand is minus 5.81

7


kWh, but on microscopic/hour scale, the power imbalance was piecewise positive and was 1.99

kWh, which means more generation than demand. This gives two possiblities, either sell it to Spot

price or store the surplus energy.

Although Spot price during these positive imbalance hours is more than the average; 0.492

Kr./kWh (see Figure 1.4), but the revenue from selling this surplus energy is not enough to cover

the cost of buying 1 kWh from the grid.

Having a storage does give rise to additional cost, but it does also gives the opportunity to trading

with the electricity energy. Electric energy can be bought when the price is lowest and sold when it

is highest, according to Spot price in Figure 1.4, this gives almost 250% in profit, which can reduce

payback time. Processing the energy through a high efficiency converter is very important, because

this affects the profit directly.

1.1.1.3 Smart PV configuration

A potential residential PV installation with battery storage in the future could be like shown in Figure

1.7, where storage is used to store surplus energy from PV panels or trading energy based on the price

information from Nordpool.

S

DC-DC

==

DC-DC

==

Inverter

=~

EMS

PVDSONordpool spot

Storage

Figure 1.7: A potential PV installation with battery storage for Smart Grid solution with energy management

system.

Due to the difference in voltage level of PV panels and the battery bank, each are shown with

its own converter, in practice those can be of similiar topology. An inverter will be used to switch the

common DC link voltage to grid voltage, an Energy Management System (EMS) will communicate

with the Smart Grid and enable an economic and secure electricity supply.

8


1.2 Problem formulation

To maximize the economic benefit and reduce the payback time of the system, a energy efficient

system is required. Based on that the problem is formulated as:

Design a high efficiency bidirectional DC-DC converter for battery storage

The requirements for this converter are:

• 3 kW.

• Common DC link voltage is 700V for grid connected.

• Target efficiency ¿ 95 at nominal power%.

• Criteria for the battery is based on Saft Synerion 48 E lithium-ion module, see more in Table

1.1

Table 1.1: Eletrical parameters of Saft Synerion 48 E[5].

Parameter Value Note

Voltage [V] 48 Norminal

Energy [Wh] 2200

Voltage window [V] 42 to 56

Discharge current [A] 40 Nominal

Charge current [A] 14 Norminal

Peak power [W] 1440 30 sec. at 20 C

1.3 Project limitations

Designing a converter is an iterative process and since the focus is to demonstrate a bidirectional

DC-DC converter with high efficiency, the first task is to analyze the power losses during power

processing. Based on that the topology which is most suited to fulfill the target efficiency will be

designed.

Due to time and resouces contraints, some further limitations are needed, those are:

• Switching with high frequency to reduce size of magnetic components.

9


• Operate in continuous-current conduction mode to reduce the losses.

• Minimum power output is 300 W.

• Using of eigth battery modules to reduces the convertion ratio and losses.

• Charging control of the battery bank is not addressed.

• The test will be carried out in the lab with a power supply and programmmable load.

The milestones of the project are listed below:

• Acquire knowlegde of high efficiency converter.

• Analyze losses.

• Design and build a bidirectional DC-DC converter with high efficiency (> 95%).

• Implement the control in the DSP TMS320F28335.

1.4 Report outline

Until now, the motivation has been mentioned. The problem formulation is formulated and the limi-

tation is presented.

In Chapter 2, a novel high efficiency bidirectional converter topology, which is using low voltage

switches in 700 V applications, is presented.

In Chapter 3, results from the thermal modeling in Plecs are presented.

In Chapter 4, the design and build of the converter.

Chapter 5 concludes the work which has been done.

Appendix provide the necessary materials for understanding the decision and realisation, which have

been moved to have the flow in the report

10

Chapter 2

Bi-directional DC-DC converters forbatteries

DC-DC converters are used to convert the unregulated DC input into a controlled DC output at a

desired voltage level. They are also referred as DC-choppers and can be considered as a DC equiv-

alent to an AC transformer with a continuously variable turn ratio. Like a transformer, it can be

used to step-down or step-up a DC voltage. Two converters can be recognized as the basic converter

topologies, namely; the boost converter and the buck converter[10].

Charger and discharger the energy to/from the batteries requires a converter with bidirectional

power flow. A simple boost is shown in Figure 2.1(a) and the buck topology in Figure 2.1(b) sup-

port only unidirectional power flow, this is due to the diode in the boost topology and the potential

different between input and output in the buck.

C2C1

L1

L1

S1

S2

D1+

Vin

-

L1

+

Vin

-

S1

D1

S1

C1

R

R

C1

L1

D1+

Vin

- RC1

S1

L1

+

Vin

- D1

S1

C1

R

Bat.

(a) The classical boost converter.

C2C1

L1

L1

S1

S2

D1+

Vin

-

L1

+

Vin

-

S1

D1

S1

C1

R

R

C1

L1

D1+

Vin

- RC1

S1

L1

+

Vin

- D1

S1

C1

R

Bat.

(b) The classical buck converter.

Figure 2.1: The boost and the buck converter.

CHAPTER 2 - Bi-directional DC-DC converters for batteries

Bidirectional power flow can obtain by back-to-back connected two unidirectional converters.

From Figure 2.1 each converter can be indentified to have an inductor (L1), a controlled switch (S1),

a diode (D1), a filter capacitor (C1) and a load (R). Thus some components can be utilised for both

topologies, if back-to-back connected is realised.

In Figure 2.2, a capacitor (C1) is added to filter/stabilise the input voltage and the diode (D1)

is replaced with the MOSFET (S2), where the intrinsic body diode is oriented in the same direction

as the rectify diode. See the circuit from left to right, this is a boost converter, where the body diode

of the MOSFET (S2) is replaced the rectify diode (D1). Because of the MOSFET (S2), this boost

converter is able to perform active rectification; by turn on this MOSFET. This can reduce the losses

during rectify period, which is not possible with a simple boost converter as shown in Figure 2.1(a).

Swap around the source and the load from Figure 2.2 and see the circuit from right to left, this

is indeed a buck converter; where C2 is now the input filter capacitor, the freewheeling diode (D1)

is replaced with the intrinsic body diode of the MOSFET (S1), L1 and C1 form a low pass filter.

By replade freewheeling diode with a MOSFET, this converter can perform active freewheeling and

thus reduce the losses during freewheeling period.

C2C1

L1

L1

S1

S2

D1+

Vin

-

L1

+

Vin

-

S1

D1

S1

C1

R

R

C1

L1

D1+

Vin

- RC1

S1

L1

+

Vin

- D1

S1

C1

R

Bat.

Figure 2.2: The proposed bidirectional DC-DC converter for batteries.

Table 2.1 sums up the properties of the mentioned converters.

Table 2.1: Properties of the converters.

Power flow Conversion Number of Active Active

components rectifify freewheeling

Boost Unidirectional Step up 4 No No

Buck Unidirectional Step down 4 No No

Proposed Bidirectional Step up/down 5 Yes Yes

Beside the differences of properties highlighted in Table 2.1, the proposed converter is the same

as the basic boost and the buck under respected mode. Thus the transfer ratio for the boost converter

under continuous-current conduction mode (CCM) is still valid and is as expressed in Equation 2.1

and as Equation 2.2 for the buck converter, where D is the percentage of on-time also known as duty

cycle.

Voutboost =Vin

1 −D[V ] (2.1)

12


Voutbuck= Vin ·D [V ] (2.2)

By CCM means, the inductor current never reach zero, this is sketched for a boost converter in

Figure 2.3 with arbitrary values.

Figure 2.3: Waveform of the inductor current over a switching cycle (Ts.

In order to maintain to operate in CCM, the inductor value can be deduced from Figure 2.3 to be:

Lboost =Vin

2 · ∆iL· Ts [H] (2.3)

Similiar can be done for the buck converter or find in litterature(s)[11] to be:

Lbuck =Vin − Vout

2 · ∆iL· Ts [H] (2.4)

It is desired to keep the current ripple small and thus operate in CCM, because the peak current

is not differ to much from the average, thus reduce the rated current of the inductor and semiconduc-

tors. This can reduce the size, cost and efficiency.

2.1 Dual phases bidirectional split converter

The idea of merger the boost and the buck; boost-buck converter, to obtain bidirectional converter for

charge and dicharge the batteries has been introduced in the previous section. Based on this merged

converter, this section justify the design of a converter, which can fullfil the target efficiency best,

thus this converter design will be modelled and build to validate the high efficiency.

To have high efficiency is by means reduce the losses, this tool is introduced in Appendix A.

2.1.1 Select of semiconductors

To have low losses, based on the analysing in Appendix A, a MOSFET with low Drain-Source on-

resistance (RDSon) is needed to reduce the conduction loss, at the same time this MOSFET must

13


have low input capacitance to reduce the switching loss.

The DC link voltage is 700V and a safety margin should be added for the require MOSFET.

Compound of silicon and carbon have give a material (SiC; silicon carbide) which has pushed the

limit of blocking voltage and other advantages to semiconductors. SiC MOSFETs at 1200V is com-

mercial avaiable, which can be used to realise the boost-buck converter, but the price is extremely

high.

Alternative is using Super junction CoolMOSTM . The arguments when CoolMOS is presented

are: The on-resistance of MOSFETs are normally increased with higher blocking voltage, but in

Super junction CoolMOS devices this ”silicon limit” is overcome, where the square-law dependency

between blocking voltage and on-resistance is amended and a very low RDSon· Qg gives low con-

duction, driving and switching losses [12]. .

CoolMOS C3 series is avaiable up to 900V , but the switching charateristics are not suited for

fast switching. Furthermore they are only tested to 600V, which cannot guarantee anything at 700V .

One way to overcome this challenge is by split the 700V DC link into two parts; one for +350V

the other for −350V and use 600V/650V devices as shown in Figure 2.4.

C2C1

L1

L1

S1

S2

D1+

Vin

-

L1

+

Vin

-

S1

D1

S1

C1

R

R

C1

L1

D1+

Vin

- RC1

S1

L1

+

Vin

- D1

S1

C1R

Bat.

CP CoolMOS

SiC schottky

barrier diode

SiC schottky

barrier diode

C2C1

L1

S2

S1Bat.

C1

S3

S1Bat.

S4

S2Bat.

L2

L1

C2

C3

C4

Load

Figure 2.4: The bidirectional split converter(BSC), where lower blocking voltage switches are utilised.

The split converter has an internal common reference, but the DC link voltage will be the con-

nect between +350V and −350V , thus 700V can be obtained.

Super junction CoolMOSTM below 700V (650V ) exist in larger number, one of the most attractive

series is the latest generation, CFD2; where the fast body diode is integrated. The advantage of

choosing a integrated fast body diode is not only reduce the switching loss, but also enable active

rectify and freewheeling, which can increase the efficiency as mentioned in the beginning of the

chapter.

Due to problem with purchase of IPx65R110CFD[13] and other CDF2 devices, which are not

avaiable at RS components or Farnell or Mouser or Digikey. The selected device is from an earlier

generation; CP series. IPW60R099CP [4], which has similiar specifications, except the built-in fast

body diode.

To eliminate the drawback from the slow body diode in the selected device, a SiC schottky

diode (SCS120AG)[14] is added in serie with MOSFET to block the body diode and another SiC

schottky barrier diode is connected in parallel with the MOSFET and blocking diode, to takeover the

functionality of the body diode. The connection of this modification of the CP device can be seen in

14


Figure 2.5.

C2C1

L1

L1

S1

S2

D1+

Vin

-

L1

+

Vin

-

S1

D1

S1

C1

R

R

C1

L1

D1+

Vin

- RC1

S1

L1

+

Vin

- D1

S1

C1R

Bat.

CP CoolMOS

SiC schottky

barrier diode

SiC schottky

barrier diode

Figure 2.5: Modification of CP device with two SiC diodes to block the slow body diode and improve the

switching charateristics.

SiC diodes is well known for theirs extremely fast reverse recovery time due to extremely low

recovery charge and this extends the switching frequency limit of hard switching. The limitation of

this modification as shown in Figure 2.5 is; this cannot perform active rectify/freewheeling due to the

block diode. Furthermore should be mentioned, that add-on with SiC diodes will increase the total

price of components, but the modification is an engineering necessity to fulfill the target efficiency

and overcome the problem with purchase of CFD2 devices.

To summarise the devices which are mentioned above, some of the most importance characteris-

tics behind the decision of the switch are shown in Table 2.2. The table is shown for the modified

IPW60R099CP, instead of the IPW60R099CP. Some of the values can be read out directly from the

datasheets while others have to be computed as the case of the modified CP. Be to fair, the devices

have approximate the same current capability.

15

CH

AP

TER

2-B

i-directionalDC

-DC

convertersforbatteries

Table 2.2: Comparision of parameters between 1200 V SiC MOSFET with IPW65R110CFD and the modified CP device.

Characteristic CMF10120D[15] IPW65R110CFD Modified Note

(IPW60R099CP + SCS120AG)

VDS 1200V 650V 600V

RDSon220 mΩ 110 mΩ 110 mΩ Max.

@ ID = 10A @ ID = 12.7A @ ID = 18A @ Tj = 25C

Qg 47nC 118nC 60nC Typ.

@ VDD = 800V , ID = 10A @ VDD = 480V , ID = 19.1A @ VDD = 400C, ID = 19A @ VGS = 10V

Ciss 1000pF 3240pF 2800pF VDD = 175V

Coss 100pF 90pF 130pF + 110pF = 240pF VDD = 175V

Crss 10pF 10pF 2.2pF VDD = 175V

VF 3.5V 0.9V 1.5V Typ.

@ IF = 5A @ IF = 19.1A @ IF = 20A @ Tj = 25C

trr 138ns 150ns 19ns Typ.

@ IF = 10A, diFdt = 100A/µs @ IF = 19.1A, diFdt = 100A/µs @ IF = 20A, diFdt = 380A/µs @ VR = 400V

Qrr 94nC 800nC 35nC Typ.

@ IF = 10A, diFdt = 100A/µs @ IF = 19.1A, diFdt = 100A/µs @ IF = 20A, diFdt = 380A/µs @ VR = 400V

16


The characteristics in Table 2.2 are important regarding to power losses performance, which are

detailed in Appendix A.

2.1.2 Boost and filter inductor

Inductor design is very challenges, beside obtain the require inductance, it all started with select the

proper core, choose the operation point so the maximum flux density must not saturate the core,

limit the ac flux density so the core losses is acceptable, choose the right wire so winding losses is

acceptable low and so on. Those design steps can be seen in Appendix B.

Design inductor with high saturation flux density core material reduces the airgab, number of

turns and the physical core size. Reduce the number of turns will decrease winding losses, which

is an important factor of this converter. Due to problem with purchase high saturation flux density

core, as consequence a Ferrite core is used. The used ETD39 N87 core from Epcos is saturated

around 0.4T at 25C, where Kool Mu goes to around 1.5T . As the consequence, the stored energy

is divided into two and realise the BSC with two interleaved boost-buck. To reduce the winding loss,

the inductance is reduce to a half (800uH) and the frequency is doubled (200kHz).

Based on the equations (in theory) in Appendix B a 1.6mH inductor can still be obtained on the

same core, by double the number of turns and increase the four double the airgab to almost 6mm.

Whenever the ETD39 core can handle for power density in practice is another question and 6mm

airgab is quite large (which contribute to EMI problems).

To reduce the influence of 200kHz switching on losses, litz wire with 2/3 of skin depth is used.

2.1.3 Interleaved dual phases bidirection split converter

In total this interleaved dual phases bidirectional split converter (IDPBSC) has four inductors; two

in +350V and two in −350V as shown in Figure 2.6.

C2C1

L1

L1

S1

S2

D1+

Vin

-

L1

+

Vin

-

S1

D1

S1

C1

R

R

C1

L1

D1+

Vin

- RC1

S1

L1

+

Vin

- D1

S1

C1R

Bat.

CP CoolMOS

SiC schottky

barrier diode

SiC schottky

barrier diode

C2C1

L1

S2

S1Bat.

C1

S3

S1Bat.

S4

S2Bat.

L2

L1

C2

C3

C4

Load

S2

S1

S3

S1

S4

S2

L2

L1

C2

C3

C4

Load

Bat.

Bat.

C1

Bat.

L1

C1 C2

S2

S1

S7

S5

L1L3

S8

S6

L4

Figure 2.6: Interleaved dual phases bidirectional split interleaved converter (IDPBSC).

As the advantage compare to BSC the current in IDPBSC is reduced by a factor of two, but

switching frequency, number of semiconductors and inductors are doubled.

17


The question is, which converter fulfill the target efficiency best?

To answer this question, based on the analytic calculation (from Appendix A) losses is calcu-

lated for the boost mode, where Vin = 168V and the duty cycle D = 0.52. Table 2.3 presents the

power losses from the Boost-buck, BSC and IDPBSC. As a comment to the table, active rectify is

not addressed, because the BSC and IDPBSC is calculated with the modified CP, where this function

is not possible. Furthermore series resistance in the boost inductor in case of Boost-buck and BSC

is assumed to be the double (because double inductance compare to IDPBSC). The MATHCAD file

used to generate the table can find in the attached CD.

Table 2.3: Power losses in Boost-buck, BSC and IDPBSC.

Converter type Plosses Plosses Plosses Plosses Efficiency

MOSFET Diode Inductor Total

Boost-Buck 35W 19.2W 47.5W 101.6W 96.613%

with CMF10120D

BSC 2 · 19.3W 2 · 3.8W 2 · 47.5W 141.1W 95.297%

with modified CP

IDPBSC 4 · 13.6W 8 · 2.4W 4 · 5.94 97.4W 96.766%

with modified CP

From Figure 2.3 it can be seen, that the power losses in IDPBSC is lowest (97.4W ), next is the

Boost-buck which differ 4 W and last the BSC with 141W . It should be mentioned, that the power

losses in the inductor for the case of Boost-buck and BSC, is under the assumption of the same core

can be used, but the airgab is 6mm and can caused serious electromagnetic interference. All the

converters above fulfill the efficiency target, but the IDPBSC show the best result. Based on the

mentioned comments, the IDPBSC will be modelled and build to verify the target efficiency.

18

Chapter 3

Thermal modelling with PLECS

In the previous chapter the analytic calculation has shown, that the IDPBSC has the highest ef-

ficiency. In this chapter the IDPBSC is modelled in boost and buck mode with lowest input voltage;

±168V and highest input voltage; ±224V , where the load varies discrete from 300W to 3000W

and the efficiency at the egde of operation point will be recorded.

Based on the datasheets of the semiconductors and the application note[16] the loosses look

up tables for PLECs are constructed. For correction the reverse recovery energy is substracted from

the turn-on energy loss of the MOSFET, because the body diode of the MOSFET is blocked by the

blocking diode. This energy is calculated as:

EQrr =1

4·Qrr · Vrr [J ] (3.1)

The reverse recovery charge can be read out from the datasheet.

CHAPTER 3 - Thermal modelling with PLECS

3.1 Modelling of the boost part of the converter

In Figure 3.1 a screen is shown the modelled converter in boost mode. A thermal heat sink is

overlap the semiconductor devices and by using Plecs probe, conduction and switching losses can

be read out. By using the provided losses averaging model from my supervisor, the power losses can

be read out.

Heat Sink1

Heat Sink2

C1C: 470e-6v_init: 165

C2C: 470e-6v_init: 165

C3C: 470e-6v_init: 300

C4C: 470e-6v_init: 300

V_dcV: Vdc

VVm1

A

Am1

Scope

R2R: 0.235

R3R: 0.235

R4R: 0.235

R1R: 0.235

L1L: Ls

L2L: Ls

Scope1

V_dc1V: Vdc

VVm2

VVm3

PulseGenerator

**

Product

S1

S1

S2

S3

S4

S3

S2

S1

S2

S5

S4

V +

V -

IdcLink

V dcLink

IdcLink

V dcLink

V +

V -

PdcLink

IdcLink

V dcLinkPdcLink

delay PulseGenerator

TconstG2T: Tinit

Probe

T S1

Probe

T S2

Scope2

Thermal Chain

FETD D1

FETD2 D2

FETD1

D3

D4

D5

D6

D7

D8

R5R: RLs

R6R: RLs

L3L: Ls

S5

S7

FETD4 D9

FETD5

D10

D11

D12

R7R: RLs

L4L: Ls

S6 FETD6 D13

D14

D15

D16R8R: RLs

TconstG3T: Tinit

Thermal Chain1

S5

S7

S6

S8

0

Constant

S8

FETD7

S4

FETD3

Rload+R: Rload

Rload-R: Rload

DC-DC split converter for batteries Switching frequency: 200 kHz

Boost mode

Figure 3.1: Screen dump in PLECS of the modelled IDPBSC in boost mode.

Due to some transients in the converter, as shown in Figure 3.2 in boost mode at nominal load.

The power losses will first read out, when the converter seem to be stable.

Power losses is modelled and read out, but the power losses in the inductor is calculated as series

resistance (0.349Ω) time the average current square.

The efficiency plot for the converter in boost mode is plot in Figure 3.2. The lowest efficiency is

obtained when the input voltage is lowest and at nominal power. It is 97.06% in the simulation

and the analytic calculation in the previuos chapter shows 96.76 which only differ by 0.3%. The

explaination must be, since the added power lower of inductor is the same (calculated value), this

show that the formular used in the anaylitic calculation is not differ so much from how Plecs uses to

compute the losses.

20


Current

Voltage

top_voltage

bottom_voltage

Pout

2

3

4

5

6

200

400

600

800

1000

100

200

300

400

500

-500

-400

-300

-200

-100

0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.200

1000

2000

3000

4000

5000

Am1

Vm1

Vm2

Vm3

Product

Figure 3.2: The transient in the modelled converter.

The efficiency is decreasing with increase power output, this make sense because the current is,

thus power losses must increase as well.

0 500 1000 1500 2000 2500 30000.97

0.975

0.98

0.985

0.99

0.995

1

Power [W]

Effi

ency

[-]

Boost Vin 168VBoost Vin 224V

Figure 3.3: Efficiency plot in boost mode where solid blue line is for Vin = 168 and the solid green line is

Vin = 224.

According to Figure 3.2, the highest efficiency is obtained with highest at lowest power de-

manding and is more than 99%.

21


3.2 Modelling of the buck part of converter

Similiar is done for the buck converter and the efficiency is plotted in Figure 3.4. No analytic

calculations have been done, thus it cannot compare. The lowest efficiency is obtained with the

lowest input voltage and is 97.5%. The highest efficiency is 99.3% and was reached with 224V in

the input. Although the efficiency is really flat between 1kW − 3kW .

0 500 1000 1500 2000 2500 30000.97

0.975

0.98

0.985

0.99

0.995

1

Power [W]

Effi

cien

cy [-

]

Buck Vout 168VBuck Vout 224V

Figure 3.4: Efficiency plot in buck mode where solid blue line is for Vout = 168 and the solid green line is

Vout = 224.

To summerise, in this chapter a thermal model has been create in PLECs/SIMULINK. The re-

sult from the simulation has confirmed the analytical calculation, which gives the confident of the

target efficiency can be obtain. The next chapter will be about the pratical design og the converter.

22

Chapter 4

Converter design and practicalresults

Modelling the IDPBSC in previous chapter has justified analytic calculation of the efficiency. In this

chapter the practical design of converter is addressed.

The schematic can be found in Appendix ??.

4.1 Miscellaneous circuits

4.1.1 Sensing circuit

To monitor the voltage at the input and output for regulation, two voltage sensing circuits are im-

plemented. The battery voltage is downscaled with R8 and R9, through the buffer (U2A) the signal

will be send to the DSP. Furthermore the upper and lower threshold are detected by the comperators

build around U1A and U1B to perform a hardware shutdown (U26 and U27).

Similiar is done for the DC Link voltage and formed around U1C and U2B, where the voltage scal-

ing (R21 and R23) is different.

4.1.2 Current sensing

Four current sensing circuit is implemented; two for the battery input and two for the DC link. The

signal will be send to DSP for monitoring and perform power calculation of the converter. As in the

voltage sensing, the current sensing signal is also send to a onboard hardware protection (U26 and

U27).

All four sensing circuit is identical, the one belongs to battery input +350V is explained here.

To reduce the power losses a hall effect-based linear current sensor IC with 100µΩ current conduc-

tor is selected (ACS758[17]). This device is bidirectional and the sensitivity is 40mV/A. At zero

current this gives 2.5V . Through U3A and the R29 and R28, the signal is amplified to 100mV/A.

CHAPTER 4 - Converter design and practical results

A voltage divide (R25 and R30) is implement so the voltage will never go more than 3V and this

signal is send to the DSP. The downscaled signal is also used for hardware detection (U3C and R37)

to perform a hardware shutdown (U26 and U27).

4.1.3 Gate drive

A small gate resistor will charge the input capacitance to the threshold voltage faster and thus

reduce the transient time during switching, but to have control of dv/dt and di/dt, gate resistor value

is recommend in the application note for CP CoolMOS[16]. For dv/dt < 50V/nS the recommend

gate resistor should not be lower than 15Ω. Beside the built-in 1.3Ω gate resistor, an external 33Ω is

used during switch on and through a diode two parallel 33Ω will be used during switch off. The total

gate resistance is approximate 10 times more than specified in datasheet for switch on and 5 times

more during switch off, thus similiar scaling can expect for total switch on time (turn on delay + rise

time) and switch off time (turn off + fall time), this gives 150ns and 325ns respectively.

To switch on the MOSFET in 150ns, the gate charge (Qg) of 80nC has to be pumped in, this

gives a peak current of:

igatepeak=

80 · 10−9

150 · 10−9= 0.54 [A] (4.1)

To improve the immunity during switch off, the gate driver is feeded with ±12V .

The power losses in the gate driver can be calculated as[18]:

Pgate = Vgs ·Qg · fswitching = 24 · 80 · 10−9 · 200 · 103 = 0.348 [W ] (4.2)

Based on Equation 4.1 and 4.2 and 2.5Apeak gate driver (HCNW3120[19]) is selected.

4.1.4 Output filter capacitor

Beside fulfill the DC voltage (with some margin) the capacitor has to fulfill the current ripple from

the converter. The maximun current ripple is equal the peak current of the boost inductor. In this

converter it is 4.65, thus a margin should be added. The maximum current ripple that the selected

electrolyt capacitor can handle can be calculated as[20]:

Irippel =

√f · a2 · b2

100 · (b2 − a2) + (f · a2)[A] (4.3)

where:

a is current ripple at 100 Hz

b is current ripple at 10 kHz and

f is frequency in Hz

This gives 7.39A for 200kHz.

24


4.2 Protection

To keep the converter operating, all possible scenario that could kill the converter should be ad-

dressed and a solution should be implement to prevent it happens, this is called protection in this

report. Inrush current control and short circuit current limiting is not mentioned here, because the

converter will be feeded from power supply.

4.2.1 Gate and drive protection

To protect the gate drive circuit from any spike, which might enter from drain dv/dt, it is recommend

to use ferrie beads[16].Furthermore a bidirectional TVS is added over gate-source to supress any

possible transient, which exceed the maximum gate-source voltage.

4.2.2 Heat sink

In order to keep the semiconductor within the maximum allowed temperature, the generated

heat must be take away, either active or passive. An electrical analog of the thermal process is shown

in Figure 4.1.

Rjc Rcs Rsa

P

Tj Tc Ts Ta

D

Figure 4.1: Electrical analog of the thermal process.

In the figure above, PD is the heat source, Tj is the junction temperature, Tc is the case tem-

perature, Ts is the heatsink temperature, Ta is the ambient temperature, Rjc is the junction to case

thermal resistance, Rcs is the case to heat sink resistance and Rsa is the heat sink to ambient resis-

tance.

The maximum allowable power dissipation is [21]:

PD =Tjmax − Ta

Rja[W ] (4.4)

Thus Rja must be:

Rja <Tjmax − Ta

PD[K/W ] (4.5)

There are two heat sinks on the converter, one for the positive and the other for the negative. All 12

semiconductors will share the same heat sink, thus the heat sink should selected based on the worst

25


case power dissipation. Based on Table 2.3, the MOSFET dissipate most; 13.6W .

Assume the Ta = 50C. Tjmax = 150C and thus Rja is:

Rja <150 − 50

13.6= 7.35 [K/W ] (4.6)

From Figure 4.1, Rja = 7.35K/W is included Rjc of 0.5K/W from the datasheet and 1K/W

for the thermal insulation pad. Themal selected heat sink is of type PR118/94/SE/M3[22] which has

3.2K/W .

4.2.3 Thermal sensing

In the prototype two temperature sensors; LM35[23] (U28 and U29) are implemented, one for each

heat sink. The potentiometer R81 determine the threshold temperature to trigger the hardware shut-

down.

4.2.4 Onboard protection

To handle the hardware shutdown, a programmable electrical erasable logic (PEEL) device is used

to form the protection hardware. The PEEL22CV10[24] up to 22 inputs and ten outputs. The ben-

efite of programmable gives the flexibility, if something have to be addon or modify. Beside the

mentioned hardware shutdown above, this onboard protection prevents gate signals to perform cross

conduction of switches.

4.3 Practical works

After running the first PCB (version 1), some problems are observed. In Figure fig:ringningboost

a 20MHz oscillation occurs and die out after 140ns, this was measured with a current 50MHz

current probe. The reverse recovery time of the SiC diode should be around 20nS. Furthermore the

turn off time is too slow, the gate resistor was 33Ω, thus this suspect a high Drain-Source parasitic

capacitance.

26


So I when home, think twice of what can be done, I realized that I have made a fundamental error, by

connect the SiC diode in parallel with the MOSFET without block the body diode. As blocking diode I used

the BYV29 schottky, the result can be seen in Figure 3. The ringing is still there, please pay attention to the

time, it dies out after about 140nS, the rise time of drain voltage is 1.2 uS, which is still slow.

Figur 3: Waveform after blocking the body diode.

Figure 4 is the result in buck mode, mounting the snubber again will not be a bad idea.

Figur 4: waveform in buck mode

Figure 4.2: Observed problem in boost mode; 140ns oscillation and too slow turn off time.

In buck mode, the problem is shown in Figure 4.3 when RC snubber is not connected; a ring-

ing of twice the input voltage occured, this must come from parasitic inductances and together with

parasitic capacitance resonate.

So I when home, think twice of what can be done, I realized that I have made a fundamental error, by

connect the SiC diode in parallel with the MOSFET without block the body diode. As blocking diode I used

the BYV29 schottky, the result can be seen in Figure 3. The ringing is still there, please pay attention to the

time, it dies out after about 140nS, the rise time of drain voltage is 1.2 uS, which is still slow.

Figur 3: Waveform after blocking the body diode.

Figure 4 is the result in buck mode, mounting the snubber again will not be a bad idea.

Figur 4: waveform in buck mode Figure 4.3: Observed problem in buck mode without RC snubber; high voltage ringing and slow turn off time.

These problem consider to be more than what cut and repair of the PCB trace can solve, so

another PCB (version 2) is built, but time could not allow to run version 2 and carry out the results.

This work is expected to continuous after the report submit.

Some of the improvement in version 2 is mentioned here.

4.3.1 PCB routing strategy

A good routing layout is an essential part of the converter design as this can improve the practical

performance of converter, especially in high frequency hard switching. Trace width should at least

27


fulfill IPC-2221 standard[25]. The strategies which have been used in version 2 of the PCB are:

Avoid routing gate, source and drain PCB track in parallel as much as possible, because this

will increase (parasitic) capacitances.

Keep the gate drive and its components close to the gate and use wide trace to avoid parasitic

inductances. This helps by using SMD components.

Use the identical layout for the two phases.

Use wide and short commutation path to reduce parasitic inductance.

Use start grounding so high current circulation is no affect small signal circuit.

Some of the applied strategy can be seen in Figure 4.4 and the

Figure 4.4: Section of PCB traces in version 2. where some routing strategies is visible.

4.3.2 Efficiency report

The setup to be carry on for testing the efficiency is shown below. This will be perform in openloop,

where to interlead signal from from function generators is feeded the converter and the efficiency

will be recorded at the same point as the losses modelling.

28


LOADDC Power

Supply

SPLIT

Converter

Function Generators

Figure 4.5: The sketch of laboratory setup for testing efficiency.

More to come...

29

Chapter 5

Conclusion and future work

In this report a novel high efficiency topology has been proposed, which can used low voltage

switches and manage bidirectional power flow. Due to the challenge of purchase, a modification

of switching device and topology is necessary in order to reach the high efficiency target. A method-

ology has been established to perform an analytic calculation of power losses. A thermal model in

Plecs has been created to predict the losses. As the result, the simulation confirms the analytical cal-

culations, the worst case efficiency is 97% at nominal power in boost mode and 98.3 in buck mode.

Taken into account of the obtained results, the converter has been designed and built to validate the

simulation model. Due to time constraint the practical work has been postponed to after the report

submit.

5.1 Future work

Beside verify the efficiency the control implementation with DSP can be done. Furthermore it can

be integrated in PV applications and perform field test. Improvement of the efficiency can be done

by using a high saturation flux density core or using other switches technology to perform active

rectify/freewheeling.

References

[1] Joergen S. Christensen. Future Perspectives - toward 2025 and 2050. Course materials: Future

Power System in Denmark, 2011. Slides can be found in the CD.

[2] ElectrocIQ. Smart PV inverters take over in 2014. Internet, Last visited:

20/1/2012. http://www.electroiq.com/articles/pvw/2011/july/

smart-pv-inverters-take-over-in-2014.html.

[3] Dansk Energi. Dansk elforsyning statistik 2008. Kailow Graphic A/S, 2009.

[4] infineon. IPW60R099CP. Internet, Last visited: 15/12/2011.

http://www.infineon.com/dgdl/IPW60R099CP_rev2.1.pdf?

folderId=db3a304412b407950112b408e8c90004&fileId=

db3a304412b407950112b42ca4c24745.

[5] SAFT. Synerion 48 E. Internet, Last visited: 06/12/2011. http://www.saftbatteries.

com/doc/Documents/stationary/Cube782/Synerion%2048E_en_0511_

protected.85909e38-2ce1-4e98-b311-c98206e602cb.pdf.

[6] European Commission Joint Research Centre Institute for Energy. PV Status Report 2011. First

edition.

[7] Energistyrelsen and Energinet.dk. Solceller - Dansk strategi. Internet, Last vis-

ited: 27/12/2011. http://www.ens.dk/da-DK/NyTeknologi/strategier/

solenergi/Documents/PV-strategi%20rev_final_A%20del%20I.pdf.

[8] Sustainablebusiness.com. Smart PV Inverters Will Dominate Market by 2015. Internet, Last

visited: 20/1/2012. http://www.sustainablebusiness.com/index.cfm/go/

news.display/id/22715.

[9] Cam Pham Adam Wronski Catalin G. Dincan, Bogdan-Ionut Craciun and Romasz Wakulski.

Residential micro grid system. Technical report, Department of Energy Technology, Aalborg

Universitet, 2009.

[10] Tore M. Undeland Ned Mohan and William P. Robbins. Power Electronics Converters, Appli-

cations and Design. John Wiley & Sons, Inc., third edition, 2003.

http://www.electroiq.com/articles/pvw/2011/july/smart-pv-inverters-take-over-in-2014.html

http://www.electroiq.com/articles/pvw/2011/july/smart-pv-inverters-take-over-in-2014.html

http://www.infineon.com/dgdl/IPW60R099CP_rev2.1.pdf?folderId=db3a304412b407950112b408e8c90004&fileId=db3a304412b407950112b42ca4c24745



http://www.saftbatteries.com/doc/Documents/stationary/Cube782/Synerion%2048E_en_0511_protected.85909e38-2ce1-4e98-b311-c98206e602cb.pdf



http://www.ens.dk/da-DK/NyTeknologi/strategier/solenergi/Documents/PV-strategi%20rev_final_A%20del%20I.pdf

http://www.ens.dk/da-DK/NyTeknologi/strategier/solenergi/Documents/PV-strategi%20rev_final_A%20del%20I.pdf

http://www.sustainablebusiness.com/index.cfm/go/news.display/id/22715

http://www.sustainablebusiness.com/index.cfm/go/news.display/id/22715

REFERENCES

[11] Robert W. Ericksion and Dragan Maksimovic. Fundamentals of Power Electronics. Springerns,

second edition, 2004.

[12] infineon. CoolMOS 900V. Internet, Last visited: 14/11/2011.

http://www.infineon.com/dgdl/CoolMOS_900V_Appnote_1_3.

pdf?folderId=db3a3043163797a6011637d4bae7003b&fileId=

db3a3043183a95550118548811474a80.

[13] infineon. IPW65R110CFD. Internet, Last visited: 13/11/2011.

http://www.infineon.com/dgdl/DS_IPX65R110CFD_2_61.

pdf?folderId=db3a3043156fd5730115c736bcc70ff2&fileId=

db3a30433004641301306abd8e2041b1.

[14] Rohm. SCS120AG. Internet, Last visited: 23/11/2011. http://www.rohm.com/

products/databook/sic/pdf/scs120ag.pdf.

[15] CREE. CMF10120D. Internet, Last visited: 14/11/2011. http://www.cree.com/

products/pdf/CMF10120D.pdf.

[16] infineon. AN-CoolMOS-CP-01. Internet, Last visited:

07/12/2011. http://www.infineon.com/dgdl/Aplication+

Note+CoolMOS+CP+(+AN_CoolMOS_CP_01_Rev.+1.2).pdf?

folderId=db3a304412b407950112b408e8c90004&fileId=

db3a304412b407950112b40ac9a40688.

[17]

[18]

[19]

[20] Kemet. ALS30/31 series. Internet, Last visited: 02/11/2011. http://docs-europe.

electrocomponents.com/webdocs/002e/0900766b8002e601.pdf.

[21] Adel S. Sedra and Kenneth C. Smith. Microelectronic Circuits. Oxford University Press, fourth

edition, 1998.

[22] Alutronic. Spezial-Kuhlkorper. Internet, Last visited: 25/11/2011. http:

//www.ixlogic.ch/Alutronic/Short%20Forms/Alutronic_Katalog_

Spezialkuehlkoerper.pdf.

[23] National semiconductor. LM35. Internet, Last visited: 02/12/2011. http://www.

national.com/mpf/LM/LM35.html.

[24] ICT. PEEL22CV10. Internet, Last visited: 20/03/2011. http://www.alldatasheet.

com/datasheet-pdf/pdf/149133/ANACHIP/PEEL22CV10A.html.

32

http://www.infineon.com/dgdl/CoolMOS_900V_Appnote_1_3.pdf?folderId=db3a3043163797a6011637d4bae7003b&fileId=db3a3043183a95550118548811474a80



http://www.infineon.com/dgdl/DS_IPX65R110CFD_2_61.pdf?folderId=db3a3043156fd5730115c736bcc70ff2&fileId=db3a30433004641301306abd8e2041b1



http://www.rohm.com/products/databook/sic/pdf/scs120ag.pdf

http://www.rohm.com/products/databook/sic/pdf/scs120ag.pdf

http://www.cree.com/products/pdf/CMF10120D.pdf

http://www.cree.com/products/pdf/CMF10120D.pdf

http://www.infineon.com/dgdl/Aplication+Note+CoolMOS+CP+(+AN_CoolMOS_CP_01_Rev.+1.2).pdf?folderId=db3a304412b407950112b408e8c90004&fileId=db3a304412b407950112b40ac9a40688




http://docs-europe.electrocomponents.com/webdocs/002e/0900766b8002e601.pdf

http://docs-europe.electrocomponents.com/webdocs/002e/0900766b8002e601.pdf

http://www.ixlogic.ch/Alutronic/Short%20Forms/Alutronic_Katalog_Spezialkuehlkoerper.pdf



http://www.national.com/mpf/LM/LM35.html

http://www.national.com/mpf/LM/LM35.html

http://www.alldatasheet.com/datasheet-pdf/pdf/149133/ANACHIP/PEEL22CV10A.html

http://www.alldatasheet.com/datasheet-pdf/pdf/149133/ANACHIP/PEEL22CV10A.html

REFERENCES

[25] the CircuitCalculator.com. PCB trace width calculator. Internet, Last visited:

02/11/2011. http://circuitcalculator.com/wordpress/2006/01/31/

pcb-trace-width-calculator/.

[26] Marco Purschel Dr. Dusan Graovac and Andreas Kiep. MOSFET Power Losses Calcu-

lation Using the Data-Sheet Parameters. Internet, Last visited: 19/12/2011. http://

www.btipnow.com/library/white_papers/MOSFET%20Power%20Losses%

20Calculation%20Using%20the%20Data-Sheet%20Parameters.pdf.

[27] Abraham I. Pressman. Switching Power Supply Design. McGraw-Hill, second edition, 1998.

33

http://circuitcalculator.com/wordpress/2006/01/31/pcb-trace-width-calculator/

http://circuitcalculator.com/wordpress/2006/01/31/pcb-trace-width-calculator/

http://www.btipnow.com/library/white_papers/MOSFET%20Power%20Losses%20Calculation%20Using%20the%20Data-Sheet%20Parameters.pdf



Appendix A

Methodology

During the power convertion of a converter, the input current has to flow through semiconductors,

inductor, filtering ect. before it is avaiable at the output. None of components are ideal, thus some

energy has been lost in each component. This appendix provides an analytic tool to estimate some

related losses of this converter. Power losses increases with the increased current and the high current

path in this converter is through semiconductors devices and boost/filter inductor.

A.1 Losses in the converter

A.1.1 Losses in semiconductors

Power losses in any components can be divided in three groups [26]:

• Conduction related losses; Pc.

• Switching related losses; Psw.

• Blocking/leakage losses Pl.

The conduction losses are represented by the energy lost in the device during the on-state.

The switching losses represent the energy losses which occur during the finite switching transient,

as the operating state of the switch is changed from on(off) to off(on).

The blocking losses is normal considered to be very small and can be neglected.

Thus the power losses can be approximated as:

Plosses ≈ Pc + Psw [W ] (A.1)

CHAPTER A - Methodology

A.1.1.1 MOSFETs

Conduction loss in MOSFETs[26]

The conduction loss in a MOSFET can be determined by using the Drain-Source on-resistance

(RDSon) and the current through the device. The on-resistance is depended on Gate-Source volt-

age (VGS), Drain current (ID) and junction temperature (Tj).

VGS is usually fixed, so the conduction loss of the MOSFETs can be computed as:

PcMOSFET= RDSon

(Tj) · I2Don[W ] (A.2)

MOSFETs are positive temperature coefficient devices thereby the conduction loss is also in-

creasing with temperature. To take the temperature into account, Equation A.3 can be used.

RDSon(Tj) = RDSonMax.

(25C) · (1 +α

100)Tj−25C [Ω] (A.3)

where:

RDSonMax.(25C) is the maximun value at 25C

Tj is the junction temperature of the operation point and

α is the slope between RDSonMax.(25C) and Tj .

The RDSonas function of temperature can be found in datasheet as shown for the case of

IPW60R099CP in Figure A.1, where the manufacture has plotted the typical and the maximun vari-

ation in the same plot.

35


9?E-'@'004?

& C;: ?>;?>.3,<,.>0<4=>4.= & C;/<,49 =: ?<.0: 9 =>,>0<0=4=>,9 .0

( =6W"- =L=L, [ Y + =L"`_#6W"( =, [ Y

E6G6B : I: G- @L@L E6G6B : I: G- @L@L

<,49 =: ?<.0: 9 =>,>0<0=4=>,9 .0 & C;><,9 =10<.3,<,.>0<4=>4.=

+ =L"`_#6W", [( = - @L@L 3 ( =6W"- @L@LP- =L=Ll7+l( =l+ =L"`_#^Ri

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Uqj fxj styj ymj sj | ufhpflj inrj sxntsxfwhhtwinslytU H S 755>26892FFigure A.1: RDSon as function of junction temperature for IPW60R099CP[4].

Instead of Equation A.3, an estimation can also be used by read out the worst case junction

temperature for this device, this is shown in Figure A.2 for different Gate-Source voltage (VGS) at

150C.

36

CHAPTER A - Methodology9?E-'@'004?

& C;: ?>;?>.3,<,.>0<4=>4.= & C;/<,49 =: ?<.0: 9 =>,>0<0=4=>,9 .0

( =6W"- =L=L, [ Y + =L"`_#6W"( =, [ Y

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+ =L"`_#6W", [( = - @L@L 3 ( =6W"- @L@LP- =L=Ll7+l( =l+ =L"`_#^Ri

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Figure A.2: RDSon charateristic for IPW60R099CP[4] at 150C.

Switching loss in MOSFETs[26][16]

Due to parasitic capacitance in the MOSFET; Gate-Source (Cgs), Gate-Drain (Cgd or Crss)

and Drain-Source (Cds), the switching dynamics are governed by charging and discharging those

capacitors through the gate resistor (Rg).

The switch-on waveform of the MOSFET is sketch in Figure A.3. Where VDD is the applied DC

bus voltage, ID is the Drain current and IF is the forward current of the body diode.

Figure A.3: Switch-on waveform of the MOSFET.

Through the gate resistor, the input capacitance (Ciss = Cgd+Cgs) is charged to the gate driver

37


voltage (Vgs). Once the voltage at the gate (Vgate) reachs Vplatue the output current will rise to IDon

and the current of the body diode is decreased, while voltage over Drain-Source is remained at DC

link voltage. This current rise time is called tri.

To switch off the diode, the stored minority carriers have to be removed, this is done during the re-

verse recovery time (trr). The MOSFET will absorb this recovery current and thus gives further loss.

After the reverse recovery time the Drain-Source voltage decrease from DC link voltage toward the

on voltage (VDS = IDon·RDSon

), this time periode is called voltage fall-time (tfu) and is governed

by the output capacitance (Cds). The energy losses during switch-on are the sum of losses during

the mentioned time constants and can be computed as:

EMOSFETon= VDD · (IDon

) · tri + tfu2

+Qrr · VDD [J ] (A.4)

The waveform during MOSFET switch-off is sketched in Figure A.4. The gate drive will dis-

charge Ciss through Rg . Once Vgate drops to Vplatue, VDS start rise to VDD. This voltage rise time

tru is determined as:

tru =Rg · Crss · VDDVplatue − Vgsoff

[s] (A.5)

Figure A.4: Switch-off waveform of the MOSFET.

Once VDS = VDD, Vplatue drops further due to dicharge of Ciss through Rg and in the mean

time IDon drops down to zero. This current fall time (tfi) is computed as:

tfi = Rg · Ciss · lnVplatue − Vgsoff

Vth − Vgsoff

[s] (A.6)

Both the threshold voltage (Vth) and the platue voltage (Vplatue) is specified in the datasheet.

38


The energy losses during switch-off can be found as:

EMOSFEToff= VDSoff

· (iDoff) · tru + tfi

2[J ] (A.7)

The power loss during switching can be expressed as:

PswMOSFET= (EMOSFETon + EMOSFEToff

) · fsw [W ] (A.8)

As the summary, to have low losses, the MOSFET should have low RDSon , low input capaci-

tance and low reverse recovery energy. LowRDSongives low conduction loss, low input capacitance

to reduce switching transient duration and thus switching loss and low reverse recovery energy, be-

cause this is an addition loss to the switching losses.

A.1.1.2 Diodes

[26] The conduction losses of the diode can be approximated by two terms, the average current

through a DC source represents the diode voltage at zero current and another source which is de-

pended on the dynamic resistance and the rms current through the diode, thus it can be expressed as:

PcDiode= VD0 · IFav +RD · I2Frms [W ] (A.9)

Theo zero curren voltage source and the dynamic resistance can be read out from the datasheet as

shown in Figure A.5 for the body diode of the IPW60R099CP device.

9?E-'@'004?

& C;2,>0.3,<20 : <A,</.3,<,.>0<4=>4.=: 1<0@0<=0/4: /0

- @L@L6W"* XReV( = EJAH: 9 ( ?6W"- L=L=#

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Figure A.5: Diode forward charateristics.

39


The energy loss during switching the diode is dominated by the turn-on energy (reverse recov-

ery energy) and can be found as:

EswDiode=

1

4·Qrr · VDrr [W ] (A.10)

where:

VDrr is the peak voltage during reverse recovery and

Qrr is the recovery charge.

A.1.2 Losses in the inductor

Two type of losses are usually addressed in inductor design, they are: winding losses and core losses.

Operate the converter in continuous-current mode operation with especially with small current rip-

ple (fraction of the full load), core losses can be neglected because only small part of B-H loop is

utilised.

The winding losses can be divided into two part; low frequency and the high frequency.

The low frequency loss is copper loss due to DC resistance (Rdc) in the conductor, which is[11]:

R = ρ · lbAw

[Ω] (A.11)

where:

ρ is the resistivity,

lb is the lenght and

Aw is the bare cross section.

The high frequency loss is due to eddy current and causes skin and proximity effect.

Skin effect is governed by the eddy current which oppose the primary ac flux in the conductor, as the

result, current density is not uniform distributed, but rather more concentrate on the surface than the

center of the conductor. Skin depth expresses the penetration depth and is:

σ =

√ρ

π · µ0 · f[m] (A.12)

where:

ρ is the resistivity in Ωm and

f is frequency in Hz.

As seen from Equation A.11, thicker conductor gives lowerRdc due to larger bare cross section,

but on the other hand if skin depth from Equation A.12 is not taken in to account, only fraction of

the conductor is utilised and the ac resistance (Rac) can be dominated. The relationship between dc

40


and ac resistance is as[27]:

RacRac

=π · r2

π · r2 − π · (r − σ)2[−] (A.13)

where:

r is radius of the conductor.

One way to overcome this challenge is by using multi stands wire also known as Litz wire. Litz

wire is multiple thin insulated copper wires which are bundled together, thus larger cross section

area can obtain without violate the penetration depth.

The proximity effect is similiar to skin effect, but coupled between the layers. By using Litz wire,

this loss can maitain low and not adresse here.

A.1.3 Others losses in the converter

Beside the power losses in the inductor and semiconductors during power processing, other losses

exist like in gate driver, filter capacitors and other type of circuits. Most of them are relative small

and can neglected, but one should be mentioned which can not be determined in forehand is the

snubber.

Due to parasitic inductance and capacitor caused by the phycial layout, energy can be stored in

the layout and create voltage transient during turn-off the switch, which gives more switching loss

than expected and the transient can be dangerous high and kill semiconductors. Snubber can be

used reduce the stress of semiconductor by either passive dissipate the energy or active recovery this

energy so the voltage limit can be fulfilled. It should also be mentioned that snubber is also used to

mimigate the EMI emission, but emission is not required for the prototype. As mentioned in Chapter

1, design converter is an iterative process, so the first iteration is used simple passive and aim for a

good PCB layout, some used layout tips can be found in [16].

41

Appendix B

Inductor design step by step

The operation voltage window of eight series connected battery modules is 336−448V . From Equa-

tion 2.1, the duty cycle of the boost converter can be expressed as:

Dboost = 1 − VoutboostVin

[−] (B.1)

Thus step up to 700V , the duty cycle window; D = 0.36 − 0.52. The nominal output current

at 3kW is:

IDClink=PDClink

VDClink

=3000

700= 4.29 [A] (B.2)

If the power converter is lossless, then the average input current at nominal power will be:

ILboost=IDClink

0.52= 8.25 [A] (B.3)

Similiar can be done for the buck converter by using Equation 2.2, the duty cycle of the buck

converter is:

Dbuck =Vin

Voutbuck

[−] (B.4)

Hence the window of duty cycle for the step down; D0.48 − 0.64.

The highest output current at 3kW of the buck converter is:

ILbuck=PDCbat.

VDCbat.

=3000

336= 8.93 [A] (B.5)

B.1 Inductor design

VDClink = 700[V ] (B.6)

CHAPTER B - Inductor design step by step

fsw = 200 · 103[Hz] (B.7)

Tsw =1

fsw= 5 · 10−6[s] (B.8)

Pmin = 300[W ] (B.9)

Pmax = 3000[W ] (B.10)

Rloadmin=V 2DClink

Pmin= 1633[Ω] (B.11)

Rloadmax=V 2DClink

Pmax= 163.33[Ω] (B.12)

Vbatmin = 4 · 42 = 168[V ] (B.13)

Vbatmax = 4 · 56 = 224[V ] (B.14)

Vout =VDClink

2[V ] (B.15)

Dmin = 1 − Vbatmax

Vout= 0.36[V ] (B.16)

Dmax = 1 − Vbatmin

Vout= 0.52[V ] (B.17)

To ensure CCM in dual phases split; I > ∆iL:

43


Lmin =Dmax · (1 −Dmax)2 ·Rloadmin · Tsw

2= 489.2µH [H] (B.18)

Lmax =Dmin · (1 −Dmin)2 ·Rloadmin

· Tsw2

= 602.1µH [H] (B.19)

∆iLmin =Vbatmax

2 · Lmax·Dmin · Tsw = 0.335 [A] (B.20)

∆iLmax =Vbatmin

2 · Lmax·Dmax · Tsw = 0.363 [A] (B.21)

K = 1 − 2 · LmaxRloadmin · Tsw

= 0.147 [−] (B.22)

Kcrit. = Dmax · (1 −Dmax)2 = 0.12 [−] (B.23)

Iloadmin=

PminVDClink

= 0.67 [A] (B.24)

Iloadmax =PmaxVDClink

= 4.286 [A] (B.25)

ILdcmin=

Iloadmin

1 −Dmin= 0.67 [A] (B.26)

ILdcmax =Iloadmin

1 −Dmax= 8.929 [A] (B.27)

ILmin= ILdcmin

− ∆iLmin = 0.335 [A] (B.28)

ILmax= ILdcmax

− ∆iLmax = 9.291 [A] (B.29)

44


Design from [11]:

Constraint 1: Maximum flux density

Imax =ILmax

2= 4.646 [A] (B.30)

Bmax = 0.34 [T ] (B.31)

µ0 = 4 · π · 10−7 (B.32)

n · Imax = Bmax ·lgµ0

[−] (B.33)

Constraint 2: Inductance

Lboost =µ0 ·Ac · n2

lg[H] (B.34)

Constraint 3: Winding area

Ku ·Wa ≥ n ·Aw (B.35)

Ku has been estimated by first wound the number of turns and estimate the windows fill factor

(Ku). Estimate to be 0.3.

Constraint 4: Winding resistance

ρcu25 = 1.724 · 10−6 [Ω −m]

ρcu100 = 2.3 · 10−6 [Ω −m]

The geometric data of the core is specified by the manufacture.

ETD34:

Ac = 0.97

MLT = 6

lg =µ0 · Lboost · I2max

B2max ·Ac

[m] (B.36)

45


n =·Lboost · ImaxB2max ·Ac

· 104 [m] (B.37)

Aw = 2.513 · 10−3 [cm2]

resitance = ρ · n·MLTAw

= 0.349 Kg ≥ ρ·L2boost·I

2max

B2maxresistance·Ku

= 0.111 This justify that ETD34 can

be used.

46

Appendix C

Schematics of the converter

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

V+

Battery under voltage

Battery over voltage

Battery voltage out of range

V potentiometer

V potentiometer

V potentiometer

Vcc

Vcc

Vcc

Vcc

Battery voltage

DC Link +

Vcc

Vcc

DC link voltage

DC link over voltage

0

0

0

0

0

0

0

0

0

0 0

0

0

0 0

0

0

0

0

Title

Size Document Number Rev

Date: Sheet of

<Doc> <RevCode>

Battery voltage detection

A3

2 7Tuesday, January 31, 2012

Title


Date: Sheet of

<Doc> <RevCode>


A3


Title


Date: Sheet of

<Doc> <RevCode>


A3


3V DSP Digital in

3V DSP Digital in

Upper threshold

Lower threshold

2V@+Vbat=224V

2.037V@DC Link + = 350V

Upper threshold

D13BAS218D13BAS218

C13100nC13100n

R202.2kR202.2k

R7

100k

R7

100k

C16100nC16100n

R91.2kR91.2k

C15100nC15100n

-

+

U1C

LM339

-

+

U1C

LM339

9

814

312

-

+

U2B

LM358

-

+

U2B

LM358

5

67

84

-

+

U1B

LM339

-

+

U1B

LM339

5

42

312

R104.7kR104.7k

R144.7kR144.7k

R224.7kR224.7k

R12

1k

R12

1k

R1510kR1510k

R131.5kR131.5k

C17100nC17100n

-

+

U1D

LM339

-

+

U1D

LM339

11

1013

312

R162.2kR162.2k

D14BAS218D14BAS218

R17

1k

R17

1k

-

+

U1A

LM339

-

+

U1A

LM339

7

61

312

R112.2kR112.2k

R231.2kR231.2k

R181.5kR181.5k

R8133kR8133k

R19

100k

R19

100k

-

+

U2A

LM358

-

+

U2A

LM358

3

21

84

C14100nC14100n

R21205kR21205k

Figure C.1: Battery sensing circuit.

CHAPTER C - Schematics of the converter

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

V+

Battery under voltage

Battery over voltage

Battery voltage out of range

V potentiometer

V potentiometer

V potentiometer

Vcc

Vcc

Vcc

Vcc

Battery voltage

DC Link +

Vcc

Vcc

DC link voltage

DC link over voltage

0

0

0

0

0

0

0

0

0

0 0

0

0

0 0

0

0

0

0

Title


Date: Sheet of

<Doc> <RevCode>


A3


Title


Date: Sheet of

<Doc> <RevCode>


A3


Title


Date: Sheet of

<Doc> <RevCode>


A3


3V DSP Digital in

3V DSP Digital in

Upper threshold

Lower threshold

2V@+Vbat=224V

2.037V@DC Link + = 350V

Upper threshold

D13BAS218D13BAS218

C13100nC13100n

R202.2kR202.2k

R7

100k

R7

100k

C16100nC16100n

R91.2kR91.2k

C15100nC15100n

-

+

U1C

LM339

-

+

U1C

LM339

9

814

312

-

+

U2B

LM358

-

+

U2B

LM358

5

67

84

-

+

U1B

LM339

-

+

U1B

LM339

5

42

312

R104.7kR104.7k

R144.7kR144.7k

R224.7kR224.7k

R12

1k

R12

1k

R1510kR1510k

R131.5kR131.5k

C17100nC17100n

-

+

U1D

LM339

-

+

U1D

LM339

11

1013

312

R162.2kR162.2k

D14BAS218D14BAS218

R17

1k

R17

1k

-

+

U1A

LM339

-

+

U1A

LM339

7

61

312

R112.2kR112.2k

R231.2kR231.2k

R181.5kR181.5k

R8133kR8133k

R19

100k

R19

100k

-

+

U2A

LM358

-

+

U2A

LM358

3

21

84

C14100nC14100n

R21205kR21205k

Figure C.2: DC link sensing circuit.

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

V+ IP+ V+ IP-

V- IP-V- IP+

DC Link+ IP+

DC Link- IP+

DC Link+ IP-

DC Link- IP-

V+ current

Battery current limiter

V- current

DC Link+ current

DC Link- current

DC Link current limiter

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC VCC

Title


Date: Sheet of

<Doc> <RevCode>

Current sensing

A2


Title


Date: Sheet of

<Doc> <RevCode>

Current sensing

A2


Title


Date: Sheet of

<Doc> <RevCode>

Current sensing

A2


40mV/A

100mV/A

Upper threshold

40mV/A

100mV/A

Upper threshold

40mV/A

100mV/A

Upper threshold

40mV/A

100mV/A

Upper threshold

40mV/A40mV/A

40mV/A40mV/A

R38

3k3

R38

3k3C20100nC20100n

C31100nC31100n

R26

10k

R26

10k

-

+

U7D

LM339

-

+

U7D

LM339

11

1013

312

R27

20.3k

R27

20.3k

U9ACS758

U9ACS758

IP+

4

IP-

5

VCC1

GND2

VIOUT3

C24100nC24100n

R54

3k3

R54

3k3

-

+

U7A

LM339

-

+

U7A

LM339

7

61

312

C28100nC28100n

R3910kR3910k

U6B

4072

U6B

4072

910

1112

13

147

U4ACS758

U4ACS758

IP+

4

IP-

5

VCC1

GND2

VIOUT3-

+

U3D

LM339

-

+

U3D

LM339

11

1013

312

R45

15k

R45

15k

U6A

4072

U6A

4072

23

45

1

147

R3330.1kR3330.1k

R3410kR3410k

R4415kR4415k

R40

10k

R40

10k

R53

3k3

R53

3k3

C18100nC18100n

R29

15k

R29

15k

R41

20.3k

R41

20.3k

R2815kR2815k

-

+

U3C

LM339

-

+

U3C

LM339

9

814

312

C21100nC21100n

C19100nC19100n

R5110kR5110k

R24

10k

R24

10k

-

+

U7B

LM339

-

+

U7B

LM339

5

42

312

C23100nC23100n

R5510kR5510k

R48

15k

R48

15k

U5ACS758

U5ACS758

IP+

4

IP-

5

VCC1

GND2

VIOUT3

R4630.1kR4630.1k

R3710kR3710k

R4715kR4715k

-

+

U3A

LM339

-

+

U3A

LM339

7

61

312

R5010kR5010k

R4930.1kR4930.1k

R42

10k

R42

10k

R25

20.3k

R25

20.3k

R43

20.3k

R43

20.3k

C30100nC30100n

R3030.1kR3030.1k

C26100nC26100n

C27100nC27100n

U8ACS758

U8ACS758

IP+

4

IP-

5

VCC1

GND2

VIOUT3-

+

U7C

LM339

-

+

U7C

LM339

9

814

312

C25100nC25100n

R3510kR3510k

C22100nC22100n

-

+

U3B

LM339

-

+

U3B

LM339

5

42

312

R36

3k3

R36

3k3

R32

15k

R32

15k

R3115kR3115k

R5210kR5210k

C29100nC29100n

Figure C.3: Current sensing circuit.

48

CHAPTER C - Schematics of the converter

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Vcc 5V

VccS5

Gate S5

Source S5

VccS7

Gate S7

Source S7

VccS3

VccS1

Source S1

Gate S1

Gate S3

Source S3

VccS5

Gate S5

Source S5

VccS7

Gate S7

Source S7

VccS3

VccS1

Source S1

Gate S1

Gate S3

Source S3

Title


Date: Sheet of

<Doc> <RevCode>

Gate drivers

A3


Title


Date: Sheet of

<Doc> <RevCode>

Gate drivers

A3


Title


Date: Sheet of

<Doc> <RevCode>

Gate drivers

A3


C67100nC67100n

U12

HCNW3120

U12

HCNW3120

NC1

Anode2

Cathode3

NC4 Vee 5

Vo 6Vo 7

Vcc 8

R87

10MHz Ferrite

R87

10MHz Ferrite

R86

470

R86

470

R78

10MHz Ferrite

R78

10MHz Ferrite

R77

10MHz Ferrite

R77

10MHz Ferrite

C5847uC5847u

D222P6SMB36AD222P6SMB36A

R57

33

R57

33

R69

33

R69

33

C5647uC5647u

C43100nC43100n

C71

100n

C71

100n

C68

100n

C68

100n

D207

Bat85

D207

Bat85

D205

Bat85

D205

Bat85


R56

33

R56

33

R68

33

R68

33

C62100nC62100n

U14

HCNW3120

U14

HCNW3120

NC1

Anode2

Cathode3

NC4 Vee 5

Vo 6Vo 7

Vcc 8

C4047uC4047u

C5047uC5047u

R76

33

R76

33

R67

10MHz Ferrite

R67

10MHz Ferrite

U22

NMA0512SC

U22

NMA0512SC

Vin1

GND2

NC3 -V 4

0V 5

+V 6

C6147uC6147u

C47100nC47100n


R82

33

R82

33

D206

Bat85

D206

Bat85

C59100nC59100n

C57100nC57100n

C4447uC4447u

R70

470

R70

470

C69

100n

C69

100nR81

33

R81

33

D201

Bat85

D201

Bat85

D203

Bat85

D203

Bat85

C33100nC33100n

C42

100n

C42

100n

U17

NMA0512SC

U17

NMA0512SC

Vin1

GND2

NC3 -V 4

0V 5

+V 6

U19

NMA0512SC

U19

NMA0512SC

Vin1

GND2

NC3 -V 4

0V 5

+V 6

R65

33

R65

33

C3247uC3247u

R85

470

R85

470

R62

10MHz Ferrite

R62

10MHz Ferrite

D202

Bat85

D202

Bat85

C37100nC37100n

C70

100n

C70

100n

C6647uC6647u

U23

HCNW3120

U23

HCNW3120

NC1

Anode2

Cathode3

NC4 Vee 5

Vo 6Vo 7

Vcc 8

U10

HCNW3120

U10

HCNW3120

NC1

Anode2

Cathode3

NC4 Vee 5

Vo 6Vo 7

Vcc 8

C5447uC5447u

R63

10MHz Ferrite

R63

10MHz Ferrite

R66

10MHz Ferrite

R66

10MHz Ferrite

R73

470

R73

470

R74

10MHz Ferrite

R74

10MHz Ferrite

C39

100n

C39

100n

R84

470

R84

470

R75

33

R75

33D219P6SMB36AD219P6SMB36A

U18

NMA0512SC

U18

NMA0512SC

Vin1

GND2

NC3 -V 4

0V 5

+V 6

C49100nC49100n

U15

NMA0512SC

U15

NMA0512SC

Vin1

GND2

NC3 -V 4

0V 5

+V 6

C38

100n

C38

100n


C51100nC51100n


C4847uC4847u

C53100nC53100n

R80

33

R80

33

U25

HCNW3120

U25

HCNW3120

NC1

Anode2

Cathode3

NC4 Vee 5

Vo 6Vo 7

Vcc 8

R58

33

R58

33

U21

HCNW3120

U21

HCNW3120

NC1

Anode2

Cathode3

NC4 Vee 5

Vo 6Vo 7

Vcc 8

C55100nC55100n

R61

33

R61

33

C4647uC4647u

U16

HCNW3120

U16

HCNW3120

NC1

Anode2

Cathode3

NC4 Vee 5

Vo 6Vo 7

Vcc 8

C64100nC64100n

R79

33

R79

33


U13

NMA0512SC

U13

NMA0512SC

Vin1

GND2

NC3 -V 4

0V 5

+V 6


R60

33

R60

33C52100nC52100n

C6347uC6347u

U26

NMA0512SC

U26

NMA0512SC

Vin1

GND2

NC3 -V 4

0V 5

+V 6

R83

470

R83

470

C4547uC4547u

C65100nC65100n

R59

33

R59

33

U24

HCNW3120

U24

HCNW3120

NC1

Anode2

Cathode3

NC4 Vee 5

Vo 6Vo 7

Vcc 8

R72

470

R72

470

C35100nC35100n

C6047uC6047u

D204

Bat85

D204

Bat85

C3647uC3647u

C41

100n

C41

100n

C3447uC3447u

D208

Bat85

D208

Bat85

U11

NMA0512SC

U11

NMA0512SC

Vin1

GND2

NC3 -V 4

0V 5

+V 6

R64

33

R64

33

R71

470

R71

470

Figure C.4: Gate drives .

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Thermal protection

Vcc

Vcc

Vcc

Temperatur threshold

Vcc

Vcc

Temperatur threshold

Vcc

00

00

0 0

Title


Date: Sheet of

PED4-1040, 2011 <RevCode>

Thermal protection

A4

7 7

Title


Date: Sheet of


Thermal protection

A4

7 7

Title


Date: Sheet of


Thermal protection

A4

7 7

Temperature threshold

10mV/C

10mV/C

R8210kR8210kC79

100nC79100n

D33

BAS218

D33

BAS218

C68100nC68100n

D32BAS218D32BAS218

U29

LM35/TO

U29

LM35/TO

VS+1 VOUT 2

GN

D3

C69100nC69100n

-

+

U30A

LM339

-

+

U30A

LM339

7

61

312

C70100nC70100n

R8110kR8110k

C71100nC71100n

U28

LM35/TO

U28

LM35/TO

VS+1 VOUT 2

GN

D3

-

+

U30B

LM339

-

+

U30B

LM339

5

42

312

Figure C.5: Thermal sensing circuit.

49

CHAPTER C - Schematics of the converter5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Gate S1Gate S2Gate S3Gate S4

Gate S5Gate S6Gate S7Gate S8

DC Link current limiter

Battery current limiter

Thermal protection

S1S2S3S4

S5S6S7S8

Battey over voltage

Vcc

Vcc

Title


Date: Sheet of

<Doc> <RevCode>

<Title>

A

6 7Wednesday, December 21, 2011

Title


Date: Sheet of

<Doc> <RevCode>

<Title>

A


Title


Date: Sheet of

<Doc> <RevCode>

<Title>

A


ThermalOver voltageCurrent limiterU27

22CV10A

U27

22CV10A

I/CLK1

VC

C24

GN

D12

I/O 14

I/O 15

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I2

I3

I4

I5

I6

I7

I8

I9

I10

I11

I13

D27LEDD27LED

U26

22CV10A

U26

22CV10A

I/CLK1V

CC

24

GN

D12

I/O 14

I/O 15

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I2

I3

I4

I5

I6

I7

I8

I9

I10

I11

I13

R78RR78R

R79RR79R

D28LEDD28LED

D31

DIODE

D31

DIODE

D30

DIODE

D30

DIODE

D29

DIODE

D29

DIODE

C67100nC67100n

D25

DIODE

D25

DIODE

D24

DIODE

D24

DIODE

D26LEDD26LED

D23

DIODE

D23

DIODE

C66100nC66100n

R80RR80R

Figure C.6: On board programmable protection circuit.

50