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High Level High Level Synthesis Synthesis

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Page 1: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

High Level High Level SynthesisSynthesis

Page 2: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip
Page 3: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

Tasks of the Tasks of the Designer/ManagerDesigner/Manager

These ideas apply to the design itself, must be reproduced in the chip

Page 4: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip
Page 5: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

Aspects of PipeliningAspects of Pipelining

Page 6: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip
Page 7: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

A view at the synthesis and designA view at the synthesis and design

You may optimize on focus of an aspect at one time

Page 8: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

The most important aspect of design is how you deal with time

Page 9: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

Dealing with space is the result of dealing with time

Page 10: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

Parameters of Parameters of designdesign

Page 11: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

FloorplanningFloorplanning

Page 12: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

Fighting complexityFighting complexity

Page 13: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

Example:Example: Partial Differential Partial Differential EquationEquation

Page 14: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip
Page 15: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

• 2 ALU/*• 1 ALU• 2 *

Earliest Deadline (ASAP)

ALU/*

*

*

Page 16: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

• Another ALU

Page 17: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

Hardware Solution Hardware Solution number 3number 3

• Slow and cheap

• 1 ALU and 1 multiplier

• 7 time steps

+

<

Page 18: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

ALAPALAP

ALU/*

* ALU

2 ALU/*

2 *

1 ALU

Page 19: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

There are free Integer Linear Programming Packages on the internet, you can buy one at PSU bookstore

Page 20: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip
Page 21: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

Harmony and Balance in DesignHarmony and Balance in Design

Page 22: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip
Page 23: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip
Page 24: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

The Kung Systolic Array as an example of The Kung Systolic Array as an example of high-level structural synthesis, universal high-level structural synthesis, universal

protypeprotype

• CAD tools:

• Simulation and visual simulation

• Code generation,

• Array design

• Optimization

Page 25: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

Spatial ComputingSpatial Computing

Page 26: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

Conclusion: Steps lead to Conclusion: Steps lead to designdesign

This year project is on Hough Transform

Page 27: High Level Synthesis. Tasks of the Designer/Manager These ideas apply to the design itself, must be reproduced in the chip

Problems for students to think about.Problems for students to think about.

• Recall and discuss examples of pipelining.• Ford’s pipelining and other metaphores from social life or

industry that may be used in high level and system design. (how many workers to speed-up mowing the lawn).

• How to implement a long convolution – think about all possible methods.

• Discuss how you can solve scheduling and allocation using graphs and moving their nodes vertically and horizontally. Use first the differential equation example, next generalize to new graphs.

• Relation of floor-planning and high level synthesis – a new perspective.

• Computing in space – one, two and three directions.• Discuss ray-tracing and other similar applications in which the

computer mimicks physics in space.


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