high level tools for low-power asic design - uni...
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1High-level EDA-tools for power-optimal ASIC designJuly, 2003
High Level Tools for Low-Power ASIC design
Arne SchulzOFFIS Research Institute, Germany
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2High-level EDA-tools for power-optimal ASIC designJuly, 2003
Overview
• introduction
• high level power estimation– µProcessors– ASICs
• tool overview– µProcessors– ASICs
• conclusion
• future work
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3High-level EDA-tools for power-optimal ASIC designJuly, 2003
Moores Law
• beating Moores Law
[Rab99]
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4High-level EDA-tools for power-optimal ASIC designJuly, 2003
„Trade-off“
Transistor
Gate
Register-transfer
Behaviour
Systemarchitecture
Simulation time
Accuracy
SPICE(some 100 pattern on small circuit)
e.g. SimpleScalar-based(some 100 M CPU instructions)
Abst
ract
ion
leve
l
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5High-level EDA-tools for power-optimal ASIC designJuly, 2003
Why High-Level?
• specification level impact analysis.
• first time right architecture.
• up to 75% power reduction in minutes.
• avoids design iteration down to RT or gates.
• saves up to months of design time.
high-level design flow
Standard design flow
no
C/C++ program
analysis & optimizaton
ok?
RT-level design
synthesis
gain: 75%time: minutes
yes
nono
gain: 30%time: minutes
ok?
gain: 15%time: days
design backend
final analysis
no
traditional design flow
Standard design flow
C/C++ program
architecture definition
memory optimization
datapath optimization
ok?
gain: 30%time: weeks
gain: 75%time: months
design backend
gain: 15%time: days
synthesis
design analysis, power estimation
RT-level design
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6High-level EDA-tools for power-optimal ASIC designJuly, 2003
Embedded Approach
trend to software development:• faster than hardware development• cheaper than hardware development• easier than hardware development• updates/fixes are possible (e.g. firmware-updates)• „off the shelf“ CPUs
high-level power estimation for µ-Processors
high-level power estimation for ASIC
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7High-level EDA-tools for power-optimal ASIC designJuly, 2003
Example SW Estimation Tool
AccuPower overview:• high level microprocessor power estimation tool• contains
– micro architectural simulators– library of VLSI layouts– power estimator
• based on SimpleScalar (MIPS-based ISA-simulator)• vendor: academic
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8High-level EDA-tools for power-optimal ASIC designJuly, 2003
Algorithmic Level Estimation
two different approaches:• quick synthesis to RTL net list
– complex and slow– inaccurate if synthesis result does not get close to final architecture
• internal information about applied synthesis tool necessary
• complexity analysis of control data flow graph (CDFG) representation– only transformation of algorithm into CDFG needed (compilation)– fast but less accurate– example: register power is computed by counting number of CDFG
edges between operations
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9High-level EDA-tools for power-optimal ASIC designJuly, 2003
Example: Quick Synthesis Approach
HyPE: Overview• Hybrid Power Estimation
• uses behavioural simulation and macro models for data path components
• three phases of estimation:- high level simulation
- calculation of data path modes
- statistical power estimation
• very high performance
• vendor: academic
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10High-level EDA-tools for power-optimal ASIC designJuly, 2003
ORINOCOORINOCO
GateGate--LevelLevel
Less Time to Low Power
Des
ign
Tim
eD
esig
n Ti
me RTRT--LevelLevel
System Architecture System Architecture DesignDesign
commercialcommercialestimation toolsestimation toolsavailableavailable
weeksweeks
daysdays
minutesminutes
Pow
er g
ain
Pow
er g
ain
90%90%
50%50%
20%20%
SpecificationSpecification
SynthesisSynthesis
??
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11High-level EDA-tools for power-optimal ASIC designJuly, 2003
ORINOCO Principle
ORINOCO DALEORINOCO DALEConstraints
•Voltage•Frequency•Timing (Critical Path Length)•Area (Number of resources)
Activity Data•Created by simulation/execution using „real world“ data input.
Activity Data•Created by simulation/execution using „real world“ data input.
Power•Clock•Interconnect•Controller•Functional Units•Register•I/O •Memory
Power•Clock•Interconnect•Controller•Functional Units•Register•I/O •Memory
Architecture•Allocation•Binding•Scheduling•Floorplan
Architecture•Allocation•Binding•Scheduling•Floorplan
Source Code•C/C++•SystemC
Source Code•C/C++•SystemC
Model Library•Created by:
ORINOCO RIO and ORINOCO BEACH
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12High-level EDA-tools for power-optimal ASIC designJuly, 2003
Example Estimation Result
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13High-level EDA-tools for power-optimal ASIC designJuly, 2003
Conclusion
• high-level power estimation: biggest gain is possible• academic approaches for high-level power optimisation –
leading edge of current research• embedded software power estimation still research topic• ASIC power estimation on lower levels: commercial tools
available (eg. Synopsys, Sequence, Cadence)• for higher levels first available tool: ORINOCO from
ChipVision
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14High-level EDA-tools for power-optimal ASIC designJuly, 2003
Future Work
• research at OFFIS (SAO-group)– new metrics (interconnect, area, timing)– improved models (IP, leakage)– software power estimation (µ-Processors, partitioning)
commercial exploitation atChipVision Design Systems