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High Performance Cognitive Radio Platform with Integrated Physical & Network Layer Capabilities

Bryan Ackland, Ivan SeskarWINLAB, Rutgers Universitybda@winlab.rutgers.eduseskar@winlab.rutgers.eduwww.winlab.rutgers.edu

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Dynamic Spectrum AllocationLarge, increasing demand for wireless servicesStatic frequency bands allocated to single service

Inefficient use of spectrumSlow, expensive political processLocally optimized incompatible solutions

FCC exploring alternativesISM & U-NII bands

Power and BW limitations to allow co-existenceSuccessful but quickly getting congested

Intelligent or “Cognitive” radios that adapt to local wireless environment

Improve spectrum efficiency and fairness

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Cognitive RadioProgrammable radio systems that adapt to:

Changing radio interferenceAvailability of nearby collaborative nodesChanging protocols & standardsApplication requirements

by modifyingFrequency, power, bandwidthModulation, coding, MACNetwork protocols

and coordinating with other cognitive systems to maximize spectral efficiency and fairness

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Cognitive Radio ImplementationTradeoff between flexibility, performance & power

“Moore’s Law” improvements in CMOS VLSI Implement some functions in SWUltimate goal: software radio??

Reality: some combination of HW, SW and reconfigurable logic

Silicon area efficiency

flexibility speed, power, cost

1 10 100 1000

Microprocessor DSP FPGA ASIC

A/D µP

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Programmable Wireless NetworksResearch Goals:

Investigate Cognitive Radio Strategies & Spectrum Sharing AlgorithmsExplore flexible, power efficient wireless architecturesDevelop board level platform for system prototyping & subsequent distribution to research community

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Project TeamWINLAB, Rutgers University

Bryan AcklandIvan SeskarD. RaychaudhuriChris Rose

GEDC, Georgia Institute of TechnologyJoy LaskarStephane Pinel

Wireless Res. Lab., Lucent Bell LaboratoriesTod SizerDragan Samardzija

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Platform GoalsDesign & build cognitive radio platform that is

High performanceHW & SW ProgrammablePhysical, baseband & network layer adaptableSupport wide range of spectrum sharing scenarios

Leverage today’s high performance off-the-shelf components to build experimental platform with maximum utility & flexibilityDemonstrate architectures and components that will enable low cost, low power, flexible integrated circuit implementations in near future.

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Spectrum Management: Problem ScopeSpectrumAllocation

Rules(static)

INTERNET

BTS

AuctionServer

(dynamic)

SpectrumCoordination

Server(dynamic)

AP

Ad-hocsensor cluster(low-power, high density)

Short-rangeinfrastructure

mode network (e.g. WLAN)

Short-range ad-hoc net

Wide-area infrastructuremode network (e.g. 802.16)

Dense deployment of wireless devices, both wide-area and short-rangeProliferation of multiple radio technologies, e.g. 802.11a,b,g, UWB, 802.16, 4G, etc.How should spectrum allocation rules evolve to achieve high efficiency?Available options include:

Agile radios (interference avoidance)Dynamic centralized allocation methodsDistributed spectrum coordination (etiquette)Collaborative ad-hoc networks

Etiquettepolicy

SpectrumCoordination

protocols

Spectrum Coordinationprotocols

Dynamic frequencyprovisioning

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Cognitive Radio: Design Space

Hardware Complexity

“Open Access”+ smart radios

Protocol Complexity(degree of

coordination)

ReactiveRate/Power

Control

ReactiveRate/Power

Control

AgileWideband

Radios

AgileWideband

Radios

Unlicensed Band

with DCA (e.g. 802.11x)

Unlicensed Band

with DCA (e.g. 802.11x)

InternetServer-based

SpectrumEtiquette

InternetServer-based

SpectrumEtiquette

Ad-hoc,Multi-hop

Collaboration

Ad-hoc,Multi-hop

Collaboration

Radio-levelSpectrumEtiquetteProtocol

Radio-levelSpectrumEtiquetteProtocol

StaticAssignmentStatic

Assignment

InternetSpectrumLeasing

InternetSpectrumLeasing

“Cognitive Radio”schemes

UWB,Spread

Spectrum

UWB,Spread

Spectrum

Unlicensed band +simple coord protocols

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Cognitive Radio: CapabilitiesSpectrum scanning & frequency agilityFast physical layer adaptation & power control to respond to changing local conditionsFlexible baseband & MAC switchable on a packet-by-packet basis (SDR) to provide interoperability with multiple radio technologiesCapable of higher layer spectrum etiquette or negotiation protocolsSimultaneous heterogeneous radio linksProtocol translation & routing to support heterogeneous and/or ad-hoc networks

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Cognitive Radio Platform

Separate sub-systems to simplify functional implementation & modification by students in experimental environment

FlexibleRF

FlexibleRF

FlexibleRF

Flexible Baseband

(SDR)

NetworkProcessor

(MAC+)

CR Strategy(host)

local drop

Flexible

Antenna

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Platform Partitioning

FlexibleRF

FlexibleRF

FlexibleRF

Flexible Baseband

(SDR)

NetworkProcessor

(MAC+)

CR Strategy(host)

Flexible

Antenna

A/D/A

A/D/A

A/D/A

Baseband & Network Processor Board(Rutgers & Lucent)

Antenna & RF Board(Georgia Tech.)

A/D/ABoard

(Rutgers)

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Agile Tri-band RF Front-endTri-band operation:

700-800 MHz2.40-2.48 GHz ISM band5.15-5.825 GHz ISM and UN-II bands

2 Transmit + 2 Receive channels for data + spectrum monitoring receiver20 MHz bandwidth on each channel tunable over band

Narrow band selection performed at baseband100mW transmit power (variable) per channelSensitivity & linearity to meet 802.11a

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Tri-band Agile Receiver

To baseband

A/D’s

tri-bandantenna

tri-bandVGA

~

tri-bandRX

20 MHz BWIF filter

Power detectionStandard identification

Tri-bandSensing

/Monitoring Unit

~

tri-bandRX

20 MHz BWIF filter

~

tri-bandRX

20 MHz BWIF filter

SWMATRIx

800 MHz2.4 GHz5.2 GHz

800 MHz2.4 GHz5.2 GHz

AgileTriband LNA + Agile High Q matching network

tri-bandantenna

SOC

SOP

~ Low-IF~150 MHz

I

Q

I

Q

Channel 1

Channel 2

I

Q

I

Q

I

Q

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Reconfigurable RFIC’s for Compact Intelligent RF Front-end

2

3

4

5

6

7

0.25 0.3 0.35 0.4 0.45 0.5 0.55

Band-IBand-II

Osc

illat

ion

Freq

uenc

y (in

GH

z)

Vtune (in V)

Switched-L Frequency Agile VCO

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Tri-band AntennasTriple-Broadband Antenna for handheld terminals- planar antenna structure- multi-band- broadband

PCB

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.51

2

3

4

5

VSW

R

Frequency (GHz)

Frequency Range (MHz): 810-1000 1600-2500 4000-6000VSWR: ≤1.5 Pattern (azimuth plane) : Omni-directional Non-omniPeak Gain (azimuth plane) : 0 dBi 3 dBiPolarization: MixedAntenna dimensions: 50 mm ×50 mm ×0.2 mm

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FR-4 Organic high density multi-layer

Reconfigurable CMOS RFIC

Multi-band/wideband

antenna.

RF Tx / Rx

RF-MEMS

Switch

Flexible baseband

L1

Out

VDD

C1

R3

R

Vgain

C4

C5

Vb

Q1

GND

GNDG

ND

Q3

R

GND

C2

C3

Q2

R2

GND

VDD

R1

L(active)

VDD

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.51

2

3

4

5

VSW

R

Frequency (GHz)

Reconfigurable CMOS RFICRF-MEMS Switch & Multi-band Antenna

GaTech System-on-Package

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Baseband & Network ProcessorInterface to multiple radio channelsReal time spectral analysisSupport comparison of HW & SW baseband solutionMAC, protocol conversion, SAR, routingData rates (total) up to 100 Mb/sSupport novel reconfigurable architectures in baseband and network layersClean partitions between Baseband, NP and CRSimple programming environment (not DSP)Fast reconfiguration time (~µs)

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MPC8260

TMS320C6701XC2V6000FPGA

Ethernet

Bell Labs Programmable Radio Platform

6M gates programmable logic2.5 Megabits DPRAM in FPGA144 dedicated multipliers

1 GFLOPS TMS320C6701280 MIPS MPC8260244 configurable I/O pins

MegarrayConnector-

244 ConfigurableI/O pins

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WINLAB Baseband Platform GV300

2 Virtex™-II FPGAs(XC2V3000) each with 256K x 18 ZBT SRAMs1 Spartan™-II FPGA for External Interface 1 Spartan™-II FPGA for Configuration Control USB interface Four 100 MHz 12-bit A/D and four 100 MHz 12-bit D/A channelsOn-board 100 MHz programmable clock oscillator32 Bit LVDS interface2M x 8 configuration FLASH

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BasebandFPGA

Virtex-494K logic cells160 DSP slices PowerPC

(RTOS)

NetworkFPGA

Virtex-494K logic cells

Soft RISC cores

SRAM(4MB)

SDRAM(128MB)

PowerPCPowerQuick III

600 MHz(LINUX)

DRAM(64MB)

64

EEPROM(config)

Baseband & Network Processor

Data, control & sensing to/from

RF front-end

Gig-E

USB-II

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Network Processor based onMultiple RISC Cores

PacketScheduler

(RISC) HeaderBuffer

Packet Buffer

(DRAM)

PacketProcessor

(RISC/reconfig)

PacketProcessor

(RISC/reconfig)

PacketProcessor

(RISC/reconfig)

LocalI&D

LocalI&D

ExternalDRAM

LocalI&D

to/from baseband

to/from CR host

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SW Development EnvironmentNeed efficient multi-user, multi-proc. compile & debug

Short learning curve for student SW developersLinux OS with Gnu tool chain

Open sourceModular: I/O drivers can be installed without kernel modification or rebootUser friendly development environment

Simulink models compiled to VHDL and/or C

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Milestones & Timeline

2-3 Cognitive Radio Scenario Demos*

SystemBaseband & Network Proc.RF Front-end

Integrated SIP/SOC agile tri-band radioY3 Q4

Y3 Q3

1. Board spin2. Baseline SW releaseY3 Q2

Y3 Q1

System Prototype based on:1. Lucent BB&NP2. Gatech Agile Radio

Prototype boards availableY2 Q4

Prototype Software Dev. Env.Y2 Q3

Agile prototype – mainly off the shelf –some custom components – full functionality

Y2 Q2

Y2 Q1

Proof of concept systemprototype based on:1. Existing WINLAB board 2. Gatech prototype

1. Component selection & schematics. 2. Software Specification

Initial prototype – off the shelf components – limited flexibilityY1 Q4

Detailed Architecture SpecificationY1 Q3

Result of HW (FPGA) and SW implementation studies

Detailed performance & interface specs (12/04)Y1 Q2

Y1 Q1

*Note: Further release of Cognitive Radio Boards to community contingent on separate funding