high speed differential signaling
DESCRIPTION
Liav Ben-Artzi, MarvellTRANSCRIPT
May 2, 2012 1May 2, 2012
High Speed Differential Signaling Interconnect Influence
‐Advanced Phenomena
Liav Ben‐Artsi
Marvell Israel (MISL) Ltd.
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Agenda
High speed signaling basics and basic phenomena
The impact of differential inner pair skew
Multiple reflections
Passive interconnect as a DCD amplifier
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The Serial Link ‐ Background
Target: To transmit serial data over a given interconnect and receive it with a desired BER.
We will discuss the following serial link related issues: Serial link data frequency content Serial link components and what influences them:– Tx driver– Interconnect – Receiver
InterconnectTx Driver
Receiver
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Frequency Content of a Serial Signal – Square Wave
An “ideal” square wave can be constructed of sinusoidal components of odd multiplications of the signal’s “main” frequency.
What is the frequency content of an 8‐10 encoded bit stream? Fastest symbol is 1010… Slowest symbol is constructed of 5 consecutive bits. First Harmonic resides between Fb/10 Fb/2 (there may be even lower frequencies corresponding to repeating data strings.)
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Frequency Content of a Serial SignalAn “Ideal” Interconnect
What interconnect will not change the signal shape except for the amplitude?
We said that:The serial data consists of different length of consecutive bits wide symbol frequency rangeEach symbol incorporates a set of sinusoidal frequencies
What would be the “ideal” interconnect description in the frequency domain?A flat insertion loss response over frequency with a constant group delay over frequency (linear phase)This interconnect is not practical
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The InterconnectA Well‐designed Physical Interconnect
• Due to physical characteristics of the material a “well designed” printed circuit board trace frequency response shows linear loss (in dbscale) and linear phase behavior.
• Frequency content of the first harmonic is from FB/(2*longest bit stream) to Fb/2 (Fb/10 to Fb/2 in 8‐10 encoding) ISI
• Other interconnect characteristics / phenomena will be discussed later in this presentation
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Introduction to Channel Theory (cont’d) Assuming a rectangular input pulse with a width of 200psec. Zoom in on the pulses at the end of a line with 5db, 16db and 26db @ 2.5GHz loss. Several phenomena can be observed:
Rise time degradation ‐Why?The decay phenomenon time increasesMaximum amplitude varies according to the interconnect loss.
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Interconnect Characteristics ‐ ISIWe have seen the signal degradation due to steeper channel loss.
Eye Diagram view 5db loss (@2.5GHz ‐bit time 200p 5GBPS).
Eye Diagram view 16db loss (@2.5GHz ‐bit time 200p 5GBPS).
Eye Diagram view 26db loss (@2.5GHz ‐bit time 200p 5GBPS).
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Interconnect Characteristics: ISI ‐ Remedies
We need to compensate for the higher frequencies loss (or attenuate the lower frequencies). This action is called Equalization.
Several types of equalization techniques (Eq) are available: Tx Eq and Rx Eq.
PE – Pre‐emphasis FFE – Feed Forward equalizationCTLE – Continues Time Linear Equalizer DFE – Decision feedback equalizer
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The Serial Link – Advanced Phenomena
The impact of differential inner pair skew (the difference in delay between the positive and negative interconnect paths).
Multiple reflections – signal degradation due to the presence of multiple discontinuities along an interconnect and the main difference between a single reflection and multiple reflections.
Passive interconnect as a DCD amplifier – what happens to a signal that has a certain amount of duty cycle distortion when traveling through a high speed interconnect.
InterconnectTx Driver
Receiver
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If the interconnect has a 10psec skew between p and n trace, what will be the amount of added jitter?
Will there be any other effects to the inner pair skew?
Phenomena such as susceptibility to Xtalk and EMI are not discussed in this presentation.
The analysis assumes very loosely coupled traces.
Differential inner pair skew
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Looking at the impact of skew on differential harmonic signals one can observe that:
The main impact of skew would be seen on the signal amplitude. The larger the skew (in terms of UI) the larger the amplitude degradation.
The harmonic signal width is not influenced, rather the ideal sampling point is shifted.
Since high frequency symbols (such as 1010…) have small UI width, inner pair skew will degrade their amplitude by a larger amount compared to lower frequency symbols (such as 111000…). This will introduce ISI.
In the case of short reach interconnects, the signal may still have a portion of higher harmonies amplitudes signals rise/fall will be highly impacted.
Differential inner pair skew – Analysis
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Zero Skew Vs. 0.5UI Skew
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Reflections occur at every location of medium change along an interconnect.
Reflection and multiple reflections
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The reflected portion can be positive or negative
The transferred portion can only have non‐negative magnitudes
The transferred portion will accumulate phase as it advances through the reflecting object (such as a via, a trace with different impedance, etc.)
A wave advancing through an interconnect accumulates phase (the interconnect has a propagation delay).
An advancing wave may be attenuated with an amount related to the medium characteristics (dielectric loss coefficient, mechanical dimensions that influence the skin effect, copper surface roughness).
Advancing and reflected waves may interact forming interference (התאבכות) – This effect will occur only in the presence of more than a single reflection multiple reflections effect.
Reflections ‐ Observations
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Single reflections – simulated results
Differential via (G‐S‐S‐G) with via stubs (capacitive).
Traces de‐embedded.
Reflected signal has a ~180° shift (+ delay)
Transferred signal has a phase accumulation according to via delay.
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Multiple reflections – simulated results
Two Differential vias (G‐S‐S‐G) with via stubs structure.
Traces (lossless) connecting the two structures.
Reflected signal bounces back and forth to create interference.
Loss will lower the interference amplitude.
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Multiple reflections – simulated results Multiple reflections causes transfer to introduce ripple (usually referred to as insertion loss deviation – ILD) – why?
The reason for optimizing return loss
Insertion loss
Return loss
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Duty Cycle is the ratio of the positive pulse duration to the pulse period.
The Ideal duty cycle is 50%.
Duty Cycle Distortion (DCD) is defined to be the deviation from the ideal 50%.
The average voltage of a 0% DCD differential signal is zero. The average signal voltage deviates from zero with the introduction of DCD baseline wander.
DCD increases with rise/fall time degradation.
An Interconnect as a Duty Cycle Distortion Amplifier
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Duty Cycle Distortion – Simulation results
Driver has a minimal pulse width of 86.8psec ‐ 10psec degradation due to DCD.
Signal at the interconnect Far‐End has a 16psec degradation due to DCD DCD was increased as a result of passing through the interconnect.
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