high-speed interconnection for vlsi systems using multiple

2296IEICE TRANS. INF. & SYST., VOL.E97–D, NO.9 SEPTEMBER 2014

PAPER Special Section on Multiple-Valued Logic and VLSI Computing

High-Speed Interconnection for VLSI Systems UsingMultiple-Valued Signaling with Tomlinson-Harashima Precoding

Yosuke IIJIMA†a), Member, Yuuki TAKADA††, Nonmember, and Yasushi YUMINAKA†††, Member

SUMMARY The data rate of VLSI interconnections has been increas-ing according to the demand for high-speed operation of semiconductorssuch as CPUs. To realize high performance VLSI systems, high-speed datacommunication has become an important factor. However, at high-speeddata rates, it is difficult to achieve accurate communication without bit er-rors because of inter-symbol interference (ISI). This paper presents high-speed data communication techniques for VLSI systems using Tomlinson-Harashima Precoding (THP). Since THP can eliminate the ISI with limitingaverage and peak power of transmitter signaling, THP is suitable for imple-menting advanced low-voltage VLSI systems. In this paper, 4-PAM (Pulseamplitude modulation) with THP has been employed to achieve high-speeddata communication in VLSI systems. Simulation results show that THPcan remove the ISI without increasing peak and average power of a trans-mitter. Moreover, simulation results clarify that multiple-valued data com-munication is very effective to reduce implementation costs for realizinghigh-speed serial links.key words: high-speed interface, Tomlinson-Harashima precoding (THP),intersymbol interference, multiple-valued signaling, low-voltage VLSI sys-tems

1. Introduction

Demand for data rates beyond Gbps has been increasing inorder to manage the exponentially growing data traffic inVLSI communications. However, in such high-speed se-rial links, channel distortion such as inter-symbol interfer-ence (ISI) and noise significantly limit I/O bandwidth rela-tive to device performances. To avoid noise effects, efficienttransmission techniques using coding methods, such as MV-CDMA, have been proposed [1]. For high-speed data ratesat Gbps levels, the main difficulty is the equalization of sig-nal distortion due to loss of interconnections.

In VLSI systems, strip lines (SL) and/or microstriplines (MSL) are widely used as interconnections. How-ever, for high-speed data rates at Gbps levels, these inter-connections exhibit complex behavior that makes accuratetransmission of information difficult. The reason for thisbehavior is that the interconnections act as low-pass filters,because of the skin effect [2] and dielectric loss, which de-creases high frequency components of signals. Therefore,the waveform of transmitter signals is distorted at the re-

Manuscript received December 10, 2013.Manuscript revised April 11, 2014.†The author is with the Oyama National College of Technol-

ogy, Oyama-shi, 323–0806 Japan.††The author is with the Graduate School of Engineering,

Gunma University, Kiryu-shi, 376–8515 Japan.†††The author is with the Faculty of Science and Technology,

Gunma University, Kiryu-shi, 376–8515 Japan.a) E-mail: [email protected]

DOI: 10.1587/transinf.2013LOP0021

ceiver by passing through a bandwidth-limited interconnec-tion. The transformation introduces ISI, which causes biterrors because of the difficulty of 0/1 detection at the re-ceiver [3].

Several signal processing techniques for pulse shap-ing have been proposed to reduce ISI at the receiver. InVLSI systems, pre-emphasis or post-equalizers, such asDFEs (Decision Feedback Equalizer), are widely employed.The pre-emphasis can cancel the ISI at a transmitter by em-phasizing rising/falling edges of pulse shapes. These tech-niques are very effective for reducing ISI. However, it is wellknown that pre-emphasis suffers from increasing the peakand average power at a transmitter. If the characteristics ofa transmission line H(z) are known in advance, ISI can beeliminated completely using signal processing techniques,such as Tomlinson-Harashima Precoding (THP), which wasproposed in 1971 by Tomlinson [4] and Harashima [5], in-dependently. The THP has been applied mainly to wire-less communication systems and optical transmission sys-tems [6].

THP can remove the ISI that is contributed by the post-cursor of wave responses at a transmitter, and it can be real-ized by a digital filter that has a modulo-N adder. BecauseTHP can limit peak and average power of transmitter sig-naling by modulo-N arithmetic, it is suitable for implemen-tation in high-speed serial links for low-voltage VLSI sys-tems [7]. Recently, future memory link systems using THPin 22-nm silicon-on-insulator (SOI) CMOS have been pro-posed, and the advantages are clarified [8].

This paper evaluates high-speed data transmission overinterconnections in VLSI systems using MSLs and hard-ware cost of THP. In [9], authors have evaluated fundamen-tal performance of THP for electrical communication by us-ing coaxial cables. To estimate THP performance for high-speed serial links for VLSI systems in practical environ-ment, this paper discusses transmission performance that isbased on measurement characteristics of an evaluation boardof a MSL. Using this transmission line, 2-PAM (Binary) and4-PAM (4-valued) data communication are compared by anumerical simulation based on measurement results of thetest board. From these simulation results, the effectivenessof THP using multiple-valued signaling is discussed fromthe viewpoint of hardware costs.

In this paper, Sect. 2 provides measurement and simu-lation results for transmission characteristics of a MSL. InSect. 3, we provide simulations of a high-speed data com-munication on the MSL. In Sect. 4, we demonstrate the ef-

Copyright c© 2014 The Institute of Electronics, Information and Communication Engineers

IIJIMA et al.: HIGH-SPEED INTERCONNECTION USING MULTIPLE-VALUED SIGNALING WITH TOMLINSON-HARASHIMA PRECODING2297

Fig. 1 Dimension of the test board.

fectiveness of THP for high-speed serial links. In Sect. 5,we discuss the hardware costs of the THP implementation.Section 6 concludes our paper.

2. Evaluation of a Microstrip Line

To estimate transmission characteristics of VLSI intercon-nections, an evaluation board of a MSL is fabricated. Thelength of the evaluation board is 1 m, and the line is madeon an FR-4 substrate with assumption of VLSI interconnec-tions, such as backplane systems and serial memory linksystems. As shown in Fig. 1, the line width was designedto realize 50 Ω characteristics impedance [10].

2.1 Measurement of Frequency Characteristics of a MSL

Figure 2 shows the S21 parameter of the test board of a MSL1 m, which was measured using a vector network analyzer(Agilent E8357A). As shown in Fig. 2 (a), the attenuationincreased because of skin effect and a dielectric loss of MSL,so it behaves as a low-pass filter. Figure 2 (b) shows thatphase delay increases with frequency. Figure 2 (c) showsthe flat frequency characteristic of group delay.

As shown in Fig. 2 (a), the attenuation is −5.8 dB at1 GHz, and it corresponds to signal decay of 51.2% at areceiver. At 2 GHz and 5 GHz, attenuation are −10.4 dBand −26.3 dB, and these show that transmitted signals areattenuated to 30.2% and 4.8%, respectively.

2.2 Simulation of Time Domain Characteristics of a MSL

In order to simulate the time domain characteristics of theMSL, an impulse response is obtained from measurementresults of frequency characteristics. The impulse responseis calculated by using an Inverse Fast Fourier Transform(IFFT) of measured frequency characteristics. Figure 3shows the waveforms of impulse response of MSLs 1 m and2 m. As shown in Fig. 3, the attenuation and delay increasewith the length of a MSL, resulting in different waveforms.Using these impulse responses, transmitted signals at the re-ceiver can be calculated by a convolution of the impulse re-sponse and transmitter signals.

(a) Amplitude characteristics of S21

(b) Phase characteristics of S21

(c) Group delay of a MSL

Fig. 2 Measurement results of an S21 parameter of a MSL 1 m.

Fig. 3 Simulation results of impulse responses (MSLs 1 m and 2 m).

3. Simulation of High-Speed Data Communication onVLSI Interconnections

In this section, accuracy and validity of our simulation areshown. Also, ISI effects of binary signaling (2-PAM) and4-valued signaling (4-PAM) on VLSI interconnections aresimulated.


3.1 Evaluation of Numerical Simulation

The data symbols of binary (2-PAM) are 0 or 1. Figures 4and 5 show waveforms of transmitter signaling and receiversignaling at 2 Gbps and 5 Gbps data communication usingMSLs 1 m. The bits of 0 and 1 are mapped to the volt-age level −0.5 V and +0.5 V, respectively. This simulationfocuses on verifying the effects of ISI for high-speed datatransmission, so AWGN (Additive White Gaussian Noise)is not considered. The waveforms at a receiver are distorted,and the distortion is expanded depending on the increasingdata rate due to propagation loss. Figure 5 shows that sym-bol decision of 0 or 1 at a receiver becomes difficult at 5Gbps data rate due to the severe ISI.

To confirm these simulation results, the actual eye di-agram of the evaluation board is measured. As shown inFig. 6 (a), a pulse generator produces a random pulse patternof 0 or 1 which is applied to the MSL 1 m. Then, a samplingoscilloscope observes the transmitted waveform and drawsthe eye diagram. Figure 6 (b) is the actual measurement sys-tem. D3186 (ADVANTESET) and WaveMASTER 8500A(LeCroy) are used as the pulse generator and sampling oscil-loscope, respectively. Figure 7 is our numerical simulationresults using the measurement condition. Comparison of thesimulation results and experimental measurements (Fig. 8)indicates good agreement between the two.

Figure 9 shows the eye diagram of 2 Gbps in 1 m whichwas simulated by using a circuit simulator, Agilent ADS(Advanced Design System). The measured S21 parame-ter of the test board can be imported to a transmission linemodel in ADS simulation systems (Fig. 9 (a)). Comparing

(a) Waveforms of transmitter signals

(b) Waveforms at receiver side

Fig. 4 Waveforms of transmitter and receiver at 2 Gbps 2-PAM on MSL1 m.

of Fig. 9 (b) and Fig. 7, our numerical simulation method canobtain the same results. In the following sections, we evalu-ate THP in terms of hardware costs by using our numericalsimulation.

3.2 Binary Signaling Transmission on a MSL

Figures 10 (a)–(c) are simulation results of eye diagrams ofbinary signaling. As shown in Fig. 10 (a), the eye is openedat 2Gbps on 2 m MSL. Hence, the amplitude information0 or 1 can be detected by a threshold voltage as same asFig. 7. On the other hand, as shown in Figs. 10 (b) and 10 (c)at 5 Gbps, the eye is completely closed by ISI, resulting inbit error. The estimatied result of Bit Error Rate (BER) is

(a) Waveforms of transmitter signals

(b) Waveforms at receiver side

Fig. 5 Waveforms of transmitter and receiver at 5 Gbps 2-PAM on MSL1 m.

(a) Measurement system

(b) Actual measurement system

Fig. 6 Experiment measurement of eye diagrams.


Fig. 7 Numerical simulation results of eye diagrams of 2-PAM usingMSL 1 m.

Fig. 8 Measurement result of an eye diagram (data rare is 2 Gbps, x-axis:200 ps/div, y-axis: 200 mV/div).

(a) Simulation model using ADS

(b) Eye diagram of 2 Gbps signaling on MSL 1 m

Fig. 9 Simulation results by using ADS.

higher than 0.3, and it is hard to detect the information atthe receiver.

3.3 4-Valued Data Signaling Transmission on a MSL

In 4-PAM, the transmitter signals are 4-valued, which meansthat 4-PAM can transmit 2-bit (00/01/10/11) data simultane-ously. Therefore, 4-valued (4-PAM) signaling can represent2 bit information as one symbol using a 4-level signal, re-sulting in reducing data rates by half. Figures 11 (a) and11 (b) are eye diagrams of 4-PAM 2 Gsysmbol/s (sps) (cor-responds to binary 4 Gbps) data rate on MSLs 1 m and 2 m,respectively.

Although the ISI effect is enlarged according to the

(a) 2 Gbps data rate, 2 m length

(b) 5 Gbps data rate, 1 m length

(c) 5 Gbps data rate, 2 m length

Fig. 10 Simulation results of eye diagrams of 2-PAM using MSL.

(a) 2 Gsps (4 Gbps) data rate, 1 m length

(b) 2 Gsps (4 Gbps) data rate, 2 m length

Fig. 11 Simulation results of 4-PAM data transmission.

number of division of PAM, the eye is slightly opened at2Gsps in a MSL 1 m, and hence we can detect the data cor-rectly. However, the eye is completely closed in a MSL 2 m


because of severe ISI as shown in Fig. 11 (b), and hence bitdecision is difficult.

4. High-Speed Data Communication Using Tomlinson-Harashima Precoding

4.1 Tomlinson-Harashima Precoding Techniques

Because THP can limit peak and average power of trans-mitter signaling, it is suitable for implementation in high-speed serial links for advanced low-voltage VLSI systems.Up to now, to eliminate ISI effects at a receiver for achiev-ing high-speed interfaces, we have tried to apply Tomlinson-Harashima Precoding (THP) to data transmission for VLSIsystems [7].

Figure 12 illustrates a block diagram of THP circuitry.As shown in Fig. 12, THP can be achieved with a digitalfilter that uses a modulo-N adder instead of a conventionaladder. The modulo-N adder always has a magnitude be-tween −N/2 and +N/2. Consequently, the dynamic rangeof THP output is limited between −N/2 and +N/2, and ithas the advantage of limiting the average and peak power inthe transmitter output. The modulo-N adder can be imple-mented by using digital adder circuits.

The weighting coefficients of THP (−h1, −h2, −h3, · · ·,−hn) are determined by the transfer function H(z) of a trans-mission line. Assuming that the transmission line is charac-terized by the transfer function

H(z) = 1 + h1z−1 + h2z−2 + h3z−3 + · · · + hnz−n (1)

using the z-transform, the coefficients are −h1, −h2, −h3,· · ·, −hn. THP coefficients h1, h2, h3, · · ·, hn are sampledvalues of impulse response at the transmission data rate. Thenumber of taps for THP depends on characteristics of H(z),especially the post-cursor length. Note that the number oftaps directly corresponds to circuit costs as shown in Fig. 12.Therefore, the number of taps should be small according tothe channel property so as to reduce circuit costs and thepower dissipation of transceiver circuitry.

Figure 13 shows the proposed data transmission sys-tem using THP. The data symbols ai are modulated at thetransmitter. The output data of THP bi is

Fig. 12 Block diagram of Tomlinson-Harashima precoding.

bi =

⎛⎜⎜⎜⎜⎜⎜⎝ai −n∑

j=1

h jai− j

⎞⎟⎟⎟⎟⎟⎟⎠ modulo N, (2)

and therefore the magnitude of bi is limited between −N/2and +N/2. At the receiver, the data after transmission ismodulo-N reduced, and THP can cancel the ISI completely,resulting in achieving ISI-free communication. However, asshown in Fig. 13, to convert the output data bi to analog sig-nals, Digital to Analog Converter (DAC) is necessary at atransmitter. To demodulate the signal at receiver, Analogto Digital Converter (ADC) is required. In high speed datatransmission using THP, high-speed DAC and ADC are im-portant factor. This fact is an issue for THP implementationin VLSI.

4.2 Binary Data Communication Using THP

To confirm the principle, THP is applied to binary data com-munication on MSLs. Figure 14 shows transmitter signalingusing THP with various conditions. Figure 14 (a) is THPoutput signaling at 5 Gbps on a MSL 1 m, and Figs. 14 (b)and 14 (c) are THP output signaling at 2 Gbps and 5 Gbps ona MSL 2 m. Those THP taps are 7, 9 and 11, respectively.At 5 Gbps as shown in Figs. 14 (a) and 14 (c), the ampli-tude is limited between −1 to 1 by modulo arithmetic. At2 Gbps data transmission (Fig. 14 (b)), however, the outputwaveform is similar to the pre-emphasis one, because THPcoefficients are stable in this condition.

Figure 15 shows simulation results of eye diagrams of2-PAM with THP. Figures 15 (a) and 15 (b) are 2 Gbps datarate on MSLs 1 m and 2 m, respectively. Also, Fig. 15 (c)shows 5 Gbps data rate on a MSL 2 m. After modulo-Nreduction using an ADC, THP can remove ISI, and the eyesare clearly opened as shown in Fig. 15.

Fig. 13 THP-based data transmission system.


(a) 5 Gbps data rate, 1 m length (THP taps:7)

(b) 2 Gbps data rate, 2 m length (THP taps:9)

(c) 5 Gbps data rate, 2 m length (THP taps:11)

Fig. 14 Transmitter signals of 2-PAM with THP.

4.3 Multiple-Valued Data Communication Using THP

Figure 16 shows simulation results of eye diagrams of 4-PAM using THP with the data rate 2 Gsps. Figures 16 (a)and 16 (b) show results of MSLs with 1 m and 2 m, respec-tively. Here, 4-PAM with 2 Gsps corresponds to 4 Gbpsbinary data transmission. This means that operating fre-quency of 4-PAM THP circuitry can be halved compared tobinary one, which contributes the low-power operation. Asshown in these figures, THP can provide clear eye diagramin multiple-valued data communication. At a receiver side,we can detect 4-valued data symbols correctly. Note that theADC/DAC-based THP transceiver circuits for binary and 4-PAM are the same except for the required number of taps.Since 4-valued signaling enables us to reduce the data rate,ISI effects can also be mitigated. Therefore, it is possible toreduce the number of taps for 4-PAM THP than binary one,resulting in decreasing hardware costs.

However, this simulation does not consider AWGN intransmission lines. To evaluate more realistic transmissionon MSLs, it is necessary to consider AWGN effects that aredetermined by the channel environment.

(a) 5 Gbps data rate, 1 m length (THP taps:7)

(b) 2 Gbps data rate, 2 m length (THP taps:9)

(c) 5 Gbps data rate, 2 m length (THP taps:11)

Fig. 15 Simulation results of eye diagram with THP (2-PAM).

(a) 2 Gsps (4 Gbps) data rate, 1 m length (THP taps:4)

(b) 2 Gsps (4 Gbps) data rate, 2 m length (THP taps:9)

Fig. 16 Simulation results of eye diagram with THP (4-PAM).


5. Discussion of Implementation Costs of THP

The achievable data rate of serial links using THP is mainlylimited by the operating frequency of transceiver circuitry,especially ADCs and DACs. For instance, to achieve 2 Gbpsdata rate in 2-PAM, high-performance circuits that can oper-ate in 2 GHz are required. In contrast, multiple-valued sig-naling, which can reduce data rates as well as the operatingfrequency of circuits, is very effective to achieve high-speedserial links in VLSI system.

Figure 17 shows the eye diagram of 4-PAM 2.5 Gsps (5Gbps) with THP. Comparing the same data rate of 5 Gbpsusing binary signaling (Fig. 15 (a)), similar eye diagram isobtained. These waveforms are fed to the same ADCs toperform modulo-N reduction. Therefore, the use of 4-PAMTHP offers advantages over binary THP, namely the reduc-tion of operating frequency by half and the reduction of thenumber of taps for THP. For instance, in these simulations,binary THP needs to operate 5 GHz using 7 taps. On theother hand, 4-PAM THP operates 2.5 GHz using 5 taps. As aresult, reduction of both operating frequency and number oftaps (Table 1) using 4-PAM greatly contributes to decreas-ing the power consumption of THP. Moreover, since THPconsists of digital rich ADC/DAC-based architectures, theperformance of THP can be improved by the CMOS scal-ing.

To reduce the hardware costs, bit resolution for theTHP operation is important. As shown in Fig. 18, bit res-olution of THP coefficients is fixed at L = 8-bit. Fig-ure 19 shows the eye diagrams of M = 4-bit, M = 6-bitand M = 8-bit. As shown in Fig. 19 (a), THP with 4-bitresolution cannot open the eye at the receiver completely.Figures 19 (b) and 19 (c) show that 6- to 8-bit resolution isnecessary to remove ISI sufficiently, and at least a 6-bit D/A

Fig. 17 Eye diagram of 5 Gbps (2.5 Gsps) 4-PAM data communicationon MSL 1 m (THP taps:5).

Table 1 Evaluation of hardware costs.

PAM Operation THP tapsLevel Frequency (Number of Multipliers and Adders)

2-PAM 5GHz 7-taps(7-Multipliers, 6-Adders)

4-PAM 2.5GHz 5-taps(5-Multipliers, 4-Adders)

converter is required for THP implementation in this chan-nel environment.

6. Conclusion

This paper evaluated high-speed data transmission systemsusing Tomlinson-Harashima Precoding. First, transmissioncharacteristics of a MSL were measured and simulated, andeye diagrams of 2-PAM and 4-PAM were evaluated usingnumerical simulation. Next, the feasibility of the data trans-mission on a MSL with THP was demonstrated. To evaluatehardware costs, the required bit resolution of THP imple-mentation was simulated.

From simulation results, THP can remove ISI effects,and thus high-speed data transmission on a MSL can beachieved. By using multiple-valued signaling with THP, op-erating frequency and implementation cost can be reduced.

Fig. 18 Bit resolution of THP operation.

(a) Simulation result of 4-bit resolution

(b) Simulation result of 6-bit resolution

(c) Simulation result of 8-bit resolution

Fig. 19 Simulation results of eye diagram (2 Gsps, 2 m length) withvarious bit resolution (THP taps:9).


As a result, 4-PAM THP has a possibility to accomplishhigh-speed serial links for VLSI systems, such as back-planes. Furthermore, compared to conventional analog pre-emphasis, THP can change and the parameters easily usingdigital calibration. Future simulations are needed to evalu-ate the various transmission lines.

References

[1] Y. Yuminaka and S. Sakamoto, “An efficient data transmission tech-nique for VLSI systems using multiple-valued code-division multi-ple access,” IEICE Trans. Electron., vol.E85-C, no.8, pp.1581–1587,Aug. 2002.

[2] H.A. Wheeler, “Formulas for the skin effect,” Proc. IRE, vol.30,pp.412–424, 1942.

[3] J.R. Barry, E.A. Lee, and D.G. Messerschmitt, Digital communica-tion, Springer, 2003.

[4] M. Tomlinson, “New automatic equaliser employing modulo arith-metic,” Electron. Lett., vol.7, pp.138–139, 1971.

[5] H. Harashima and H. Miyakawa, “Matched-transmission techniquefor channels with intersymbol interference,” IEEE Trans. Commun.,vol.COM-20, Issue 4, pp.774–780, 1972.

[6] Y. Wang, J. Muller, and J. Speidel, “3 Gbit/s transmission over plas-tic optical fiber with adaptive Tomlinson-Harashima Precoded sys-tems,” 2013 IEEE International Conference on Consumer Electron-ics (ICCE), 6290632, Jan. 2013.

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Yosuke Iijima received the B.E. and M.E.degrees in electronic engineering from GunmaUniversity in 2003 and 2005, respectively. In2008, he received the D.E. degree in electronicengineering from University of Tsukuba. Heis currently an assistant professor in the Divi-sion of Innovative Electrical and Electronic En-gineering at Oyama National College of Tech-nology, Japan. His research interests include de-sign of high-speed interfaces, digital signal pro-cessing, sensor communication systems and its

applications.

Yuuki Takada received the B.E. degreein electronic engineering from Gunma Univer-sity, in 2012. He is currently working toward theM.E. degree in electrical engineering at GunmaUniversity. His main areas of interests includehigh-speed interfaces for VLSI systems.

Yasushi Yuminaka received the B.E., M.E.,and D.E. degrees in electronic engineering fromTohoku University in 1990, 1992, and 1995, re-spectively. He is currently an associate pro-fessor in the Division of Electronics and In-formatics, Faculty of Science and Technology,Gunma University. Dr. Yuminaka received theIEE Ambrose Fleming Premium Award in 1994,the Niwa Memorial Award in 1995, the YoungEngineer Award from the IEICE of Japan in1995, the Excellent Poster Award from Sys-

tem LSI Biwako Workshop in 1999, the Young Excellent Author Awardfrom Karuizawa Workshop in 2000 and the Outstanding Contributed PaperAward at the IEEE International Symposium on Multiple-Valued Logic in2000 and 2009. His research interests include design of multiple-valuedintegrated circuits, high-speed interfaces for VLSI systems, new-paradigmof computing systems and their applications. He is a member of IEEE andIEEJ.

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