high-speed quad-mosfet driverww1.microchip.com/downloads/en/devicedoc/md1811...md1811...

2020 Microchip Technology Inc. DS20005744A-page 1

MD1811

Features• 6 ns Rise and Fall Time• 2A Peak Output Source and Sink Currents• 1.8V to 5V Input CMOS Compatible• 5V to 12V Total Supply Voltage• Smart Logic Threshold• Low-Jitter Design• Four Matched Channels• Drives Two P-Channel and Two N-Channel

MOSFETs• Outputs can Swing Below Ground• Low-Inductance Package• High-Performance, Thermally Enhanced Package

Applications• Medical Ultrasound Imaging• Piezoelectric Transducer Drivers• Non-Destructive Testing• PIN Diode Driver• CCD Clock Driver/Buffer• High-Speed Level Translator

General DescriptionThe MD1811 is a high-speed quad-MOSFET driverdesigned to drive high-voltage P-channel andN-channel MOSFETs for medical ultrasoundapplications and other applications requiring ahigh-output current for a capacitive load. Thehigh-speed input stage of the MD1811 can operatefrom a 1.8V to 5V logic interface with an optimumoperating input signal range of 1.8V to 3.3V. Anadaptive threshold circuit is used to set the leveltranslator switch threshold to the average of the inputlogic 0 and logic 1 levels. The input logic levels may beground referenced even though the driver is putting outbipolar signals. The level translator uses a proprietarycircuit, which provides DC coupling together withhigh-speed operation.The output stage of the MD1811 has separate powerconnections, enabling the output signal L and H levelsto be chosen independently from the supply voltagesused for the majority of the circuit. As an example, theinput logic levels may be between 0V and 1.8V, thecontrol logic may be powered by +5V and –5V, and theoutput L and H levels may be varied anywhere over therange of –5V to +5V. The output stage is capable ofpeak currents of up to ±2A, depending on the supplyvoltages used and load capacitance present. The OEpin serves a dual purpose. First, its logic H level is usedto compute the threshold voltage level for the channelinput level translators. Second, when OE is low, theoutputs are disabled, with the A and C outputs high andthe B and D outputs low. This assists in properlypre-charging the AC coupling capacitors that may beused in series in the gate drive circuit of an externalPMOS and NMOS transistor pair.

Package Type16-lead QFN

(Top view)

See Table 2-1 for pin information.

1

High-Speed Quad-MOSFET Driver

MD1811

DS20005744A-page 2 2020 Microchip Technology Inc.

Functional Block Diagram

Typical Application Circuit

0.22µF

3.3V CMOSLogic Inputs

OUTA

OUTB

OUTC

OUTD

VDD VH

+10V

VSS VLGND

INA

INB

INC

IND

OEENAB

10nF

To PiezoelectricTransducer #1

-100V

#1

#2

MD1811

0.47µF

1.0µF

1.0µF

1.0µF

1.0µF

+PLS1

-PLS1

+PLS2

-PLS2

10nF

10nF

10nF

+100V

-100V

+100V

TC6320

TC6320

To PiezoelectricTransducer #2

+10V


MD18111.0 ELECTRICAL CHARACTERISTICSAbsolute Maximum Ratings†Logic Supply Voltage, VDD–VSS ........................................................................................................... –0.5V to +13.5VOutput High Supply Voltage, VH .................................................................................................. VL–0.5V to VDD + 0.5VOutput Low Supply Voltage, VL.................................................................................................... VSS–0.5V to VH+ 0.5VLow-Side Supply Voltage, VSS.................................................................................................................. –7V to + 0.5VLogic Input Levels ........................................................................................................................VSS–0.5V to GND +7VMaximum Junction Temperature, TJ

....................................................................................................................+125°COperating Ambient Temperature, TA ..................................................................................................... –20°C to +85°CStorage Temperature, TS ......................................................................................................................–65°C to +150°CPower Dissipation ................................................................................................................................................. 2.2WESD Rating (Note 1) ............................................................................................................................... ESD Sensitive

Note 1: Device is ESD sensitive. Handling precautions are recommended.

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to thedevice. This is a stress rating only, and functional operation of the device at those or any other conditions above thoseindicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions forextended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICSElectrical Specifications: VH = VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, and TA = 25°C

Parameter Sym. Min. Typ. Max. Unit ConditionsLogic Supply Voltage VDD–VSS 4.5 — 13 V 2.5V ≤ VDD ≤ 13VLow-Side Supply Voltage VSS –5.5 — 0 VOutput High Supply Voltage VH VSS +2 — VDD VOutput Low Supply Voltage VL VSS — VDD –2 VVDD Quiescent Current IDDQ — 0.8 — mA

No input transitions, OE = 1VH Quiescent Current IHQ — — 10 µAVDD Average Current IDD — 8 — mA One channel on at 5 MHz,

no loadVH Average Current IH — 26 — mAInput Logic Voltage High VIH VOE–0.3 — 5 V

For logic inputs INA, INB, INC, and IND

Input logic Voltage Low VIL 0 — 0.3 VInput Logic Current High IIH — — 1 µAInput Logic Current Low IIL — — 1 µAOE Input Logic Voltage High VIH 1.7 — 5 V

For logic input OEOE Input Logic Voltage Low VIL 0 — 0.3 VOE Input Resistance RIN 10 20 30 kΩLogic Input Capacitance CIN — 5 10 pFOutput Sink Resistance RSINK — — 12.5 Ω ISINK = 50 mAOutput Source Resistance RSOURCE — — 12.5 Ω ISOURCE = 50 mAPeak Output Sink Current ISINK — 2 — APeak Output Source Current ISOURCE — 2 — A

MD1811


TEMPERATURE SPECIFICATIONS

Note 1: 1 oz. 4-layer 3” x 4” PCB

AC ELECTRICAL CHARACTERISTICSElectrical Specifications: VH = VDD = 12V, VL = VSS = GND =0V, VOE = 3.3V and TA = 25°C

Parameter Sym. Min. Typ. Max. Unit Conditions Input or OE Rise and Fall Time tirf — — 10 ns Logic input edge speed

requirementPropagation Delay when Output is from Low to High tPLH — 7 — ns

CLOAD = 1000 pF, input signal rise/fall time of 2 ns (See Tim-ing Diagram)

Propagation Delay when Output is from High to Low tPHL — 7 — ns

Output Rise Time tr — 6 — nsOutput Fall Time tf — 6 — nsRise and Fall Time Matching l tr–tf l — 1 — ns

For each channelPropagation Low-to-High and High-to-Low Matching l tPLH–tPHL l — 1 — ns

Propagation Delay Matching Δtdm — ±2 — ns Device-to-device delay matchOutput Enable Time tOE — 9 — ns

Parameter Sym. Min. Typ. Max. Unit ConditionsTEMPERATURE RANGEMaximum Junction Temperature TJ — — 125 °COperating Ambient Temperature TA –20 — 85 °CStorage Temperature TS –65 — 150 °CPACKAGE THERMAL RESISTANCE16-lead QFN JA — 45 — °C/W Note 1


MD1811Timing Diagram

TABLE 1-1: TRUTH FUNCTION TABLELogic Inputs Outputs

OE INA INB OUTA OUTBH L L VH VHH L H VH VLH H L VL VHH H H VL VLL X X VH VL

OE INC IND OUTC OUTDH L L VH VHH L H VH VLH H L VL VHH H H VL VLL X X VH VL

3.3V

INPUT

0V tPLH

10%

90%

50% 50%

tPHL

tr

90%

10% tf

12V

OUTPUT

0V

MD1811


2.0 PIN DESCRIPTIONTable 2-1 shows details on the pins of MD1811. SeePackage Type for the location of the pins.

TABLE 2-1: PIN FUNCTION TABLE

Pin Number Pin Name Description

1 INB Logic input. Input logic low will cause the output to swing to VH. Input logic high will cause the output to swing to VL. Keep all logic inputs low until IC powers up.

2 VL Supply voltage for N-channel output stage

3 GND Logic input ground reference

4 VL Supply voltage for N-channel output stage

5 INC Logic input. Input logic low will cause the output to swing to VH. Input logic high will cause the output to swing to VL. Keep all logic inputs low until IC powers up.6 IND

7 VSS Low-side supply voltage. VSS is also connected to the IC substrate. It is required to be connected to the most negative potential of voltage supplies and is powered up first.

8 OUTDOutput driver. Swings from VH to VL. Intended to drive the gate of an external N-channel MOSFET through a series capacitor. When OE is low, the output is disabled. OUTD will swing to VL, turning off the external N-channel MOSFET.

9 OUTCOutput driver. Swings from VH to VL. Intended to drive the gate of an external P-channel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTC will swing to VH, turning off the external P-channel MOSFET.

10 and 11 VH Supply voltage for P-channel output stage

12 OUTBOutput driver. Swings from VH to VL. Intended to drive the gate of an external N-chan-nel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTB will swing to VL, turning off the external N-channel MOSFET.

13 OUTAOutput driver. Swings from VH to VL. Intended to drive the gate of an external P-chan-nel MOSFET through a series capacitor. When OE is low, the output is disabled. OUTA will swing to VH, turning off the external P-channel MOSFET.

14 VDD High-side supply voltage

15 INA Logic input. Input logic low will cause the output to swing to VH. Input logic high will cause the output to swing to VL. Keep all logic inputs low until the IC powers up.

16 OE

Output Enable logic input. When OE is high, (VOE+VGND)/2 sets the logic threshold level for inputs. When OE is low, OUTA and OUTC are at VH, while OUTB and OUTD are at VL regardless of the inputs INA, INB, INC, or IND. Keep OE low until IC powers up.

Substrate The IC substrate is internally connected to the thermal pad. Thermal Pad and VSS must be connected externally.


MD18113.0 APPLICATION INFORMATIONFor proper operation of the MD1811, low-inductancebypass capacitors should be used on the varioussupply pins. The GND input pin should be connected tothe logic ground. The INA, INB, INC, IND, and OE pinsshould be connected to a logic source with a swing ofGND to OE, where OE is 1.8V to 5V. Good tracepractices should be followed corresponding to thedesired operating speed. The internal circuitry of theMD1811 is capable of operating up to 100 MHz, withthe primary speed limitation being the loading effect ofthe load capacitance. Because of this speed and thehigh transient currents due to the capacitive loads, thebypass capacitors should be as close to the chip pinsas possible. Unless the load specifically requiresbipolar drive, the VSS and VL pins should havelow-inductance feed-through connections directly to aground plane. The power connection VDD should havea ceramic bypass capacitor to the ground plane withshort leads and decoupling components to preventresonance in the power leads.The voltages of VH and VL decide the output logiclevels. These two pins can draw fast transient currentsof up to 2A, so they should be provided with a suitablebypass capacitor located next to the chip pins. Aceramic capacitor of up to 1 µF may be appropriate,with a series ferrite bead to prevent resonance in thepower supply lead going to the capacitor. Pay particular attention to minimizing trace lengths,current loop area, and using sufficient trace width toreduce inductance. Surface-mount components arehighly recommended. Since the output impedance ofthis driver is very low, in some cases, it may bedesirable to add a small series resistor in series withthe output signal to obtain better waveform transitionsat the load terminals. This will reduce the outputvoltage slew rate at the terminals of a capacitive load.Ensure that parasitic couplings are minimized from thedriver output to the input signal terminals. The parasiticfeedback may cause oscillations or spurious waveformshapes on the edges of signal transitions. Since theinput operates with signals down to 1.8V, even smallcoupled voltages may cause problems. The use of asolid ground plane as well as good power and signallayout practices will prevent this problem. Make surethat the circulating ground return current from acapacitive load will not react with common inductanceand cause noise voltages in the input logic circuitry.

MD1811


4.0 PACKAGING INFORMATION

4.1 Package Marking Information

Legend: XX...X Product Code or Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of available charactersfor product code or customer-specific information. Package may or not includethe corporate logo.

3e

3e

16-lead QFN Example

XXXXXXXX YYWWNNNe3

MD1811K6 2025521e3


MD1811

Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.

MD1811


NOTES:


MD1811APPENDIX A: REVISION HISTORY

Revision A (September 2020)• Converted Supertex Doc# DSFP-MD1811 to

Microchip DS20005744A• Changed the package marking format• Updated the quantity of the 16-lead QFN K6 pack-

age from 3000/Reel to 3300/Reel to align it with the actual BQM

• Made minor text changes throughout the docu-ment

MD1811


PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

Example:

a) MD1811K6-G: High-Speed Quad-MOSFET Driver, 16-lead QFN, 3300/Reel

PART NO.

Device

Device: MD1811 = High-Speed Quad-MOSFET Driver

Package: K6 = 16-lead QFN

Environmental: G = Lead (Pb)-free/RoHS-compliant Package

Media Type: (blank) = 3300/Reel for a K6 Package

XX

Package

- X - X

Environmental Media Type Options


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© 2020, Microchip Technology Incorporated, All Rights Reserved.

ISBN: 978-1-5224-6856-1

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high-speed quad-mosfet driverww1.microchip.com/downloads/en/devicedoc/md1811...md1811...

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