Teradyne High Speed Subsystem Overview

The Teradyne High Speed Subsystem (HSSub) addresses ATE requirements that are common to most recent designs including increasing speeds, protocol complexity, data quantities, processing demands, along with lower latency interaction with the UUT. As the level of integration within UUTs increases, there are more concurrent I/O ports of various types. Digital buses of various speeds and complexity are coupled with equally demanding analog and RF ports. The HSSub avoids dedicated, single-purpose hardware. Powerful and flexible hardware and software combine to provide reconfigurable, multi-purpose capabilities. Within seconds, the HSSub Runtime Defined Instruments are configured to address the unique requirements of a specific UUT. The HSSub is designed for integration into existing or future factory or depot test systems with the ease of a single LXI instrument. Alternately, the HSSub may be used in a stand-alone role either as a bench-top tester or the nucleus for a newly designed test system.

The HSSub is designed as a commercial solution for Defense and Aerospace test that provides a more economical approach than the applications-specific approaches of the past. Most ATE is inadequate for today’s wide range of I/O port requirements, forcing test departments to use multiple single-purpose instruments or fully custom ITA-based circuitry. Over time, these techniques tend to be very expensive due

Runtime Defined Bus Solution for Defense and Aerospace ATE

FEATURES

Addresses Defense and Aerospace test of assemblies with I/O port requirements that include:

● Serial or parallel, standardized or custom, protocol-based buses of any speed

● Runtime Defined Instruments are configured in seconds by the TPS for specific UUT requirements

● Open Three Tier Architecture combines programmable hardware, real-time processing, and PC technology to simplify protocol and TPS development across a broad range of requirements

● Scalable architecture addresses the demand to consolidate digital, analog, and RF UUT requirements into a single facility with common support infrastructure

BENEFITS

Teradyne hardware, firmware, software, and proven support infrastructure minimize the cost of both deployment and long-term sustainment:

● Lowest long-term logistics cost

● Lowest development costs

● Highest production throughput

High Speed Subsystem

to early obsolescence, lack of flexibility, low throughput, lack of documentation and applications support, and the overall high cost of long-term logistics support.

The HSSub provides a superior solution with a unique Three-Tier Architecture consisting of:

● Tier 1: Instrument-based low-level programmable hardware such as FPGAs and bus-specific devices provide the greatest possible performance

● Tier 2: Instrument-based upper-level real-time processors and FPGAs provide critical control and data manipulation

● Tier 3: Setup, top-level coordination, and system integration of the HSSub PC provides for multiple, concurrently executing instruments implementing the lower two tiers

The HSSub TriFlex™ software tightly integrates the three tiers to provide unprecedented power and flexibility. The ease of use of upper tiers is complemented by the speed of the lower tiers. Other commercial and in-house approaches are typically over-dependent on the use of FPGAs, which provide high performance, but are generally more difficult to program than processors. The HSSub properly employs tier 1 hardware for low-level operations, while moving upper-level protocol operations to the more flexible and easily programmed upper tiers. The open HSSub Three-Tier Architecture streamlines protocol and TPS development by Teradyne and end users.

HSSub Foundation

The subsystem is housed in a self-sufficient HSSub Foundation, a

HSSub Three-Tier Archictecture

combination of hardware and software that coordinates the HSSub instrumentation and the interactions with the UUT. The Foundation includes a chassis and related mechanics, local PC computing (tier 3), and the HSSub TriFlex software that controls the instrumentation. A family of Foundations provides solutions for system integration, laboratory use, and ATE Ancillary utilization. Optionally, a Virginia Panel G20 receiver system is used to provide a robust production interface. HSSub integrates into a large-scale test system as an LXI instrument, interfaced by Ethernet, and controlled by high-level commands from the TPS running on the controlling test station computer.

The HSSub Foundation is comprised of a PXI Express 3U Chassis with a bandwidth approaching 2 GB/s between the PC and the internals of all HSSub instruments. The Foundation includes the HSSub PC running the Windows 7 64-bit operating system, providing the LXI communication up to the test station host computer and integration down to the HSSub Instruments. Teradyne can provide complete hardware and software integration of third-party instrumentation into the HSSub, avoiding the complexities of compatibility testing, optimization, and debugging.

The Foundation is populated with a variety of HSSub instruments that provide tier 1 (low-level) and optional tier 2 (upper-level) support. IO Expansion Instruments (IOXI) support tier 1 with combinations of FPGAs, programmable protocol devices, and low-level signal interfaces that address a broad range of UUT port types. RT Processor Modules satisfy most tier 2 requirements with a fast real-time processor and operating system. Core Instruments combine an FPGA for tier 1 with a real-time processor for tier 2.

HSSub Core Instruments

Each Core Instruments is configured at runtime to manage the requirements of a specific bus type and upper-level protocol. There are two of these instruments, the LVDS Core Instrument and the Serial Core Instrument, which are identical except for I/O connections. The required number of concurrent bus types generally determines the quantity of Core Instruments. Each Core Instrument contains a multi-core real-time processor and large, rapidly configured FPGA resources. The real-time processor

High Speed Subsystem

operations to rapidly move data within all HSSub memory.

Many physical bus requirements can be met using direct I/O from the Test FPGA in a Core Instrument. Some buses require special physical interface or low-level protocol capabilities not possible with a Core Instrument FPGA. In these cases Core Instruments may be associated with one or more IO Expansion Instruments by the HSSub software. All of the processor and FPGA capabilities of the Core Instrument are available to the TPS developer for upper-level (tier 2) support of the low-level (tier 1) functions of the IO Expansion Instruments.

HSSub LVDS Core Instrument

The LVDS Core Instrument can provide direct I/O for parallel buses. A very large proportion of the high-speed test requirements today are based on parallel LVDS buses that emerged prior to the standardization of Multi-Gigabit serial buses. These parallel buses often use custom design, or employ commercial approaches that are no longer well supported. The flexibility of the LVDS Core Instrument is key to addressing the required customization. This instrument provides up to 64 differential data pairs and 8 differential control/clock signals. The differential signals can be reconfigured for very low-voltage single-ended operation if required.

HSSub Serial Core Instrument

The Serial Core Instrument is identical in architecture to the LVDS Core Instrument except for the physical I/O brought out to the front panel connectors, which

manages internal Core Instrument operation and provides dedicated and predictable high-level processing capabilities. The Wind River VxWorks operating system provides mission-critical reliability and mature software development and debug tool support. UUT-specific real-time functionality is achieved using C/C++ programming in conjunction with the Teradyne HSSub TriFlex software interfaces.

The Core Instrument has a Virtex-6 FPGA for port-specific test requirements (Test Defined FPGA). In addition to I/O, the Test Defined FPGA is always available to perform very high-performance bus protocol processing and math operations. All HSSub FPGAs may be configured in seconds under control of the TPS. Many standardized bus tests run using FPGA firmware supplied by Teradyne. TPS developers may already have their own FPGA code for custom applications, or have the resources to develop it. HSSub VHDL/Verilog infrastructure libraries simplify the integration of user code to the HSSub hardware and TriFlex software infrastructure. The HSSub Debug Card can be mounted on the front of the instrument during TPS development to allow access to the full range of debug tools associated with the Wind River and Xilinx development tools.

The FPGAs and Real-time Processor have large high-speed memories to allow very fast, low-latency data access. The HSSub hardware includes very high-speed buses within instruments, between instruments, and to the HSSub PC. The TriFlex software makes it easy to use DMA

Core Instruments and IO Expansion Instruments team up for UUT I/O support

Physical I/OPhysical I/O Physical I/O

UUT

LVDSCore Instrument

IO ExpansionInstrument

AnyCore Instrument

SerialCore Instrument

Control & Processing

consists of 16 Multi-Gigabit Transceivers (MGT). Many serial buses such as Fibre Channel, PCI Express, Serial RapidIO, Aurora, and RocketIO can be serviced directly from the Test FPGA. The Buses that are supported directly by the Serial Core Instrument tend to be much more standardized than those that use the LVDS Core Instrument.

RT Processor Module

The RT (real-time) Processor Module is an economical means for providing tier 2 real-time support that is identical and compatible with that of the Core Instruments. Typically, these modules are associated in software with IO Expansion Instruments (tier 1).

HSSub IO Expansion Instruments

Many I/O ports require capabilities that go beyond those of the Test Defined FPGA on the Core Instruments. Special buffering may be needed for unique signaling requirements. This is the case for Low Voltage TTL (LVTTL), Multi-Point LVDS (M-LVDS), as well as optical and transformer-coupled buses. In addition, some buses such as Ethernet, HotLink, StarFabric, and FireWire have protocol requirements that are most efficiently handled in specialized silicon.

These special tier 1 bus requirements are satisfied by HSSub IO Expansion Instruments. An associated Core Instrument or RT Processor Module provides the tier 2 upper-level protocol processing capability and overall I/O port control. The TPS software establishes the association between real-time processors and one or more IO Expansion Instruments. This relationship is dynamic; it may be reassigned between TPSs, or even during the execution of a single TPS.

Many of these instruments use the new Flexible IO Expansion Instrument architecture, a family of 2-slot instruments employing a common Xilinx Virtex 7 FPGA capability with one or two Physical Interface Modules that implement the unique port-related functionality. The key advantage of this approach is that Teradyne can quickly implement Physical Interface Modules for emerging user requirements, and the core functionality provides incredible power for protocol development.

HSSub Remote Test Head

Many UUT buses require close proximity to the instrumentation to avoid the

For example, Teradyne includes Fibre Channel with the HSSub software that any TPS developer can use. On the other hand, an end user with proprietary test requirements can develop custom HSSub Apps. All Apps are developed using the best in class tools; Xilinx Vivado and ISE FPGA Design Suites (tier 1), Wind River Workbench for C/C++ real-time development (tier 2), Visual Studio, LabWindows/CVI, or LabVIEW on the PC (tier 3).

HSSub TPS Programming

HSSub TPS programming on the PC is performed in much the same way as with conventional instruments. A TPS invokes an HSSub App by making calls to an HSSub TriFlex API. Once an App is loaded, the TPS communicates with the App through an IVI-compliant interface. Generally, functions on the HSSub PC are called from the main TPS running on the main Test Station computer. The two computers communicate via an IVI-compliant LXI driver on the main computer, and the TriFlex APIs on the HSSub computer.

HSSub Benefits and Advantages

An increasing number of assemblies with demanding I/O port requirements are continuously introduced into factories, deployed to the field, and will require service at depots. Lacking corresponding ATE capabilities, test engineers have struggled to address these needs. Increasingly complex active ITAs with FPGAs, processors, and memory are becoming commonplace. Systems are being augmented with single-purpose instruments to address individual I/O port requirements. More and more of the test capabilities are external to the core

loading or time delay associated with long signal cabling. In some cases the UUT can be close to the HSSub Foundation in the test system. In other cases the physical nature of the UUT or test adaptor may make it impossible to place it close enough to the HSSub. In order to minimize the distance, up to four HSSub IO Expansion Instruments may be remotely located in a small Remote Test Head near the UUT, minimizing the length of the signal path. A remote instrument is controlled by a Core Instrument, RT Processor Module, or the HSSub PC over a high-speed optical bus, operating as if it were located in the Foundation chassis.

HSSub Apps

The TPS software employs one or more HSSub Applications, or Apps that configure the HSSub instrumentation. An App consists of the code and data for each of the three tiers. For instance, a Video Over Fibre Channel App may use the Serial Core Instrument and contain the following:

1. FPGA code that provides standard low-level Fibre Channel support

2. A real-time processor program for performing the upper-level video framing functions

3. A programming interface (API) on the PC which looks just like a driver for a dedicated instrument, manipulated by the TPS code

Programming of all three tiers is completely open, and is accessed by APIs of the HSSub TriFlex software. An App can use one or many instruments. A TPS can simultaneously load multiple Apps. Teradyne, the end user, or third-party developers can provide apps.

High Speed Subsystem

Bus Technology Tier 1 Instrument Typical Application

LVTTL LVTTL IOXI Standard, Custom, Boundary Scan

LVDS LVDS Core Custom Buses

M-LVDS LVTTL IOXI Custom Buses

Fibre Channel Serial Core Standard Wired & Optical Protocols

Serial RapidIO Serial Core Standard Serial

Aurora Serial Core Proprietary Serial Standard

FireWire FireWire IOXI Standard AS5643 MIL FireWire

Ethernet Ethernet IOXI Up to 1G Standard Wired & Optical

RS-485 RS-485 IOXI Standard and Custom Buses

RS-232 RS-232 IOXI Up to 36 Concurrent Standard Channels

HOTLink II HOTLink IOXI Proprietary Serial Standard

Typical HSSub bus implementations

Semi Test

Defense & Aerospace

Production Board

Wireless Test

Production

Customer Care

Software

Engineering

Storage Test

Training

Parts Services

eKnowledge

Teradyne, Inc. 600 Riverpark Drive, North Reading, MA 01864

+1.978.370.2700 | www.teradyne.com

Various Foundations available for standalone, rack-mount, and ATE Ancillary usage

Chassis 3U PXI Express chassis with 3–16 available instrument slots, PCIe Generation 2 technology

Computer hardware 2 GHz processor, 8-16 GB local memory, internal to PXI chassis or external 1U rack mountable

Computer operating system Windows 7 64-Bit Edition

Test executives and Teradyne TestStudio, or user-supplied TestStand, development environments Visual Studio, LabWindows, LabVIEW

Timing Controller Central timing controller distributes precision clocks, trigger in, trigger out to all instrument slots (16-slot Foundations only)

Operating Range 0 – 45 degrees C

HSSub-5010 High Speed Subsystem Core LVDS Instrument (Teradyne Part Number 611-039-00)

PXI Express Slots 2

Real-time Processor Freescale 4-Core Processor with Wind River VxWorks RTOS

Total Memory 3 GB DDR3 SDRAM

Test Defined FPGA Family Xilinx Virtex-6

LVDS I/O Pairs Single-Ended I/O

# I/O Signals 72 differential pairs (64 data) 132 single-ended (128 data)

Levels 3.5 mA typical 1.2V, 1.5V, 1.8V. 2.5V

Data Port Configurations 4x16, 2x32, 1x64 4x32, 2x64, 1x28

Maximum Clock Rate 400 MHz 100 MHz

Maximum bit rate per 800 Mbps (DDR) 200 Mbps (DDR) data lane

HSSub-5050 Serial Core Instrument (Teradyne Part Number 613-892-00)

PXI Express Slots 2

Real-time Processor Freescale 4-Core Processor with Wind River VxWorks RTOS

Total Memory 3 GB DDR3 SDRAM

Test Defined FPGA Family Xilinx Virtex-6

Serial Channels 16 Xilinix Multi-Gigabit Tranceivers

Maximum Speed 3.125 Gbps

HSSub-5020 RT Processor Module (Teradyne Part Number 609-494-80)

PXI Express Slots 1

Real-time Processor Freescale 4-Core Processor with Wind River VxWorks RTOS

Total Memory 2 GB DDR3 SDRAM

HSSub-6020 LVTTL IO Expansion Instrument (Teradyne Part Number 612-122-00)

PXI Express Slots 1

# I/O Signals 84 LVTTL bidirectional data bits and 4 clocks, 8 LVTTL GPIO or 44 LVDS pairs (up to 100 MHz)

Test Defined FPGA Xilinx Virtex 5 with 512 MB DDR2 SDRAM

Voltage Levels 3.3V, 2.5V, 1.8V, 1.5V, 1.2V

HSSub-6040 Hybrid IO Expansion Instrument (Teradyne Part Number 614-383-80)

PXI Express Slots 1

Test Defined FPGA Xilinx Virtex 6 with 1 GB DDR3 SDRAM

Serial Channels 8 Multi-Gigabit Tranceivers (up to 5 Gbps)

Parallel Signals 18 LVDS pairs (up to 400 Gbps)

HSSub-6065 4-Port Optical IO Expansion Instrument (Teradyne Part Number 618-142-80)

Chassis Slots 1

Application Connects up to 4 ports of a Serial Core Instrument or Ethernet IO Expansion Instrument for conversion to opti-

cal using standard SFP modules

Flexible IO Expansion Instrument Family (A common FPGA-based infrastructure that can be integrated with one or two Physical Interface Modules (PIM) for specific I/O requirements)

Chassis Slots 2

FPGA Xilinix Virtex 7 XC7VX330T

Total Memory 2 GB DDR3 SDRAM

RS-485 PIM 32 bidirectional pairs, up to 20 Mbps

RS-232 and IRIG-B PIM 8 RS232 ports with all handshake signals IRIG-B with RS422 I/O or AM or Manchester modulation

HotLink and ECL PIM 4 HotLink II ports, 200 – 1500 Mbp 12 ECL single-ended, up to 60 Mbps

Ethernet PIM 8 ports of 10/100/1000 Mbps under control of HSSub PC or Core Instrument RT Processor Up to 2 Optical ports (requires Optical IO Expansion

Instrument)

Teradyne and the Teradyne logo are trademarks of Teradyne, Inc. All other brand and product names are trademarks or registered trademarks of their respective owners. Information contained in this document is summary in nature and subject to change without notice.© Teradyne 2017, All rights reserved.01-17-17

Specifications

High Speed Subsystem

ATE system. These highly customized solutions are rarely optimized for production throughput, ease of programming, or long-term sustainability. ITA circuitry and single-purpose instruments are particularly subject to early obsolescence, which forces costly replacement, redesign, and inevitably, costly TPS software changes.

The High Speed Subsystem was

purpose instruments and ITA circuitry, the highly reconfigurable HSSub consists of far less total hardware to support. The three-tier processing architecture and TriFlex software provides the power and flexibility to address the broad range of ever-changing UUT requirements. A common methodology for all TPS development is far more efficient than the totally TPS-specific custom approaches.

designed to provide benefits of the highest throughput, lowest development cost, and optimized lifecycle logistics costs. The HSSub advantages over alternate approaches results from the highly refined subsystem architecture, tightly integrated use of best-in-class development tools, and commercial infrastructure for training, documentation, support, and maintenance. Compared to single-