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High Throughput Biosensing PlatformJose Miguel da Fonseca Leitao

INESC-ID / IST, University of Lisbon, Portugaljose.leitao@tecnico.ulisboa.pt

Abstract—A novel multi-channel high performance embed-ded system capable of high throughput biological analysis isproposed in this paper. Although there are other integratedlab-on-chip solutions based on magnetoresistive biochips, theylack the scalability and computational resources to cope withnew biochip designs featuring more than 1000 sensors. A newconfigurable acquisition and processing architecture is proposed,combining dedicated co-processors to perform signal filtering andother computational demanding tasks, with a central processorcontrolling the whole system. The mapping of the architectureinto a Zynq SoC demonstrated its ability to support 19 timesmore sensors, through the use of multiple acquisition channels,while ensuring a sampling frequency 1000+ times higher than theprevious platforms. A new methodology to retrieve the biologicalinformation from the sensed signals is also introduced. Thisapproach is based on the Zoom FFT algorithm and it provides ahigh-resolution spectral analysis, which ultimately increases themeasurement’s robustness to noise.

Index Terms—Biochip, Biosensing Platform, Zoom FFT,FPGA, Signal Processing, Multi-channel Acquisition

I. INTRODUCTION

Conventional biological analysis methods are being grad-ually replaced by sophisticated and compact biochip-basedpoint-of-care devices. These perform common blood or glu-cose analysis at a fraction of the cost and require a muchshorter analysis time [1], [2]. Given the high potential ofthese technologies, the research in biodetection methods andbiochips has significantly grown in the past decade. From thisresearch, new and more efficient methods became possible,providing a valuable tool for several applications, like clinicaldiagnostics, forensics or drug screening. A good exampleis gene expression profiling, where thousands of biosensorsanalyze a given sample in parallel [1]. However, given thecomplexity and computational needs of the electronic sens-ing system, portable and standalone embedded systems withadequate computational capabilities for such high throughputanalysis have not yet been developed.

Recently, magnetoresistive biochips have been developedand integrated with electronic systems to provide completelab-on-chip solutions [2], [3]. INESC-ID and INESC-MNdeveloped a system [4] that has a low throughput but achievesa high sensitivity, high Signal-to-Noise Ratio (SNR) and highdynamic range [5]. The developed system includes all theelectronic circuitry for addressing the biochip, for drivingcontrol signals and for conditioning and acquiring the biochipsignals. It has a single acquisition channel, with a maximumrate of 3.52 k samples per second (sps). However, by usingTime-Division Multiplexing (TDM), it is able to address upto 256 biosensors. The acquired signals are processed by amicro-controller and transmitted to a digital analyzer where,

through a conventional graphical user-interface, the experimentis controlled by the operator or analyst [4].

However, more than 256 sensors are required for many im-portant applications (e.g., gene expression profiling). To tacklethis limitation, a new type of magnetoresistive biochip thatcombines CMOS with thin film fabrication technologies hasbeen recently developed [6]. Currently, faster multi-channelbiochips are being prototyped and will reach more than 1000sensors. These require multiple acquisition channels operatingat a higher sampling rate, thus producing a much highervolume of data and demanding a computation power thatcannot be delivered by the current platform [4].

To deliver the computational power required by the newgenerations of biochips and allow simultaneous acquisition andprocessing at higher sampling rates, a high-performance andconfigurable acquisition and processing architecture is hereinproposed. It uses multiple dedicated co-processors performingFast Fourier Transform (FFT)-based signal filtering, as well asother complex correction algorithms. An additional dedicatedprocessor is used to synthesize the stimulus signals for thesensors, and a central processor to control the whole system.With this approach, a fully autonomous embedded system isenvisaged to allow a standalone operation of the platformand to increase its flexibility and usability. The platform wasprototyped using a development board featuring a Xilinx ZynqSoC, in which all the main components of the system can beefficiently implemented. The results suggest that the systemis able to support the growing demands of computationalresources which will be required by future analysis systemsbased on new generation biochips.

The paper is organized as follows. Section II introduces thebiological detection principles and presents a new approachto extract the biological information from the sensors usingthe Zoom FFT algorithm. Then, the proposed architecturefor the high throughput biosensing platform is described inSection III. Section IV details the system implementation ona Zynq prototyping board and the experimental results areprovided in Section V. Finally, Section VI concludes the paper.

II. BIOLOGICAL SIGNAL DETECTION AND PROCESSING

Figure 1 depicts the biochip schematic representation andits interface with the proposed platform. The laboratory assaybegins by labelling the biological targets under analysis withMagnetic Particles (MPs). Then, a bias current, iB , and anoscillating magnetic field, hB , are applied to the sensors. Uponbiomolecular recognition and washing, the sensors detect thefringe fields created by the MPs that have been capturedby biological probes placed above the sensors [2], [3]. The

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biological information is then extracted by measuring thevariations of the sensor voltage signal, vbind [4].

To reduce the system cost and complexity, the 256 biochipsensors are measured in TDM. Since reaching a low noiselevel requires a high number of samples per sensor, biochipreading times in the previous version of the platform is about4 minutes [4]. Because biomolecular recognition occurs at alow speed, this strategy is acceptable for previous biochips.However, it does not scale well when the number of sensorsgrows to 1000+. To circumvent this, newer biochips areorganized in independent groups of at most 256 elements.With this approach, the total reading time is constrained bythe number of sensors within each group. Hence, the biochipsize can be scaled without increasing the overall reading time.Nevertheless, this also imposes significant changes in the plat-form electronics. Each group must be serviced by a dedicatedacquisition channel comprising signal conditioning circuitsand an Analog-to-Digital Converter (ADC). Furthermore, thedata from each channel needs to be processed in parallel, toallow the observation of the assay evolution in real-time.

Additional characteristics of the biochip must also beconsidered. To avoid the effect of low frequency noise andmaximize the attained SNR, the applied signals iB and hB

must include an AC component. Consequently, vbind needs tobe measured at a specific binding frequency, fbind, which ismainly determined by the modulation induced by the magneticfield hB{f2}, the bias current iB{f1}, the sensor’s response tothese AC signals, and the system’s noise and cross-talk. Due tothe complexity of the biochip technology and of the circuitrythat drives and measures the sensors, it is not easy to determinea good a-priori estimate of the frequency at which the SNR ismaximum. To optimize the biological sensitivity, fbind shouldbe adapted in real-time, by changing the frequencies of iBand/or hB . However, this introduces the added difficulty ofdetermining the signal amplitude at an unknown frequency. Aflexible and tractable method is to use an FFT of the signalacquired at each of the 1000+ sensors, to compute the signalamplitude vbind at the frequency fbind. Although it ensures agood adaptability, this approach requires a sampling frequencygreater than 50 kHz and a frequency resolution as low as1 Hz, for a 24-bit resolution in each sensor. This imposeslarge memory and hardware requirements, constraining thescalability of the system.

A. Zoom FFTThe Zoom FFT appears as an alternative approach to real-

time spectral analysis that allows the resolution in frequencyto be increased within a specific frequency range. This al-ternative approach to real-time spectral analysis that allowsthe resolution in frequency to be increased within a specificfrequency range. Since the frequency resolution is defined as1/∆f = N/fS , and N is mostly constrained by the amountof memory available in the system, this approach reduces thesampling frequency internally, so as to improve the resolutionwithout increasing the memory requirements. The spectrum isfirst shifted and centered around the targeted frequency regionusing complex modulation, and it is then low-pass filtered inorder to isolate the frequencies within the desired range. Afterthese operations are applied, the signal can then be deliberatelyaliased [7] through down-sampling to achieve a higher degreeof resolution. The filtering stage that precedes the down-sampling phase is what prevents the frequency componentsthat lie outside of the specified band to appear in the finalzoomed spectrum, at least at a significant a level.

Despite the increase in the frequency resolution, the ZoomFFT constrains the spectral analysis to a narrower frequencyband that of the raw FFT. Nevertheless, this is totally compat-ible with the type of analysis that is targeted in the concernedbiosensing application, since most of the detail is only requiredat frequencies near fbind. This section demonstrates how to usethe Zoom FFT method to improve the SNR of the simulatedsignal at a specific band near fbind for a fixed number ofevaluated points, N = 216 = 65536. The used data setcorresponds to a signal with fh = 211 Hz, fi = 997 Hzand fbind = fi + fh = 1208 Hz, sampled at fS = 6000 Hz.

Complex Modulation: The shift property of the DiscreteFourier Transform (DFT) states that is possible to shift thespectrum of a signal by multiplying it, in the time domain, bya linear phase P (m). A circular shift of f0 Hz is achievedby making m = f0/fS . Figure 2(a) shows the originalspectrum of the simulated signal and a shifted version of thesame spectrum is depicted in figure 2(b). This operation wasperformed with f0 = fbind, so that the frequency of interestis shifted towards the 0 Hz component.

Low-pass Filtering: In signal processing, filtering can bedefined as an operation that is able to modify the frequencyspectrum of a signal by attenuating or amplifying specificfrequency bands. A low-pass filter allows low-frequency com-ponents to pass and attenuates the frequencies above a certainthreshold called cut-off frequency. The ideal filter would have

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(a) Original spectrum of the signal

(b) Shifted spectrum after complex modulation

Fig. 2. The complex modulation stage of the Zoom FFT.

a unitary gain at the pass-band and an infinite attenuationat the stop-band. Real filters are designed to approximatethis ideal frequency response. Increasing the quality of thisapproximation is usually accomplished at the expense of anincrease in the computational complexity.

Today there are numerous tools to automatically find theoptimal filter coefficients for the target frequency responsespecifications, such as the MATLAB’s Filter Design andAnalysis Tool. Using this tool, a Finite Impulse Response(FIR) filter was generated with an order of 235 and a cut-offfrequency of 90 Hz. The magnitude of the obtained frequencyresponse is depicted in figure 3(a). After applying such a high-order filter to the shifted signal’s spectrum the componentsoutside of the [−90, 90] Hz interval are successfully attenuatedto the noise level. As seen in figure 3(b), the main goal of thefiltering stage in the Zoom FFT algorithm, which is to limitthe band of the signal to the vicinity of the DC component,was accomplished.

Down-sampling: Down-sampling a signal by a positiveinteger decimation factor M is implemented by discardingM − 1 consecutive samples and retaining every M th sampleof the original sequence. The resulting signal has an effectivesampling rate of fSd = fS/M , which means that the Nyquistfrequency for this new sequence is M times lower than theoriginal. When the band of the signal is not limited to thisnew Nyquist frequency, the down-sampling will result intounwanted aliasing. This is usually an undesirable effect andthat is the reason why down-sampling is often preceded by

(a) Frequency response of a high-order low-pass filter

(b) Shifted spectrum after low-pass filtering

Fig. 3. The low-pass filtering stage of the Zoom FFT.

anti-aliasing filtering.In fact, the low-pass filtering stage of the Zoom FFT is

performed exactly to prevent unwanted aliasing to occur.However, once the signal spectrum is limited to a narrowerband, the aliasing that results from down-sampling turnsinto a benign effect, since it reinforces the targeted signalenergy within that frequency band. In this particular case, theconsecutive superposition of aliased spectra translates into aspectrum with greater detail. As the spectrum gets narrower, sodoes the frequency step, which means that a higher resolutionin frequency is obtained.

The zoom effect that results from down-sampling is valid forany signal but it would be useless for high-frequency signalswithout the complex modulation stage. This stage is essentialto translate the region of interest to the low-frequency band.From that point, the FFT is able to produce a high resolutionin the frequency spectrum within the targeted range, providedthat the frequencies that lie outside the band are significantlyattenuated by the filtering process. In this case, since the signalwas limited to a band of ±90 Hz, the maximum M factorthat would keep this band within the new Nyquist frequencywould be M = (fS/2)

90 = 33.3(3). An M = 32 was selected,and after the three pre-processing stages of the Zoom FFT areapplied to the incoming sequence, the N -point FFT producesthe spectrum depicted in figure 4.

From a different perspective, the increase in frequencyresolution might also be attributed to the increase in thesampling time. Since the effective sampling frequency at theinput of the FFT block is reduced, it takes a longer time toproduce N samples. In this way, a longer period of exposure is

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Fig. 4. Zoom FFT output with a 32× zoom factor around fbind.

intuitively associated with a reduction of the noise floor, sincethe random noise is usually assumed to have a zero mean.Furthermore, after the decimation, the same amount of energywill be distributed among a greater number of frequencies,which will naturally cause an individual decrease of the noisepresence in each component. Summing up, this method is ableto provide a high resolution in the frequency analysis, thusbeing suitable for the biosensing application in question.

III. PROPOSED ARCHITECTURE

The computational performance required to ensure theresolution and reliability of biorecognition assays can beachieved by optimizing the processors’ architecture and byincreasing the exploited parallelism with the usage of multi-core structures. Nonetheless, similarly to what happens withmost high throughput applications, it would be insufficientto exclusively address the performance limitations, since thebottleneck may also arise in the communication channels, suchas the one connecting the acquisition circuits to the processingunit. Furthermore, due to the significant complexity of theunderlying algorithms, the processing unit must be able tostore and manipulate large datasets, making it clear that ahigh memory bandwidth and capacity are necessary to takefull advantage of the enhanced processing capabilities.

The architecture proposed to fulfill the requirements of thehigh throughput biosensing platform is depicted in figure 1.A high-speed serial interface must be selected in order toprovide a fast communication between the ADC and the setof dedicated cores where the most computational intensivetasks are handled. All components, including the generatorof the stimuli signals, are configured by a General PurposeProcessor (GPP) which, aside from acting as the main systemcontroller, can also perform auxiliary computations on theacquired data. This processor shares its main memory witha set of I/O devices, such as the input peripherals used tocontrol the experiment and the display on which the resultsare presented to the user. A network interface is also included,allowing the processed data to be transferred to an externaldatabase, easily available to other users.

The following subsections provide a more detailed descrip-tion of the embedded system main building blocks.

A. General Purpose Processor and Main MemoryA GPP is the most suitable device to configure, initialize

and control the several system components, thus playing a keyrole in allowing an easy system integration. Aside from actingas the main system controller, this central processor can alsoperform auxiliary computations on the acquired data. Sincemost of the system’s hardware components are able to operateautonomously and do not require constant intervention of theprocessor, the main user interface software can run in thisunit, thus avoiding the need for an external Personal Computer(PC). This is an important step to provide a fully embeddedbiosensing platform which combines all the necessary featuresto perform a biological assay in a single system.

Ideally, the processor should also have Operating System(OS) support in order to benefit from the available softwarepackages that provide complex system management function-alities, graphical libraries for developing the user’s front-endapplication, and high-level interfaces to the standard I/O andmemory peripherals. Automatic multi-task scheduling is alsoan advantage of using an OS, since it allows the processorto efficiently monitor the co-processors at the same time isrunning the user interface and displaying the processed data.

B. High-throughput sensor interfaceAs introduced in section I, novel high-density biochips are

organized in groups of at most 256 biosensors, which can beindependently addressed and read through multiple acquisitionchannels. With this approach, the otherwise excessively longreading time is only constrained by the number of sensorswithin each group. Hence, the biochip size can be scaledwithout increasing the overall reading time.

In the proposed architecture, each acquisition channel islinked to one of the biochip sensor groups through an in-dividual ADC, which digitalizes the voltage signal acquiredfrom the selected biosensor prior to being processed by thedigital signal co-processors. The envisaged state-of-the-art24-bit ADCs can operate at a maximum of 4 MSamples/s, thusresulting in a maximum throughput per channel of 96 Mbit/s.Therefore, the absence of a high-speed data channel wouldseriously compromise the overall throughput and prevent thesystem to take full advantage of a high sampling frequency,which is essential to minimize the effect of the low-frequencynoise in the acquired signals.

A typical solution to achieve high transmission rates ongeneric physical interfaces is to use the Low-Voltage Dif-ferential Signaling (LVDS) standard, where susceptibility toelectromagnetic noise interferences is reduced by doublingthe number of transmission wires per channel. Since the mostimportant applications of biochip technology are duly relatedto the health industry, it is critical to prevent data corruptionto guarantee the maximum correctness of the obtained results.Therefore, this option provides a reliable transmission betweenthe ADCs and the co-processors while ensuring the compati-bility with most of the high-resolution ADCs, despite the slightincrease in hardware resources.

On top of this physical layer, a Serial Peripheral Interface(SPI) bus protocol is considered, to provide configuration and

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Fig. 5. Specialized Zoom FFT co-processor architecture with multi-rate filters.

addressing capabilities based on a SPI master/slave controller.Besides being cost-effective, these simple communication con-trollers are also easily configurable by software, which furthersupports the usage of a GPP as a centralized control unit forthe whole system.

C. Specialized Co-processorsThe specialized Zoom FFT co-processors are responsible for

measuring the amplitude of the sensors binding signal, vbind,at a specific frequency. This signal is estimated using a zoom-in FFT approach. In a first step, an FFT is performed witha low frequency resolution, and by using a subset of sensorsin the same channel. This provides a coarse and preliminaryidentification of the best fbind frequency to measure the vbind,while keeping the hardware resources and power consumptionat tolerable levels. After identifying the fbind range, band-passfiltering and signal demodulation are performed, to displacethe frequency of interest down to base band. This allows thecomputation of multiple Zoom FFTs (one per channel) with ahigher bit and frequency resolution, while still confining therequired resources. Also, to increase SNR and achieve systemscalability, the zoom-in procedure can be performed as manytimes as required.

After the complex modulation the signal is split into twostreams, corresponding to the real and the imaginary part ofthe modulated signal, as shown in figure 5. Therefore, two low-pass filters are required to remove the frequencies outside thezoomed band so as to prevent the unwanted aliased spectrato appear in the down-sampled signal. The main advantageof multi-rate filters is the ability to combine the samplingconversion and the filtering operations in order to increasethe overall computational efficiency. As previously explained,down-sampling is achieved by periodically discarding samples,so when the filtering operation precedes the down-sampling,most of the filtered results are thrown away. In the case ofmulti-rate filters, the down-sampling and low-pass filteringare performed by a single filter with reduced order thatonly produces results at the new (lower) sampling rate. Asproposed in [8], a cascade of Cascaded Integrator Comb(CIC) and FIR filters is considered, as it provides a resource-efficient hardware implementation of the anti-aliasing stageof the Zoom FFT. Finally, a pipelined FFT core computesthe resulting zoomed spectrum of the signal and provides thedesired output in the frequency domain. The signal is alsowindowed prior to the FFT computation in order to removethe discontinuities at the boundaries of the input frame. Anadditional squaring module is also required to compute thesquared magnitude of the complex FFT output, which relatesto the energy of the signal at each frequency and consequentlyto the amplitude of the sensor’s binding signal, vbind.

Due to the involved computational complexity, a reconfig-urable FPGA device is regarded as the most suitable tech-nology to accommodate these specialized co-processors. Itcombines the required high performance level, while stillconferring the flexibility to change or update the adoptedprocessing algorithms. In particular, multiple configurationscan be stored in memory: one for each zoom-in level. In run-time, the user starts by observing the coarse signal spectrumof the initial subset of sensors. Then, the most favourabledemodulation frequency and spectrum band is selected. Thiswill trigger the FPGA reconfiguration and the deploymentof the specialized co-processors in hardware, configured withthe target demodulation frequency. At this point, the user canobserve the binding signal for each sensor.

D. Stimulus signal generator

As referred in Section II, reference AC signals must be sup-plied to the biosensors, to produce a measurable response. Theamplitude and frequency ranges of these stimuli is partiallyconstrained by the considered biochip technology. However,since the noise level at which the measurements are exposedto is inversely proportional to the frequency of these signals,the accuracy of the results is strongly constrained by thisparameter. As a consequence, a variable and configurablefrequency generator, which can be adjusted and parametrizedby the GPP, will ensure the adaptability of the biosensingplatform to new generations of the biochip. The required signalgenerators can be easily implemented by using Direct DigitalSynthesizers (DDSs) deployed in the reconfigurable fabric andcontrolled by the GPP.

E. I/O Peripherals and User Interface

A convenient set of I/O peripherals are required to make thisbiosensing platform a truly standalone analysis and diagnosissystem. These modules not only allow the user to take fullcontrol of the experiment, but also offer the visualizationmeans for clinical interpretation purposes. The standard set ofcomputer peripherals (i.e. USB keyboard / touch screen paneland HDMI monitor) is regarded as the most appropriate meansto prototype this interface, conferring the desired usabilityexperience. Furthermore, thanks to the OS running on the GPP,the evolution from the proposed system to a final commercialproduct will require little engineering and adaptation efforts.

IV. IMPLEMENTATION

The Xilinx Zynq 7000 Extensible Processing Platform wasconsidered the most appropriate prototyping technology forthe proposed embedded system. This particular System on aChip (SoC) includes a state of the art reconfigurable fabricand it offers most of the features required by the proposedsystem. This section starts with a brief overview of the Zynqarchitecture, followed by a description of the implementedscalable and high-throughput biosensing platform.

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A. Zynq SoC Architecture

The Zynq SoC integrates two independent modules in thesame chip: the Processing System (PS), featuring a dual-coreARM Cortex-A9 GPP, and the Programmable Logic (PL),consisting of Xilinx 7-series Field Programmable Gate Array(FPGA) fabric. In addition to the ARM processors and theassociated Double Data Rate (DDR)-memory controller, thePS also integrates a collection of industry-standard communi-cation interfaces.

At boot time, the PS configures the PL by means of theProcessor Configuration Access Port (PCAP) and initializesthe system clocks. All these configurations, including thebitstream for the FPGA can be enclosed in a single file, calledthe First Stage Boot Loader (FSBL). Through the PCAP, theARM GPP is able to exploit the software-driven dynamicpartial reconfiguration capabilities of the reconfigurable fab-ric, thus promoting an adapted and optimized usage of thereconfigurable part of this SoC.

The available low-latency and high-bandwidth communica-tion channels interconnecting the processor and the reconfig-urable fabric, enable the development of embedded systemsrequiring levels of performance that could not be reachedby equivalent two-chip solutions. Hence, the PS-PL intercon-nection emerges as the centerpiece of the Zynq architectureby providing support for an efficient hardware/software co-design that relies on three types of connectivity ports, basedon the Advanced eXtensible Interface (AXI) bus protocol,namely the General-Purpose (AXI-GP), the High-Performance(AXI-HP), and the Accelerator Coherency Port (AXI-ACP)AXI interfaces. In addition, an hard-core ARM PL330 DMAController (DMAC) with eight channels is also available inthe PS to perform automatic data movements within theprocessor’s memory space.

The Zynq provides one AXI-ACP and four AXI-HP portsto achieve high-throughput transfers between the PL and thePS. While the first provides direct acess to the L2 cache ofthe GPPs, the second connects to the DDR memory controller.There are also four AXI-GP ports, two slaves and two masters,connecting the PL to the central interconnect in the PS, beingsuitable for a lower bandwidth communication. From the eightchannels of the PL330 DMA controller, four are available atthe PL end, thus providing an additional interface to connectthe FPGA fabric to the GPP or to the main memory.

The least demanding option in terms of implementationcomplexity is the one using the GPPs to move data betweenthe PS and PL, thus removing the need to handle events froma separate DMA. In this configuration, access to the PL isaccomplished through one of the two AXI-GP master ports,capable of addressing memory-mapped peripherals placed inthe PL, provided that an inexpensive AXI slave interface isimplemented to service the bus requests issued by the proces-sors. However, spending a significant number of processingcycles of the GPP to perform simple data movements is notefficient, since the computational power that could be appliedto more complex tasks is essentially wasted during theseoperations. Furthermore, this method is rather limited in termsof throughput, achieving an estimated maximum transfer rate

of 25 MB/s.On the other hand, the data movement methods involving

Direct Memory Access (DMA) operations require little GPPintervention, thus being more suitable for large transfersbetween the PL and the PS. The ARM DMAC is able toperform transfers at up to 600 MB/s and is also very low-demanding in terms of PL resources, since it only requires amemory-mapped slave, just as in the GPP controlled I/O case.Nevertheless, programming this controller can be a complextask, not being the best option for a first prototyping phase.

Additional DMA options are available when using a PLperipheral as a bus master. This AXI master interface can beconnected to the AXI-GP, AXI-HP or the AXI-ACP. The firstis a general purpose port that provides a similar throughput tothe ARM DMAC. However, it is substantially more complex interms of hardware implementation due to the added difficultyof implementing master functionalities. In terms of softwareimplementation, however, this option is simpler since it doesnot require programming the controller. In order to achievehigh-performance data transfers between the PS and the PLthe AXI-HP or the AXI-ACP should be used. Although thebus master implementation in the PL is similar to the previouscase, the AXI-HP takes advantage of a direct access to theDDR memory controller to achieve peak throughputs as highas 1200 MB/s. The AXI-ACP connects directly to the sharedL2 cache of the GPPs, thereby being equivalent in terms ofattained throughput. Nevertheless, it uses many word lines inthe cache, which might degrade the performance of the GPPssince the L2 cache holds both instructions and data. Therefore,this last option should only be used for low to medium-sizeddatasets, in situations where latency is critical. Applicationsrequiring fast transfers of large data sets between the PL andthe PS should use the AXI-HP instead.

B. Prototype ImplementationThe ZedBoard is a low-cost development board suited for

rapid prototyping of systems based on the Zynq-7000 chipand it was selected for prototyping the proposed biosensingplatform. Due to the wide variety of peripherals availableon the board, this platform provides the main requisites formost of the applications targeted by Zynq devices, such assoftware acceleration, embedded processing and developmentof mobile applications. In the interest of increased flexibility,the PS and PL I/Os are easily accessible through severalexpansion connectors, thus allowing the Zynq to be connectedto additional peripherals that are required by the particularbiosensing application. The Zedboard provides 512 MB ofDDR3-Random-access Memory (RAM), connected directly tothe memory controller of the Zynq. In addition, an FPGAMezannine Card (FMC) connector enables the access to thegeneral purpose pins of the Zynq chip, which can be usedeither to interface the ADCs or to output control signals forthe stimulus required by the biochip. The on-board High-Definition Multimedia Interface (HDMI) port and transceiverenable the use of modern desktop or embedded monitors todisplay information to the user. An Universal Serial Bus (USB)interface is also provided, and can be used to connect conven-tional computer peripherals, such as the keyboard/mouse pair

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Fig. 6. Single-channel implementation overview.

in order to register the user’s input. The large set of availableI/O interfaces in this development board enables the designerto explore a diversity of features in Zynq-based designs.

The first step in implementing the proposed architectureis to map its constituents into platform-specific components.Thanks to the inner structure of the selected platform, mostof the components are readily available and embedded inthe PS, such as the GPP, the user input peripherals and themain memory controller. The remaining components, on theother hand, can be effectively placed in the PL, namely theDDS for stimulus generation, the SPI controller for the fastADC interface, and the Zoom FFT Co-processor in charge ofextracting the biological information from the sensed signals.Standard Hardware Description Language (HDL) files willbe used to describe and implement all of these individualcomponents.

While there are tools and open source repositories thatcan facilitate the development, integrating a large numberof distinct components in a single system is far from beingtrivial. The establishment of control and data communicationpathways is a key step in the design of a well organinzedand functioning system, thus requiring some additional en-gineering effort. From the previous analysis of the differentPS-PL communication interfaces, it is clear that there arespecific communication methods which are more suited fortransmitting control commands while others are better usedfor large data transfers.

Consequently, the AXI-GP port was selected for exchangingcontrol and status commands between the GPP and all ofthe components in the PL. A single Control Unit (CU)equipped with an AXI slave interface is able to receive singleword read/write requests from the GPP and broadcast thecorresponding control signals to any sector of the hardwaresystem in the PL. In addition, the GPP is able to retrieve thestatus of any core placed in the PL by reading the memory-mapped address of a particular control register. The role of thiscentralized CU is basically to store the configurations comingfrom the GPP and formatting them as control words whichcan be easily interpreted by each unit of the PL.

Due to the large size of the FFT output frames and inorder to maximize the available throughput, the AXI-HPchannel was selected to hold the data transfers between the

co-processors and the GPP. Since the PL is able to accessto the system’s main memory through this high-performancechannel, this connection can be seen as a simple sharedmemory communication scheme, typical of DMA peripherals.From a software perspective, the GPP should have a read-onlyaccess to the memory region that is being written by the co-processing unit, enabling it to retrieve the processed data andpresenting it to the user.

However, as long as the acquisition is running, the co-processing unit is constantly producing new outputs. Thus,some form of synchronization is required to ensure coherentdata transfers. This motivates the implementation of a FrameManager to meet this guarantee that no frame is rewrittenwhile its being read by the GPP. This unit receives the locksignals coming from the GPP, which are passed by the CU, andtriggers an Interrupt Request (IRQ) to alert the processor whenthe locked frame is available for reading. By keeping track ofthe locked frames, the Frame Manager is able to update theaddresses on which the next frame is written in order to avoidunwanted collisions. In addition, the Frame Manager requiresan AXI master interface supporting burst transfers in order toefficiently write the frames to the main memory.

C. System I/O and User InterfaceTwo different interfaces need to be supported by the

biosensing platform: (i) an SPI-based interconnection witheach ADC channel and with the stimuli generator; and (ii) theinterface with the human operator. The connection to thebiosensing ADC and with the stimuli generator are accom-plished by an off-the-shelf and open-source core implementa-tion of the SPI protocol, available at OpenCores.org [9]. Theselection of this particular core took into account its particularcharacteristics in terms of versatility and resource efficiency.

The user interface is accomplished by using the HDMIgraphics port and an USB keyboard (the latter is planned to bereplaced by an USB touch-screen panel). Although an HDMIinterface already exists in the Zynq platform, the controllerhas to be implemented on the reconfigurable fabric. For this, acontroller module from a reference design targeting an HDMIoutput interface was used, along with the data streaming blocksrequired to handle DMA video streams [10].

The DMA engine is connected to one AXI-HP port and tothree DMA channels of the PL330 controller, thus enablingthem to directly gather audio and video data from the mainmemory. These additional DMA connections between the PLand the PS are omitted in figure 6 so as to decrease thecomplexity of the depicted block diagram. The HDMI controllogic, which also resides on the PL side, is connected to anAXI-GP interface and mapped into the memory-space of theOS, allowing the usage of existing software device drivers tocontrol the display connected to the HDMI port.

D. Acquisition and Processing StagesRegarding the implementation of the acquisition and pro-

cessing blocks, the performance and the scalability are thetwo major concerns that need to be properly addressed. Themaximum sampling rate and the resolution in frequency are

8

TABLE IFFT HARDWARE RESOURCE OCCUPATION.

FFT size Hardware resources (per channel) Maximum(#samples) LUT (53200) BRAM (140) DSP48 (220) #channels

1024 3686 (7%) 8 (6%) 24 (11%) 82048 4375 (8%) 11 (8%) 31 (14%) 64096 4765 (9%) 14 (10%) 31 (14%) 616384 7201 (14%) 28 (20%) 40 (18%) 432768 7916 (15%) 55 (39%) 49 (22%) 265536 7254 (14%) 106 (76%) 103 (47%) 1

the main factors determining the system performance. Thus,they need to be maximized to cope with the demands ofthe next generation of biochips. Since the considered high-resolution ADCs work at a maximum of 4 MHz, this valuewas established as the target sampling rate for each acqui-sition channel. Furthermore, to finely tune the frequency ofthe binding signal, a frequency resolution of 0.5 points/Hz,corresponding to a frequency step of 2 Hz, was consideredto be sufficient for measurements occurring at such a highfrequency. This corresponds to an FFT of 64k or 32k points,and a zoom factor of 32× or 64×, respectively. In terms ofscalability, the number of supported acquisition channels alsoneeds to be maximized while maintaining the performancelevel in each channel.

Parallel Processing : A possible approach to implement thedesired multi-channel system is to replicate the acquisition andprocessing components per channel. In fact, the architecturewas designed considering that each acquisition channel has anindependent co-processor, so that the scalability is exclusivelylimited by the amount of hardware resources available inthe PL. The Zoom FFT was introduced in section II as atechnique to meet the considered frequency resolution require-ments. However, as the zooming factor increases, so does thecomplexity of the required anti-aliasing filters. Therefore, theresources occupied by the FFT and by the low-pass filtersneed to be balanced in order to obtain the desired resolutionin frequency.

As a first approach to implement the biosensing platformin the Zynq device, a single-channel prototype was studiedand implemented to demonstrate the capabilities of this basetechnology in providing real-time spectral analysis. Afterimplementing this standalone system, some preliminary resultswere obtained for the scalability of the system when usingthe Xilinx FFT core. From these results it was concludedthat a direct extension of this implementation to multiplechannels was fairly limited in terms of scalability, assumingthe frequency resolution needs to be preserved. Lookingsolely at the area occupied by the FFT cores, as presentedin table I, it is clear that is impossible to implement morethan two channels of high resolution FFTs, with 32k or 64kpoints, in the considered Zynq device. Furthermore, since theADC’s sampling frequency is much slower than the maximumclock frequency at which these cores are able to operate, thehardware resources are noticeably being underused. Therefore,from this experience, a new implementation strategy wasdevised to enable a more efficient usage of the hardwareresources of the PL.

Serial Processing

In essence, the acquisition stage is the only one which hasto operate in parallel, since the biological reaction has to beobserved simultaneously in all the channels. However, once thesampled data is retrieved and buffered, it can then be seriallyprocessed, as long as the processing stage is able to achievethe necessary throughput to avoid stalling the acquisition. Thisis only possible due to the difference between the maximumsampling rate and the maximum operating frequency for theco-processors in the PL. Thus, by aggregating the processingof several ADC channels in a single co-processor operatingat a much higher frequency, it is possible to reduce therequired amount of resources. Furthermore, the implementedco-processor is able to provide a higher resolution in frequencywhen compared to the option with several co-processors, sinceit is now possible to have a larger area for both the FFT andthe filter hardware cores.

Nevertheless, this adaptation is still impracticable unlessthe First in, First out (FIFO) buffers are able to store afull frame for each channel, given that the FFT core expectsseparate frames at the input in order to work properly. Onceagain, storage becomes a critical issue, since the amount ofmemory required by this buffering stage can not be met by theembeddded Block RAMs (BRAMs). For instance, four framesof 32k samples, 24-bit wide, would occupy at least 84 BRAMsout of the available 140 in the Zynq 7020. After adding theBRAMs used by the Xilinx FFT core, the maximum number ofBRAMs is exceeded. Therefore, the buffering must take placein the external main memory so as to avoid compromising thesystem’s scalability.

In addition to multiplexing the data from each channel, anew fetching unit needs to be placed in order to retrieve theserialized frames from the main memory so that they canbe processed. Both these units need to connect to separateAXI Burst Master Controllers to perform independent reador write bus requests to the memory bus. Whenever a fullframe is written by the Channel Multiplexer to the mainmemory, an issue flag is activated so that the Frame Fetchercan begin to fetch it. A similar operation needs to takeplace after the decimation occurs, since the fetched framesare compressed after the zooming stage. Basically, M framesneed to be evaluated so that a full FFT frame can be formedafter an M-times decimation. This requires the inclusion of ademultiplexing unit and an additional fetching unit betweenthe Zoom and the FFT stages. The adopted implementation ofthe acquisition and processing stages is depicted in figure 7.

V. EXPERIMENTAL RESULTS

After defining the main implementation options discussedin the previous section, the hardware and software componentswere individually designed and tested. The hardware unitswere synthesized, placed and routed in the Zynq XC7020 us-ing the Xilinx Integrated Software Environment (ISE) DesignSuite version 14.4. The software was developed and cross-compiled for the ARM-v7 architecture using GNU CompilerCollection (GCC) 4.6.3 on Ubuntu 12.04. For the graphicallibraries, Qt 4.8.1 was used, together with the Qwt plug-in

9

Fig. 7. Adopted implementation, using separate co-processors for the Zoom and for the FFT computation.

Fig. 8. PL area results for a variable number of acquisition channels.

version 6.1.0. In the current prototype, the ARM dual-coreGPP was clocked at 667 MHz and the DDR-RAM at 533MHz. The PL subsystem was connected to a 50 MHz clock.

The number of parallel acquisition channels could be lim-ited, at some extent, by the amount of resources occupiedby the hardware system, since each ADC requires a directinterface to be placed in the PL side of the Zynq. In thecurrent implementation, the only components that need tobe replicated as the number of channels increases, are theSPI Controller and the multiplexed buffers inside the ChannelMultiplexer. The number of instantiated channels is controlledby a generic input parameter in the corresponding HDLfiles. By consecutively changing that parameter, the systemwas synthesized, placed and routed for a variable number ofchannels, giving rise to the area results depicted in figure 8.The obtained results, in terms of occupied LUT cells andBRAMs, make clear that the scalability of the system is farfrom being bounded by the available resources in the PL.Therefore, the selected implementation strategy was successfulin improving the area efficiency of the design.

Nevertheless, the area efficiency that resulted from time-sharing the hardware resources in a single co-processing unit,imposed an obvious limit to the maximum system throughput.A processing throughput of 4 MSamples/s per channel isrequired to concurrently sample the multi-channel biochipdevices. The dark blue curve in the figure 9 represents thatlinear relationship for an increasing number of channels.However, the output data rate is ultimately limited by thesoftware throughput since the processed results have no use if

they can not be digested by the GPP in order to be presented,in some form, to the user. Therefore, a maximum of 9 channelsare supported when performing a first and coarser FFT analysisat full speed.

The situation is slightly different once the zooming modeis activated. Both for a 4×, 16× or 64× decimation, thethroughput at the Zoom Co-processor output is decreased bythe own zoom factor, as represented in the light blue and pinkcurves of figure 9. This means that the input and consequentlythe output data rates of the FFT Co-processor in the followingprocessing stage are considerably reduced. Hence, the numberof channels can be increased as long as the throughput thatis generated after decimation stays below the software limit.This ensures that the FFT results can be retrieved by the GPP.

In this case, the Zoom Co-processor is the only co-processing unit which has to operate at the full acquisitionspeed of 4 MSamples/s per channel. However, since the datatransfers between the Channel Multiplexer are mediated by theexternal memory bus, the maximum throughput is naturallyconstrained by the bus efficiency. For an operating frequencyof 150 MHz, the maximum bus throughput was estimated tobe 75 MSamples/s. Thus, the maximum number of channelsis limited by this throughput boundary since it is lowerthan the one imposed by the Zoom Co-processor itself whenoperating at 100 MHz. In the current implementation a totalof 19 parallel channels are supported when performing theZoom FFT.

The attained scalability is in line with the maximum numberof parallel ADC interfaces supported by the Zynq device. Byusing the prototype implemented in the Zedboard, between9 and 10 channels, depending on the operating mode, canbe implemented using the general purpose differential pinsaccessible in the development board. When moving to thefinal version of the system, using a custom developed board,a total 19 channels in the zooming mode can effectively beimplemented, taking full advantage of the wide number of pinsavailable in the Zynq.

VI. CONCLUSION

An architecture for a scalable and high-throughput biosens-ing platform was proposed to meet the performance require-ments of novel high-density biochip devices. In contrast withthe previous platform, the proposed system is able to read

10

Fig. 9. Multi-channel throughput requirements versus system constraints.

several biosensors in parallel through the use of multiple ac-quisition channels. Furthermore, the digital signal processingtechnique used to retrieve the biological information from thesensed signals was improved, allowing a higher sensitivity tobe achieved in the performed bioassays. This new approachdecreases the susceptibility to the various noise sources presentin the system, by enabling the runtime adaptation of thebinding frequency so as to avoid the most noisy regions ofthe spectrum. A fine tune of this parameter naturally requiresa spectral visualization with a high resolution in frequency.Hence, the devised system provides a configurable spectralanalysis of the sensed signals, being able to successivelyincrease the resolution in frequency thanks to the Zoom FFTtechnique. This digital signal processing algorithm allows thefrequency spectrum to be zoomed across a selected frequencyband, by adding an additional pre-processing stage to theFFT computation. In this stage, the signal is shifted in thefrequency domain, and then it is filtered and decimated, soas to confine the spectrum of the signal to a given frequencyregion. Therefore, a higher resolution can be achieved, withina selected interval of frequencies, without the usual increase inthe number of evaluated FFT samples which would eventuallylead to a prohibitive demand in both memory and computa-tional resources.

The biosensing system was successfully prototyped usingthe Xilinx Zynq reconfigurable SoC as the base technology,and the Zedboard as the main development board. This hybridGPP-FPGA device was found to be particularly suitable forimplementing complex embedded systems that need to com-bine a high computational performance with the flexibility ofsoftware-based interfaces and standard I/O peripherals. Thedevised system is able to meet the throughput requirements ofthe new generation biochips by offloading the most computa-tionally intensive operations to dedicated co-processing unitsplaced in the FPGA side. The processed data frames are thenwritten to the system’s main memory through a specializedcommunication channel, which is also a distinctive feature ofthe Zynq. On the other hand, the software running on theon-chip GPP is able to access to that shared memory regionin order to retrieve the processed frames and to display themto the user via an HDMI display. Moreover, all the systemcomponents, including the dedicated co-processors, can becontrolled by the user through the software GUI, using a set

of generic input peripherals such as the mouse/keyboard pairor even an embedded touchscreen, thus avoiding the need foran external analyzer.

After examining the implementation results, it is clear themaximum number of supported channels is not limited bythe area but rather by the attained throughput. The overallthroughput is constrained by the hardware co-processors, bythe memory bus and by the software running on the GPP.When applying the raw FFT, a maximum number of 9 channelswas obtained, limited by the software throughput. In the ZoomFFT mode, this number is extended to 19, being only limitedby the memory bus efficiency. Nevertheless, implementingmore than 10 acquisition channels requires a PCB other thanthe Zedboard, in order to gain access to additional I/O pinsnecessary to the interface with the ADCs.

In summary, the overall scalability of the system is essen-tially limited by the structural constraints imposed by the Zynqdevice, which means that new implementation strategies needto be devised to take full advantage of larger chips. As anexample, the newly launched Zynq 7100 provides roughlyten times more DSP units and five times more LUTs andBRAMs than the currently used device. Nevertheless, the PSand the PS-PL communication infrastructure is exactly thesame and the existing bottlenecks are not expected to beimproved due to the increase of the available PL resources.Therefore, although the proposed architecture remains validfor an indeterminate number of channels, the platform-specificimplementation is always a laborious process and can leadto considerable changes in the internal organization of thesystem, as demonstrated in the currently developed prototype.

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