highly linear low noise amplifier - texas a&m university linearized lna...amsc low noise...
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1
AMSC
Highly Linear Low Noise Amplifier
Sivakumar GanesanTexas A&M [email protected]
Advisors: Dr. Edgar Sánchez-SinencioDr. Jose Silva-Martinez
Analog and Mixed Signal Center
Department of Electrical & Computer Engineering
2
AMSC Outline
• Motivation• Background• Proposed Solution• Testing Strategy• Experimental Results• Conclusion
3
AMSC Motivation
• Numerous co-existing wireless standards and wireless equipment
4
AMSC Frequency Spectrum
• Limited spectrum allotted to each user• Possible large interferers from other
channels in-band and out of band
5
AMSC Receiver Architecture
• Antenna receives the entire band of signals • Stringent requirements on the receiver front-end • BPF filters the out of band channels• LNA receives the entire in-band signals• In-band channel interference problems in LNA
– Blocking– Intermodulation
6
AMSC Blocking
– If , a large interferer results in signal being “blocked”
)()()()( 33
221 txtxtxty ααα ++=
tAtAtx 2211 coscos)( ωω +=
......cos23)( 11
2231 +⎟⎠⎞
⎜⎝⎛ +≅ tAAty ωαα
03 <α
7
AMSC Intermodulation
• Third order intermodulation (IM3) components corrupt the signal resulting in distortion
tAtAtx 2211 coscos)( ωω +=
)2cos(43)2cos(
43)( 121
223212
2133 ωωαωωα −+−= AAAAtyIM
DesiredChannel
Interferers
LNA
IM3
DesiredChannelInterferers
8
AMSC Linearity Measurement
• Third order Input Intercept Point (IIP3) is a measure of circuit non-linearity
• Fundamental = ,IM3 = 334
3 AαA1α
9
AMSC Low Noise Amplifier
• Low Noise Amplifier– First amplifying block in a receiver– High gain, Low Noise Figure– Presents amplified signals (desired + IM3) to
mixer• Highly linear LNA with high gain and low
NF required
10
AMSC Background
• Existing Linearization Techniques– Optimum Biasing– Negative Feedback– Input Impedance Frequency Termination– Feedforward Cancellation
11
AMSC Optimum Biasing
• Current =• IIP3= • gm3=0 results in very high IIP3
......33
221 +++= gsmgsmgsmd vgvgvgi
3
1
34
m
m
gg
12
AMSC Optimum Biasing
• Drawbacks– High IIP3 obtained over a narrow region– Process variations degrade IIP3– Limited voltage gain due to restricted input
transconductance (gm1)– Poor NF
13
AMSC Negative Feedback
• Popular in baseband circuits to improve linearity
• IIP3= ( ) β1
31
22
3
3
1 ,
121
134
mo
o
o
mm
m
o
m
m gT
TT
ggg
Tgg
=
⎟⎟⎠
⎞⎜⎜⎝
⎛+
−
+
14
AMSC Negative Feedback
• Linearity improvement at the expense of circuit gain
• Second order non-linearity effect on IIP3• gm3<0, leads to further deterioration• Feedback techniques not suitable at RF
frequencies
15
AMSC Negative Feedback
• Inductor LS acts as a feedback network
• Provides best gain and noise performance
• Poor linearity performance due to second order non-linearity feedback
Cascode LNA
16
AMSC
Input Impedance Termination• Feedback network is frequency dependent• Different effect on different harmonics
[ ] [ ] [ ]
)()()(,)(1)()()(
)(
2,2,)(
)2(212
)2()(1)(1)(14
)(3
1
211
3
1
sZsZsZsZgsZgsZgssZsC
gsA
fjsfjssssswhere
VsZsCg
sAsZsCg
sAsZsCVI
sAIIP
eb
emo
mmFje
m
bbaaba
sjem
jem
jeT
Q
+=++++
=
==<<−=∆
⎭⎬⎫
⎩⎨⎧
++∆∆+∆
+−+≈
βτ
ππ
17
AMSC
Input Impedance Termination• The input and output impedances selectively
tuned for second harmonic frequencies• Requires huge passive elements
18
AMSC Feedforward
• Scaled versions of the input signal are fed to two different amplifiers
Pre-scalar(β)
Amplifier(A)
Amplifier(A)
X(t) Y(t)
β
Ymain(t)
Yaux(t)
xA
tytyty
xxAtyxxAty
auxmain
auxmain
.11
)()()(
1*)1.(..)(),1.(.)(
2
322
22
2
⎟⎟⎠
⎞⎜⎜⎝
⎛−=
−=
+=+=
β
ββαβα
19
AMSC Feedforward-1
• Drawbacks– Linearity improvement at the expense of gain– Reduced NF due to additional active
components– Mismatch and errors in signal scaling leads to
reduced improvement• Derivative Superposition (DS) method
addresses the above problems
20
AMSCDerivative Superposition (DS) Method
• DS method also addresses the problem of narrow range with optimum biasing technique.
• gm3 negative in strong inversion and positive in weak inversion
MAWA
MBWB
VGS VOFF
OUT
IN
L
ZS
StrongInversion
WeakInversion
21
AMSC DS-Method
• Wide range of bias values with very small gm3and hence IIP3 improvement obtained
• Drawbacks– Second order harmonics ( ) converted to
voltage at the source– Control parameter Vgs has both fundamental and
second harmonics
abba ωωωω ±±,2,2
LC
ZCjLj
g
gg
WhereLCg
IIP
gssgsm
mm
gsm
)2(22
132
,3
43
1
22
3
221
ωωω
ε
εω
+++−=
=
22
AMSC Modified DS-Method
• Addresses the effect of second order non-linearity feedback
• Magnitude and phase of second order non-linearity contribution to IM3 is tuned to cancel the third order non-linearity contribution to IM3
MB MA
VGS VOFF
OUT
IN
L2
L1
AuxiliaryTransistor
MainTransistor
23
AMSC Modified DS-Method
( )[ ]
( )
A
A
A
AA
ABA
AB
ABAA
gLjsngLLj
ggg
CLCCLCLsnsng
WhereCLCCLgIIP
12
121
1
22
321
223
2122
13
1)()(2
11
1321)()(
,3
4
ωω
ε
εω
+=+
+−+⎥
⎦
⎤⎢⎣
⎡++
+=
++=
24
AMSC Drawbacks
• Weak inversion transistor connected in parallel degrades NF
• Auxiliary transistor loads the input affecting the frequency of operation
• Auxiliary transistor affects both linearity and input match leading to increased design steps
0
222
02
54
4
d
gsng
dnd
gC
fkTi
gfkTi
ωδ
γ
∆=
∆=
tDsatd Ig φ=0
25
AMSC
Proposed Solution
26
AMSC Basic Idea
• An auxiliary circuit is unavoidable to achieve high linearity
• IM3 components in the drain current of the main transistor has the required information of its non-linearity
• Auxiliary circuit is used to tune the magnitude and phase of IM3 components
• Addition of main and auxiliary transistor currents results in negligible IM3 components at output
27
AMSC Basic Idea
(Magnitude and angle tuned)
Im
Reg3A g2A
g3B
28
AMSC Proposed LNA
29
AMSC Theoretical Analysis
• IIP3 derived using the harmonic input method of Volterra series analysis
33213
221211
33
33
221
*),,(*),(*)( xxxbaout
bbb
aaaaaaa
vsssCvssCvsCiii
vgi
vgvgvgi
++=+=
=
++=
LA
ZS
vx
va
vb CB ib
ia
LB
CA
ix ioutvout
30
AMSC Theoretical Analysis
( )
)(1)()(
)1(22)()(
3,
)()(Re613
1
2
22
31
22
3
12
1
BAB
AaA
BB
BBb
a
aa
a
s
sLsLsCsCgsLsn
CLsCLssnsng
gggwhere
gsAsZ
IIP
+++
=
++
+−=
⎭⎬⎫
⎩⎨⎧=
ε
ε
• The effect of second order non-linearity can be seen in the above equation
• The value of g3bcan be tuned to obtain high IIP3 by choosing appropriate values for the inductors LA and LB and the aspect ratios of the transistors.
31
AMSC Theoretical Analysis
• MATLAB plots for different values of LA and LB is plotted
• The result corroborates the idea of IIP3 improvement by cancellation of IM3 components
DesignedPoint
32
AMSC IIP3 Sensitivity
0
5
10
15
20
25
4 4.2 4.4 4.6 4.7 4.8 5 5.2 5.4
Main Transistor Inductor (nH)
IIP3
(dB
m)
0
5
10
15
20
25
0.5 0.75 0.9 1 1.05 1.1 1.25 1.5
Aux Transistor Inductor (nH)
IIP3
(dB
m)
Variation with La Variation with Lb
33
AMSC Effect on Input Match
• If , the input impedance can be simplified to that of a cascode LNA
• The input matching is unaffected by the auxiliary transistor
12 <<BACLs
A
AaA
AGin C
LgsL
sCsLZ 11
+++=
34
AMSC Effect on Input Match
• Effect on input match (S11) with and without auxiliary transistor
202 MHz188 MHz
Without Auxiliary
With Auxiliary
35
AMSC Effect on NF
• The gate noise current of the auxiliary transistor gets added with the drain noise current of main transistor and is attenuated by the gain of LNA
36
AMSC Effect on NF
• 0.3dB degradation in NF observed• Lossy inductor in the auxiliary branch
contributes to increased NF
NF with auxiliary transistor
NF without auxiliary transistor
37
AMSC LNA Design
• Linear LNA was designed and fabricated in TSMC 0.35µm CMOS technology
• The inductors were designed using ASITIC and a Q of 2.5 was obtained
• The LNA was designed to have maximum gain at 900MHz
• The LNA fabricated was a stand alone LNA terminated by the 50Ω port impedance
38
AMSC Component Values
10 nHLD
1.05 nHLB
5 nHLA
30 nHLG
24 µm/0.4 µm, m=36MB
24 µm/0.4 µm, m=16MC
24 µm/0.4 µm, m=16MA
ValueComponent
39
AMSC Chip Photograph
40
AMSC Testing Strategy
• The gain obtained in LNA is less as it sees a 50Ω load impedance
• Gain can be improved by connecting a resistor in series with the port
•LNA Gain= 5050* +
=R
VV
VV
in
out
in
x
41
AMSC Advantages
• Increased gain results in larger signal swings
• LNA subject to large signal swings is an ideal test for linearity
• Linearity of LNA unaffected due to linear resistive element
42
AMSC Experimental Results
• R=0Ω, S11=-15.85 dB, S21=4.4 dB, Gain= 4.4 dB
S21 (Power Gain)S11 (Input Match)
43
AMSC Experimental Results
• R=75 Ω, S11=-11.7 dB, S21=1.5 dB, Gain= 9.5 dB
S21 (Power Gain)S11 (Input Match)
44
AMSC IIP3 Test Setup
45
AMSC IIP3 Measurement
• Pin=-10dBm, Pf= -13.2dBm PIM3= -75.07dBm
• IIP3 = +20.93 dBm
PowerOutputtoneIMTotalP
PowerOutputSignalTotalPPowerInputSignalTotalPwhere
PPPdBmIIP
IM
f
in
IMfin
3
2)(3
3
3
=
==
−+=
• R=75 Ω
46
AMSC IIP3 MeasurementO
utpu
t Pow
er p
er to
ne (d
Bm
)
47
AMSC Experimental Results
• R=100 Ω, S11=-10.7 dB, S21=1.1 dB, Gain= 10.6 dBS21 (Power Gain)S11 (Input Match)
48
AMSC IIP3 MeasurementO
utpu
t Pow
er p
er to
ne (d
Bm
)
49
AMSC Summary of Results
20.511.5-0.5-9.5150
2110.61.1-10.7100
20.99.51.5-11.775
204.44.4-15.850
IIP3 (dBm)LNA Gain (dB)S21 (dB)S11 (dB)R (Ω)
50
AMSC De-embedding Results
• 6dB increment in gain when ‘R’ is changed from 0Ω to 100Ω and hence on-chip load resistance can be computed to be 150Ω
• Gain of LNA with Zext=∞ is 6dB more than gain with R=100Ω• Gain of LNA adding other losses is estimated to be 18.5dB• The NF of the LNA after de-embedding the noise contribution of
termination resistors (R=100Ω and 50Ω port) is calculated to be
1.76dB
51
AMSC Comparison of Results
23.5
8.9
11.7
5.4
24.2
45
21.1
22.5
Pdc
(mW)
54
29
124
117
503
3
19
793
FOM
221.6515.50.90.25µm CMOSMTT ‘05
10.51.814.60.90.25µm CMOSISCAS ‘04
11.71.415.70.880.5µm SiGe BiCMOSESSCC ‘05
15.62.8100.90.35µm CMOSJSSC ‘04
182.82.50.90.35µm CMOSISSCC ‘01
16.1314.92.20.25µm CMOSISSCC ‘03
151.96.530.18µm CMOSISCAS ‘04
211.7618.50.950.35µm CMOSThis Work
IIP3 (dBm)
NF (dB)
Gain (dB)
Freq (GHz)TechnologyWork
52
AMSC
Fig 1 shows the simplified small signal model of LNA. RL is the load impedance of LNA presented by the LC resonant circuit at the output, R is the external resistor connected to improve the gain and 50Ω is the resistance of the port.
Fig 1: Small Signal Model
De-Embedding the NF of LNA
53
AMSC
For numerical analysis a value of RL=150Ω and R=75Ω are used below.
From Table 3 in the paper, the measured gain at the point VLNA shown in Fig 1 is 10.5dB for R=75Ω and NF is 2.95dB. Hence
(1)972.1101 1095.2
250
2==+=
Ω
−
VV
NF inmeasured
54
AMSC Noise Analysis at output:
Fig 2: Noise Analysis
Fig 2 shows the model used for noise analysis. 2LNAi and
2RLi
are the noise currents due to input transistor and the load resistance (RL) respectively. 22RLLNA ii + is reflected to the output port to generate
2_ outLNAv
.
55
AMSC
The resistors R and 50Ω generate an output noise voltage at the node ‘OUT’ given by
( )( )72.0*50*4
5050*
5050*4
505050
505014
2
2
22
22
KT
RRR
RRRR
KT
RRR
RRRR
KTV
LL
L
LL
Ladd
=
⎥⎥
⎦
⎤
⎢⎢
⎣
⎡
+++⎟⎟
⎠
⎞⎜⎜⎝
⎛++
+=
⎥⎥
⎦
⎤
⎢⎢
⎣
⎡⎟⎟⎠
⎞⎜⎜⎝
⎛++
+⎟⎟⎠
⎞⎜⎜⎝
⎛++
+=
(2)
The output noise measured at the node ‘OUT’ is the sum of noise contributed by the LNA and the output resistive network formed by R and 50Ω and is given as follows.
56
AMSC
))2((72.0*50*450
50*
5050*
22
_
22
2_
2
fromKTR
V
VR
VV
outLNA
addoutLNAoutmeasured
+⎟⎠⎞
⎜⎝⎛
+=
+⎟⎠⎞
⎜⎝⎛
+=− (3)
The overall gain of LNA for R=75Ω is given as follows.
34.14.0*35.3)(
4.07550
50
35.35.10
*
_
_
_
_
==
=+
=
==
==
v
outLNA
out
in
outLNA
outLNA
out
in
outLNA
in
out
AGainOverall
VV
dBV
V
VV
VV
VV
GainOverall
57
AMSC
Total input measured noise is given as follows.
))3((72.0*50*42
2
2
22
fromA
KTV
AV
V
vinLNA
v
outmeasuredinmeasured
+=
=
−
−−
Where 2inLNAV − is the total input referred noise contribution of LNA and RL alone.
50*4250 KTVLet n =
. Hence total input referred noise contribution of LNA and the load resistor alone is given by
( )( )5.0
4.09.0
))1((72.0*
110
250
250
2
25010
95.2250
2
n
n
v
nninLNA
V
V
fromA
VVV
=
−=
−⎥⎦⎤
⎢⎣⎡ −=−
De-embedded NF = 1+0.5=1.76dB
58
AMSC Conclusion
• A highly Linear LNA using a non-linearity cancellation technique has been proposed
• Theoretical analysis using Volterra series has been done to corroborate the idea
• The LNA has been designed and fabricated in TSMC 0.35µm technology
• An IIP3 of +21dBm has been experimentally achieved