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ECE 4170 (1)

Simulation vs. Synthesis

© Sudhakar Yalamanchili, Georgia Institute of Technology

ECE 4170 (2)

Execution Models for VHDL Programs

• Two classes of execution models govern the application of VHDL programs

• For Simulation– Discrete event simulation– Understanding is invaluable in debugging programs

• For Synthesis– Hardware inference– The resulting circuit is a function of the building blocks used

for implementation• Primitives: NAND vs. NOR• Cost/performance

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ECE 4170 (3)

Simulation vs. Synthesis

• Simulation and synthesis are complementary processes

entity my_ckt isport (x,y :in bit;z : out bit)end entity my_ckt;

architecture behavioral of my_ckt is-- declarationsbegin-- some code hereend architecture behavioral;

entity my_ckt isport (x,y :in bit;z : out bit)end entity my_ckt;

architecture behavioral of my_ckt is-- declarationsbegin-- some code hereend architecture behavioral;

Synthesis

Simulation

ECE 4170 (4)

Simulation of Digital Systems

• Digital systems are modeled as the generation of events – value transitions – on signals

• Discrete event simulations manage the generation and ordering ofevents

– Correct sequencing of event processing– Correct sequencing of computations caused by events

@5 ns

@10 ns

@15 ns

@5 ns

v1 v2@5ns

v3 v4@10ns

v5 v6@15ns

Head

0

3

ECE 4170 (5)

Discrete Event Simulation: Example

1 0a@5ns

U 1carry@5ns

U 0sum@5ns

0 1sum@10ns

1 0carry@10ns

0 1a@10ns

1 0b@10ns

1 0a@15ns

5ns

10ns

10ns

Initial state: a = b = 1, sum = carry = UEvent List HeadSimulation Time

0ns U 1carry@5ns

U 0sum@5ns New event generated

from inputUpdate time

Update signal values, execute, generate new events, update time

Update signal values, execute, generate new events

ba sum

carry 10 15 20 25 30 35 40

a

b

sum

carry

5Time (ns)

Event

ECE 4170 (6)

Discrete Event Simulation

• Management of simulation time: ordering of events

• Two step model of the progression of time– Evaluate all affected components at the current time: events on

input signals– Schedule future events and move to the next time step: the

next time at which events take place

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ECE 4170 (7)

Simulation Modeling

• VHDL programs describe the generation of events in digital systems• Discrete event simulator manages event ordering and progression of time• Now we can quantitatively understand accuracy vs. time trade-offs

– Greater detail more events greater accuracy– Less detail smaller number of events faster simulation speed

ba sum

carry

VHDL Model

compiler

Discrete Event Simulator from Vendor

ECE 4170 (8)

Synthesis and Hardware Inference

• Both processes can produce very different results!

Synthesis engine

HDLDesign Specification

Author HDL

Author Hardware Design

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ECE 4170 (9)

Inferring Combinational Logic

---- pseudo code for a single bit arithmetic/ logic unit--s1 <= in1 and in2;s2 <= in1 or in2;s3 <= in1 xor in2; -- perform the sum operationc_out <= (in1 and c_in) or (in1 and in2)

or (in2 and c_in);out <= s1 when sel = “00” else

s2 when sel = “01” elses3 when sel = “10” else‘0’;

• Each statement implies a logic component

ECE 4170 (10)

Inferring Sequential Logic

• Inference of sequential components is more subtle– All possible execution paths through the code must be accounted

for• Results are very sensitive to the manner in which code is written• Inferences of latches vs. flip flops

---- a simple conditional code block --

if (sel = ‘0’) thenz <= in1 nor in2;

end if;

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ECE 4170 (11)

Optimization

ABC

B

C

D

B

ABC

B

C

B

C

A

C

B

D

B

ABC + BC + BD

• Logic synthesis can produce several equivalent solutions

ECE 4170 (12)

Field Programmable Gate Arrays: Principles

• The chip is tiled with Configurable Logic Blocks (CLBs)– each block can “implement” a few gates and flip flops

• An interconnect switching matrix is interleaved with this array of CLBs

• Usage: partition, place, and route a design

CLB CLB CLB

CLB CLB CLB

CLB CLB CLB

Configurable Logic Blocks

Interconnect

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ECE 4170 (13)

Inside a Xilinx Configurable Logic BlockC1• • • C4

G4

G3

G2

G1

LogicFunctionof G1–G4

G´

F4

F3

F2

F1

LogicFunctionof F1–F4

F´

LogicFunction of F,́

G,́ and H1H´

4

H1

K(CLOCK)

DIN/H2 SR/H0 EC

S/RControl

1

Bypass

YQDINF´G´H´

G´

H´

DINF´G´H´

H´

F´

1

S/RControl

SD

RD

D

EC

Q

SD

RD

D

EC

Q

Y

XQ

X

Multiplexer Controlled byConfiguration Program

ECE 4170 (14)

Inside a Xilinx IO Block

T

Out

Output Clock

I1

I2

Clock Enable

Input Clock

Slew RateControl

PassivePull-Up/

Pull-Dwon

Output MUX

Flip-Flop

D Q

CE

Flip-Flop/Latch

DQ

CEFast

CaptureLatch

Latch

G

DQ

Delay Delay

InputBuffer

OutputBuffer

0

1

Pad

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ECE 4170 (15)

Implementing Digital Circuits in a CLB

• Boolean functions are implemented as look-up tables

• Combinations of lookup tables implement multivariable functions

• Implementation of behavior

• Sequential circuits use CLB latches/flip flops

C

D

A

B

Out

CD

AB

Out

Look-up Table (16x1 SRAM)

ECE 4170 (16)

Wiring Resources

• Optimize signal delay• “Chip length” signals can be configured as buses• Global nets for low skew clocks and reset signals

12

8

4

3

2

3

12 4 4 6 4 8 4 2

Quad Long Global Long Double Single Global Carry DirectClock Clock Chain Connect

Quad

Single

Double

Long

DirectConnect

Long

CLB

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ECE 4170 (17)

Specialized Resources

• Carry chains between columns of CLBs• Configuration of CLB RAM as

– Memories rather than lookup tables– Shift registers (Xilinx Virtex 5)

• Core generators– Optimized libraries of components– Vendor supplied

• Configuration bit stream for configuring a design– What about editing the bit stream directly!

ECE 4170 (18)

Chip Configuration: Xilinx

• Configuration bits for CLBs– bits for loading the LUTs– bits for configuring the flip flops– bits for setting multiplexors

• Configuration bits for the switch matrix– Connecting horizontal and vertical lines– Tri-state devices within the CLBs

• Configuration bits for the IOBs– IO clocks– storage vs. direct “access” to the pin

• Equivalent concepts for all vendors

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ECE 4170 (19)

Heterogeneous FPGAs: The Xilinx Virtex 5

• Basic building block remains the same• Substrate augmented with “hard cores”

ECE 4170 (20)

The Basic Virtex 5 Slice

Look-up Tables (LUTs)Flip Flops

Carry Chains

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ECE 4170 (21)

Customized Virtex 5 Slice

Can be configured as Block RAM or

Shift register

ECE 4170 (22)

A DSP Slice

• Product families are customized with differing ratios of slice types to address different market segments

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ECE 4170 (23)

A Simplified Design Flow

HDL State Machine SchematicEditor Editor Capture

Model Development

Synthesis

Place and Route

Programming

Behavioral Simulation

Functional Simulation

Verification

Device Programming

CoreGeneration

Utilitites

ECE 4170 (24)

Summary

• VHDL is used to describe digital systems and hence has language constructs for key attributes– Events, propagation delays, and concurrency– Timing, and waveforms– Signal values and use of multiple drivers for a signal

• VHDL has an underlying discrete event simulation model– Model the generation of events on signals– Built in mechanisms for managing events and the

progression of time– Designer simply focuses on writing accurate descriptions