hmc833lp6ge · 2019-06-05 · 25 mhz to 6000 mhz. the integrated phase detector (pd) and...

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HMC833LP6GEv03.714

FRACTIONAL-N PLL WITH INTEGRATED VCO25 - 6000 MHz

For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or [email protected]

Functional Diagram

Features• RFBandwidth:25-6000MHz

• MaximumPhaseDetectorRate100MHz

• UltraLowPhaseNoise-110dBc/HzinBandTyp.

• FigureofMerit(FOM)-227dBc/Hz

• <180fsRMSJitter

• 24-bitStepSize,Resolution3Hztyp

• ExactFrequencyMode

• BuiltinDigitalSelfTest

• 40Lead6x6mmSMTPackage:36mm2

Typical Applications

• CellularInfrastructure

• MicrowaveRadio

• WiMax,WiFi

• CommunicationsTestEquipment

• CATVEquipment

• DDSReplacement

• Military

• TunableReferenceSourceforSpurious-FreePerformance

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 781-329-4700 • Order online at www.analog.com Application Support: Phone: 1-800-ANALOG-D

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General DescriptionTheHMC833LP6GEisalownoise,wideband,Fractional-NPhase-Locked-Loop(PLL)thatfeaturesanintegratedVoltageControlledOscillator(VCO)withafundamentalfrequencyof1500MHz-3000MHz,andanintegratedVCOOutputDivider(divideby1/2/4/6.../60/62)anddoubler,thattogetherallowtheHMC833LP6GEtogeneratefrequenciesfrom25MHzto6000MHz.TheintegratedPhaseDetector(PD)anddelta-sigmamodulator,capableofoperatingatupto100MHz,permitwiderloop-bandwidthswithexcellentspectralperformance.

TheHMC833LP6GEfeaturesindustryleadingphasenoiseandspuriousperformance,acrossallfrequencies,thatenable it tominimizeblockereffects,andimprovereceiversensitivityandtransmitterspectralpurity.Thesuperiornoisefloor(<-170dBc/Hz)makestheHMC833LP6GEanidealsourceforavarietyofapplications-suchas;LOforRFmixers,aclocksourceforhigh-frequencydata-converters,oratunablereferencesourceforultra-lowspuriousapplications.

AdditionalfeaturesoftheHMC833LP6GEincludeRFoutputpowercontrolfrom0to9dB(3dBsteps),outputMutefunction,andadelta-sigmamodulatorExactFrequencyModewhichenablesuserstogenerateoutputfrequencieswith0Hzfrequencyerror.

Parameter Condition Min. Typ. Max. Units

RF Output Characteristics

OutputFrequency 25 6000 MHz

VCOFrequencyatPLLInput 1500 3000 MHz

RFOutputFrequencyatfVCO 1500 3000 MHz

Output Power

RFOutputPoweratffundamental=2000MHz

AcrossAllFrequenciesseeFigure9BroadbandMatchedInternally

[1]1.5 3 4.5 dBm

OutputPowerControlRange 3 9 dB

OutputPowerControlStep 0.75 3 dB

RFOutputPoweratfdoubler=3000MHz


[1]-3.5 -2.5 -1 dBm

RFOutputPoweratfdoubler=6000MHz


[1]-11 -7 -5 dBm

Harmonics for Fundamental Mode

foModeat2GHz 2nd/3rd/4th -20/-29/-45 dBc

fo/2Modeat2GHz/2=1GHz 2nd/3rd/4th -23/-15/-35 dBc

fo/30Modeat3GHz/30=100MHz 2nd/3rd/4th -25/-10/-33 dBc

fo/62Modeat1550MHz/62=25MHz 2nd/3rd/4th -17/-8/-21 dBc

Harmonics in Doubler Mode

2foModeat4GHz ½/3rd/4th/5th -7/-23/-15/-40 -4/-15/-7/-28 dBc

VCO Output Divider

VCORFDividerRange 1,2,4,6,8,...,62 1 62

Electrical SpecificationsVPPCP, VDDLS, VCC1, VCC2 = 5 V; RVDD, AVDD, DVDD3V, VCCPD, VCCHF, VCCPS = 3.3 V Min and Max Specified across Temp -40 °C to 85 °C

[1]Measuredsingle-ended.Additional3dBpossiblewithdifferentialoutputs.

[2]Measuredwith100Ωexternaltermination.See“ReferenceInputStage”sectionformoredetails.



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PLL RF Divider Characteristics

19-BitN-DividerRange(Integer) Max=219-1 16 524,287

19-BitN-DividerRange(Fractional)Fractionalnominaldivideratiovaries(-3/+4)dynamically

max20 524,283

REF Input Characteristics

MaxRefInputFrequency 350 MHz

RefInputVoltage ACCoupled[2] 1 2 3.3 Vp-p

RefInputCapacitance 5 pF

14-BitR-DividerRange 1 16,383

Phase Detector (PD) [3]

PDFrequencyFractionalModeB [4] DC 100 MHz

PDFrequencyFractionalModeA(andRegis-ter6[17:16]=11)

DC 80 MHz

PDFrequencyIntegerMode DC 125 MHz

Charge Pump

OutputCurrent 0.02 2.54 mA

ChargePumpGainStepSize 20 µA

PD/ChargePumpSSBPhaseNoise 50MHzRef,InputReferred

1kHz -143 dBc/Hz

10kHz Add1dBforFractional -150 dBc/Hz

100kHz Add3dBforFractional -153 dBc/Hz

Logic Inputs

Vsw 40 50 60 %DVDD

Logic Outputs

VOHOutputHighVoltage DVDD V

VOLOutputLowVoltage 0 V

OutputImpedance 100 200 Ω

MaximumLoadCurrent 1.5 mA

Power Supply Voltages

3.3VSuppliesAVDD,VCCHF,VCCPS,VCCPD,RVDD,DVDD

3.0 3.3 3.5 V

5VSupplies VPPCP,VDDLS,VCC1,VCC2 4.8 5 5.2 V

Power Supply Currents

+5VAnalogChargePump VPPCP,VDDCP 8 mA

+5VVCOCoreandVCOBufferfo/1ModeVCC2 105 mA

fo/NModeVCC2 80 mA

+5VVCODividerandRF/PLLBufferfo/1ModeVCC1 25 mA

fo/NModeVCC1 80 100 mA

Electrical Specifications (Continued)

[3]Slewrateofgreaterorequalto0.5ns/Visrecommended,see“ReferenceInputStage”sectionformoredetails.Frequencyisguaranteedacrossprocessvoltageandtemperaturefrom-40°Cto85°C.[4]ThismaximumphasedetectorfrequencycanonlybeachievediftheminimumNvalueisrespected.eg.InthecaseoffractionalBmode,themaximumPFDrate=fvco/20or100MHz,whicheverisless.



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+3.3VAVDD,VCCHF,VCCPS,VCCPD,RVDD,DVDD3V

52 mA

PowerDown-CrystalOffReg01h=0,

CrystalNotClocked10 µA

PowerDown-CrystalOn,100MHzReg01h=0,

CrystalClocked100MHz5 mA

Power on Reset

TypicalResetVoltageonDVDD 700 mV

MinDVDDVoltageforNoReset 1.5 V

PoweronResetDelay 250 µs

VCO Open Loop Phase Noise at fo @ 2 GHz

10kHzOffset -86 dBc/Hz


1MHzOffset -141 dBc/Hz



VCO Open Loop Phase Noise at fo @ 2 GHz/2 = 1 GHz






VCO Open Loop Phase Noise at fo @3 GHz/30 = 100 MHz






VCO Open Loop Phase Noise at 2fo @ 4 GHz






VCO Open Loop Phase Noise at 2fo @ 6 GHz








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Figure of Merit

FloorIntegerMode Normalizedto1Hz -230 dBc/Hz

FloorFractionalMode Normalizedto1Hz -227 dBc/Hz

Flicker(BothModes) Normalizedto1Hz -268 dBc/Hz

VCO Characteristics

VCOTuningSensitivityat2800MHz Measuredat2.5V 13.3 MHz/V




VCOSupplyPushing Measuredat2.5V 2 MHz/V




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Figure 1. Typical Closed Loop Integer Phase Noise[“LoopFilterConfigurationTable”]

Figure 2. Typical Closed Loop Fractional Phase Noise[“LoopFilterConfigurationTable”]

Figure 3. Free Running Phase NoiseFigure 4. Free Running VCO Phase Noise vs. Temperature

Figure 5. Typical VCO Sensitivity at Fo

-220

-200

-180

-160

-140

-120

-100

-80

1 10 100 1000 10000 100000

fout 3800 MHz,Lopp BW 74KHz,rms jitter 108fsecfout 3800MHz,Loop Filter 90KHz,rms jitter 87fsecfout 5600MHz,Loop BW 74KHz,rms jitter 188fsec

fout 1600MHz,Loop BW 74KHz,rms jitter 127fsecfout 1600MHz,Loop BW 90KHz, rms jitter 97fsec

fout 5600MHz,Loop BW 90KHz,rms jitter 118fsec

OFFSET(KHz)

PH

AS

E N

OIS

E(d

Bc/

Hz)

-220

-200

-180

-160

-140

-120

-100

-80

1 10 100 1000 10000 100000

fout 3805 MHz,Loop BW 74KHz,rms jitter 123fsecfout 3805MHz,Loop BW 90KHz,rms jitter 104fsecfout 5605MHz,Loop BW 74KHz,rms jitter 202fsecfout 5605MHz,Loop BW 90KHz,rms jitter 128fsecfout 1605MHz, Loop BW 74KHz,rms jitter 130fsecfout 1605MHz, Loop BW 90KHz, rms jitter 123fsec

OFFSET (kHz)P

HA

SE

NO

ISE

(dB

c)

-180

-160

-140

-120

-100

-80

-60

-40

103

104

105

106

107

108

5536 MHz4732 MHz3885 MHz3058 MHz

PH

AS

E N

OIS

E (

dB

c/H

z)

OFFSET (Hz)

-180

-170

-160

-150

-140

-130

-120

-110

-100

10 100 1000 10000

27C-40C85C

PH

AS

E N

OIS

E (d

Bc/

Hz)

FREQUENCY (MHz)

100 MHz Offset

1 MHz Offset

100 kHz Offset

0

1

2

3

4

5

TU

NE

VO

LT

AG

E A

FT

ER

CA

LIB

RA

TIO

N (

V)

VCO FREQUENCY(MHz)

fmin fmax

1500 30000

10

20

30

40

50

60

0 1 2 3 4 5

2817 MHz at 2.5V, Tuning Cap 152418 MHz at 2.5V, Tuning Cap 151996 MHz at 2.5V, Tuning Cap 151575 MHz at 2.5V, Tuning Cap 15

TUNING VOLTAGE (V)

kV

CO

(M

Hz/V

)

Typical Performance Characteristics

Figure 6. Typical Tuning Voltage After Calibration at Fo



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Figure 7. Integrated RMS Jitter[1]

[1]RMSJitterdataismeasuredinfractionalmodewith100kHzLoopbandwidthusing50MHzreferencefrequencyfrom1kHzto20MHzintegrationbandwidth.

[2]TheoutputpowerfromFrequency25MHzto3000MHzisusingfundamentalConfigurationwithGainSetting01,outputpowerfromFrequency3000MHzto6000MHzisusingdoublerConfigurationwithGainSetting11

[3]Measuredfroma50Ωsourcewitha100Ωexternalresistortermination.See“ReferenceInputStage”sectionformoredetails.FullFOMperformanceuptomaximum3.3Vppinputvoltage.

Figure 8. Figure of Merit

Figure 9. Typical Output Power vs. Temperature [2]

Figure 10. Output Power vs Gain Control Setting (VCO_Reg02h[8]=1. See VCO_Reg02h)

Figure 11. Reference Input Sensitivity, Square Wave, 50 Ω[3]

Figure 12. Reference Input Sensitivity Sinusoidal Wave, 50 Ω[3]

50

100

150

200

250

300

10 100 1000 10000

-40C27C85C

JIT

TE

R (

fs)

OUTPUT FREQUENCY (MHz)

-240

-230

-220

-210

-200

102

103

104

105

106

NO

RM

AL

IZE

D P

HA

SE

NO

ISE

(d

Bc/H

z)

FREQUENCY OFFSET (Hz)

FOM FloorFOM 1/f Noise

Typ FOM vs Offset

-12

-10

-8

-6

-4

-2

0

2

0 1000 2000 3000 4000 5000 6000

27 C-40 C85 C

OU

TP

UT

PO

WE

R (

dB

m)


-234

-232

-230

-228

-226

-224

-222

-220

-15 -12 -9 -6 -3 0 3

14 MHz Square Wave25 MHz Square Wave50 MHz Square Wave100 MHz Square Wave

FO

M

REFERENCE POWER (dBm)

-235

-230

-225

-220

-215

-210

-205

-200

-20 -15 -10 -5 0 5

14 MHz sin25 MHz sin50 MHz sin100 MHz sin

REFERENCE POWER (dBm)

FO

M (

dBc/

Hz)

-10

-5

0

5

10

0 1000 2000 3000 4000 5000 6000

Gain Setting 11Gain Setting 10Gain Setting 01Gain Setting 00

OU

TPU

T P

OW

ER

(dB

m)




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Figure 13. Integer Boundary Spur at 5900.8 MHz[4]

Figure 14. Integer Boundary Spur at 3900.4 MHz [5]

-180

-160

-140

-120

-100

-80

-60

-40

-20

0

1 10 100 1000 10000 100000

PH

AS

E N

OIS

E (

dB

c/H

z)

OFFSET (kHz)

[4]FractionalModeB,50MHzPDfrequency,74kHzLoopFilterBW[5]FractionalModeinModeB,IntegerBoundaryat3800MHz[7]ExactFrequencyMode,REFin=100MHz,PD=50MHz,OutputDivider1Selected,LoopFilterbandwidth=100kHz,ChannelSpacing=100kHz[8]ExactFrequencyMode,ChannelSpacing=100kHz,FractionalModeBRFout=2591MHz,REFin=100MHz,PDfrequency=50MHz,Output

Divider1selected,LoopFilterbandwidth=120kHz,[9]FractionalModeBRFout=2591MHz,REFin=100MHz,PDfrequency=50MHz,OutputDivider1selected,LoopFilterbandwidth=120kHz.

-180

-160

-140

-120

-100

-80

-60

-40

-20

0

1 10 100 1000 10000 100000

PH

AS

E N

OIS

E (

dB

c/H

z)

OFFSET (kHz)

-180

-160

-140

-120

-100

-80

-60

-40

-20

0

1 10 100 1000 10000 100000

PH

AS

E N

OIS

E (

dB

c/H

z)

OFFSET (kHz)

Figure 15. Fractional-N Exact Frequency Mode ON Performance at 2113.5 MHz[7]

Figure 16. Fractional-N Exact Frequency Mode ON Performance at 2591 MHz[8]

Figure 17. Fractional-N Exact Frequency Mode OFF Performance at 2591 MHz[9]

-180

-160

-140

-120

-100

-80

-60

1000 10000 100000 1000000 10000000 100000000

PH

AS

E N

OIS

E (

dB

c/H

z)

OFFSET (kHz)

-180

-160

-140

-120

-100

-80

-60

1 10 100 1000 10000 100000

PH

AS

E N

OIS

E (d

Bc/

Hz)

OFFSET (kHz)

-180

-160

-140

-120

-100

-80

-60

-40

-20

0

0.1 1 10 100 1000 10000 100000

PH

AS

E N

OIS

E (

dB

c/H

z)

OFFSET (kHz)

Figure 18. Worst Spur, Fixed 50 MHz Reference, Output Freq. = 2000.1 MHz[10]



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LoopFilterBW(kHz)

C1(pF)

C2(nF)

C3(pF)

C4(pF)

R2(kΩ)

R3(kΩ)

R4(kΩ)

LoopFilterDesign

74 150 27 220 220 0.82 1 1

90 270 3.9 56 56 1.2 1 1

200 56 1.8 N/A N/A 2.2 0 0

Loop Filter Configuration Table

Figure 19. RF Output Return Loss Figure 20. Worst Spur, Tunable Reference, Output Frequency = 2000.1 MHz [10]

[10]CapabilityofHMC830LP6GEtogeneratelowfrequencies(aslowas25MHz),enablestheHMC830LP6GEtobeusedasatunablereference

sourceintotheHMC833LP6GE,whichmaximizesspurperformanceoftheHMC833LP6GE.Pleasesee“HMC833LP6GEApplication

Information”formoreinformation.[11]Thegraphisgeneratedbyobserving,andplotting,themagnitudeofonlytheworstspur(largestmagnitude),atanyoffset,ateachoutput

frequency,whileusingafixed50MHzreferenceandatunablereferencetunedto47.5MHz.See“HMC833LP6GEApplicationInformation”formoredetails.

[12]PhasenoiseperformanceoftheHMC833LP6GEwhenusedasatunablereferencesource.HMC833LP6GEisoperatingat6GHz/30,6GHz/54forthe100MHz,55.55MHzcurvesrespectivelyLoopFilter56pF//(2.2kohm+1.8nF)IntegerMode100MHzWenzeloscillatorwithRdiv=250MHzcomparisonfrequency.

Figure 21. Low Frequency Performance [11]

-170

-160

-150

-140

-130

-120

0.1 1 10 100 1000 10000 100000

Carrier Frequency = 25 MHzCarrier Frequency = 55.55 MHzCarrier Frequency = 100 MHz

PH

AS

E N

OIS

E (

dB

c/H

z)

OFFSET (kHz)

Figure 22. Low Frequency Performance [12]

-120

-110

-100

-90

-80

-70

-60

-50

2GHz +1kHz 2GHz +10kHz 2GHz +100kHz 2GHz +1000kHz 2GHz +10000kHz

Fixed 50 MHz ReferenceTunable Reference

WO

RS

T S

PU

R (

dB

c)

OUTPUT FREQUENCY

-180

-160

-140

-120

-100

-80

-60

-40

-20

0

0.1 1 10 100 1000 10000 100000

PH

AS

E N

OIS

E (

dB

c/H

z)

OFFSET (kHz)

-35

-30

-25

-20

-15

-10

-5

0

25 100 1000 10000

RE

TU

RN

LO

SS

(dB

)

FREQUENCY (MHz)



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Pin DescriptionsPinNumber Function Description

1 AVDD DCPowerSupplyforanalogcircuitry.

2,5,6,8,9,11-14,18-22,24,26,29,34,37,38

N/CThepinsarenotconnectedinternally;however,alldatashownhereinwasmeasuredwiththesepinsconnectedtoRF/DCgroundexternally.

3 VPPCP PowerSupplyforchargepumpanalogsection

4 CP ChargePumpOutput

7 VDDLS PowerSupplyforthechargepumpdigitalsection

10 RVDD ReferenceSupply

15 XREFP ReferenceOscillatorInput

16 DVDD3V DCPowerSupplyforDigital(CMOS)Circuitry

17 CEN ChipEnable.Connecttologichighfornormaloperation.

23 VTUNE VCOVaractor.TuningPortInput.

25 VCC2 VCOAnalogSupply2

27 VCC1 VCOAnalogSupply1

28 RF_OUT RFOutput

30 SEN PLLSerialPortEnable(CMOS)LogicInput

31 SDI PLLSerialPortData(CMOS)LogicInput

32 SCK PLLSerialPortClock(CMOS)LogicInput

33 LD_SDO LockDetect,orSerialData,orGeneralPurpose(CMOS)LogicOutput(GPO)

35 VCCHF DCPowerSupplyforAnalogCircuitry

36 VCCPS DCPowerSupplyforAnalogPrescaler

39 VCCPD DCPowerSupplyforPhaseDetector

40 BIAS

Externalbypassdecouplingforprecisionbiascircuits.Note:1.920V±20mVreferencevoltage(BIAS)isgeneratedinternallyandcannot

driveanexternalload.Mustbemeasuredwith10GΩmetersuchasAgilent34410A,normal10MΩDVMwillreaderroneously.



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Outline Drawing

NOTES:

1.PACKAGEBODYMATERIAL:LOWSTRESSINJECTIONMOLDEDPLASTICSILICAANDSILICONIMPREGNATED.

2.LEADANDGROUNDPADDLEMATERIAL:COPPERALLOY.

3.LEADANDGROUNDPADDLEPLATING:100%MATTETIN.

4.DIMENSIONSAREININCHES[MILLIMETERS].

5.LEADSPACINGTOLERANCEISNON-CUMULATIVE.

6.PADBURRLENGTHSHALLBE0.15mmMAX.PADBURRHEIGHTSHALLBE0.25mmMAX.

7.PACKAGEWARPSHALLNOTEXCEED0.05mm.

8.ALLGROUNDLEADSANDGROUNDPADDLEMUSTBESOLDEREDTOPCBRFGROUND.

9.REFERTOHITTITEAPPLICATIONNOTEFORSUGGESTEDPCBLANDPATTERN.

Absolute Maximum RatingsAVDD,RVDD,DVDD3V,VCCPD,VCCHF,VCCPS

-0.3Vto+3.6V

VPPCP,VDDLS,VCC1,VCC2 -0.3Vto+5.5V

OperatingTemperature -40°Cto+85°C

StorageTemperature -65°Cto150°C

MaximumJunctionTemperature 150°C

ThermalResistance(RTH)(junctiontogroundpaddle)

9°C/W

ReflowSoldering

PeakTemperature 260°C

TimeatPeakTemperature 40sec

ESDSensitivity(HBM) Class1B

StressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thisisastressratingonly;functionaloperationofthedeviceat theseoranyotherconditionsabove thoseindicatedintheoperationalsectionofthisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditions for extended periods may affect devicereliability.

Parameter Condition Min. Typ. Max. Units.

Temperature

JunctionTemperature 125 °C

AmbientTemperature -40 85 °C

Supply Voltage

AVDD,RVDD,DVDD3V,VCCPD,VCCHF,VCCPS 3.0 3.3 3.5 V

VPPCP 4.8 5.0 5.2 V

Recommended Operating Conditions



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PartNumber PackageBodyMaterial LeadFinish MSLRating PackageMarking[1]

HMC833LP6GE RoHS-compliantLowStressInjectionMoldedPlastic 100%matteSn MSL1H833XXXX

[1]4-DigitlotnumberXXXX

Package Information

Evaluation PCB Schematic

Thecircuitboardused in theapplicationshoulduseRFcircuitdesign techniques.Signal linesshouldhave50Ohmimpedancewhilethepackagegroundleadsandexposedpaddleshouldbeconnecteddirectlytothegroundplanesimilar to thatshown.Asufficientnumberofviaholesshouldbeusedtoconnect the topandbottomgroundplanes.TheevaluationcircuitboardshownisavailablefromHittiteuponrequest.

To view this EvaluationPCBSchematic please visit www.hittite.com and choose HMC833LP6GE from the “Search by Part Number” pull down menu to view the product splash page.

Evaluation PCB

Item Contents PartNumber

EvaluationKit

HMC833LP6GEEvaluationPCBUSBInterfaceBoard6’USBAMaletoUSBBFemaleCableCDROM(ContainsUserManual,EvaluationPCBSchematic,EvaluationSoftware,HittitePLLDesignSoftware)

EKIT01-HMC833LP6GE

Evaluation Order Information



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HMC833LP6GE Application InformationLargebandwidth(25MHzto6000MHz),industryleadingphasenoiseandspuriousperformance,excellentnoisefloor(<-170dBc/Hz),coupledwithahighlevelofintegrationmaketheHMC833LP6GEidealforavarietyofapplications;asanRForIFstageLO,aclocksourceforhigh-frequencydata-converters,oratunablereferencesourceforextremelylowspuriousapplications(<-100dBc/Hzspurs).

Figure 23. HMC833LP6GE in a typical transmit chain

Figure 24. HMC833LP6GE in a typical receive chain

Figure 25. HMC830LP6GE used as a tunable reference for HMC833LP6GE

UsingtheHMC833LP6GEwithatunablereferenceasshowninFigure25,itispossibletodrasticallyimprovespuriousemissionsperformanceacrossallfrequencies.ExampleshowninFigure20graphshowsthatitispossibletohavespuriousemissions<-100dBc/Hzacrossallfrequencies.Formoreinformationaboutspuriousemissions,howtheyarerelatedtothereferencefrequency,andhowtotunethereferencefrequencyforoptimalspuriousperformancepleaseseethe“FractionalOperationandSpurious”sectionofthisdatasheet.Notethatatverylowoutputfrequencies<100MHz,harmonicsincreaseduetosmallinternalACcoupling.Applicationswhicharesensitivetoharmonicsmayrequireexternallowpassfiltering.



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Output gain setting for Optimal Power FlatnessTheoutputoftheHMC833LP6GEismatchedto50Ωacrossalloutputfrequenciesfrom25MHzto6000MHz.Asa result of thewideband50Ωmatch, theoutput power of theHMC833LP6GEdecreaseswith increasingoutputfrequency,asshowninFigure9.Ifrequired,itispossibletoadjusttheoutputstagegainsettingoftheHMC833LP6GE(“VCO_Reg02hBiases”[7:6])atvariousoperatingfrequenciesinordertoachieveamoreconstantoutputpowerlevelacrossthefrequencyoperatingrangeoftheHMC833LP6GE.AnexampleisshowninFigure26.

Figure 26.

-20

-15

-10

-5

0

5

0 1000 2000 3000 4000 5000 6000

OU

TP

UT

PO

WE

R (

dB

m)


Gain = 0 dB

Gain = 9 dBGain = 6 dB

Divider outputstage gain = 3 dB(VCO_Reg02h[8] = 1)

Reducing the output power variation of HMC833LP6GE across frequency by adjusting output stage gain

control. IfahigheroutputpowerthanthatshowninFigure26isrequired,itispossibletofollowtheHMC833LP6GEoutputstagewithasimpleamplifiersuchasHMC311SC70E inorder toachieveaconstantandhighoutputpower levelacrosstheentireoperatingrangeoftheHMC833LP6GE.



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1.0 Theory of OperationHMC833LP6GEistargetedforultralowphasenoiseapplicationsandhasbeendesignedwithverylownoisereferencepath,phasedetectorandchargepump.

TheHMC833LP6GEconsistsofthefollowingfunctionalblocks:

1.ReferencePathInputBuffersand’R’Divider2.VCOPathInputBufferandMulti-Modulus’N’Divider3.Δ∑FractionalModulator4.PhaseDetector5.ChargePump6.SerialPortwithReadWriteCapability7.GeneralPurposeOutput(GPO)Port8.PowerOnResetCircuit9.VCOSubsystem10.Built-InSelfTestFeatures

1.1 VCO SubsystemTheHMC833LP6GEcontainsaVCOsubsystemthatcanbeconfiguredtooperatein:• Fundamentalfrequency(fo)mode(1500MHzto3000MHz).• DividebyN(fo/N),whereN=1,2,4,6,8...58,60,62mode(25MHzto1500MHz).• Doubler(2fo)mode(3000MHzto6000MHz).AllmodesareVCOregisterprogrammableasshowninFigure27.OneloopfilterdesigncanbeusedfortheentirefrequencyofoperationoftheHMC833LP6GE.

Figure 27. PLL and VCO Subsystems



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1.2 VCO Calibration

1.2.1 VCO Auto-Calibration (AutoCal)HMC833LP6GEusesasteptunedtypeVCO.AsimplifiedsteptunedVCOisshowninFigure28.AsteptunedVCOisaVCOwithadigitallyselectablecapacitorbankallowingthenominalcenterfrequencyoftheVCOtobeadjustedor‘stepped’byswitchingin/outVCOtankcapacitors.AmoredetailedviewofatypicalVCOsubsystemconfigurationisshowninFigure29.AsteptunedVCOallowstheusertocentertheVCOontherequiredoutputfrequencywhilekeepingthevaractortuningvoltageoptimizednearthemid-voltagetuningpointoftheHMC833LP6GE’schargepump.ThisenablesthePLLchargepumptotunetheVCOoverthefullrangeofoperationwithbothalowtuningvoltageandalowtuningsensitivity(kvco).

The VCO switches are normally controlled automatically by the HMC833LP6GE using theAuto-Calibration feature. TheAuto-Calibration feature is implemented in the internal statemachine. ItmanagestheselectionoftheVCOsub-band(capacitorselection)whenanewfrequencyisprogrammed.TheVCOswitchesmayalsobecontrolleddirectlyvia registerReg05h for testingor forotherspecialpurposeoperation.OthercontrolbitsspecifictotheVCOarealsosentviaReg05h.

Figure 28. Simplified Step Tuned VCO

Figure 29. HMC833LP6GE PLL and VCO SubsystemsTouseastep tunedVCOinaclosed loop, theVCOmustbecalibratedsuch that theHMC833LP6GEknowswhichswitchpositionontheVCOisoptimumforthedesiredoutputfrequency.TheHMC833LP6GEsupportsAuto-Calibration (AutoCal)of thestep tunedVCO.TheAutoCalfixes theVCOtuningvoltageat theoptimummid-pointof thechargepumpoutput, thenmeasures the free runningVCO frequencywhilesearching for thesettingwhich results in the free runningoutput frequency that isclosest to thedesired phase locked frequency. This procedure results in a phase locked oscillator that locks over



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averynarrowvoltage rangeon thevaractor.A typical tuningcurve forastep tunedVCO isshown inFigure30.Notehowthetuningvoltagestaysinanarrowrangeoverawiderangeofoutputfrequencies.

0

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920 960 1000 1040 1080 1120 1160

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50MHz PFD, 500kHz Tuning Steps, +25C256 Count Calibration ,195kHz Resolution31usec Total Cal Time

01531

Figure 30. A Typical 5-Bit 32 Switch VCO Tuning Voltage After CalibrationThecalibrationisnormallyrunautomaticallyonceforeverychangeoffrequency.ThisensuresoptimumselectionofVCOswitchsettingsvs.timeandtemperature.TheuserdoesnotnormallyhavetobeconcernedaboutwhichswitchsettingisusedforagivenfrequencyasthisishandledbytheAutoCalroutine.TheaccuracyrequiredinthecalibrationaffectstheamountoftimerequiredtotunetheVCO.ThecalibrationroutinesearchesforthebeststepsettingthatlockstheVCOatthecurrentprogrammedfrequency,andensuresthattheVCOwillstaylockedandperformwelloverit’sfulltemperaturerangewithoutadditionalcalibration,regardlessofthetemperaturethattheVCOwascalibratedat.

Auto-CalibrationcanalsobedisabledallowingmanualVCOtuning.Refertosection1.2.2foradescriptionofmanualtuning

1.2.1.1 AutoCal Use of Reg05hAutoCal transfers switch control data to the VCO subsystem via Reg 05h. The address of the VCOsubsysteminReg05hisnotalteredbytheAutoCalroutine.TheaddressandIDoftheVCOsubsysteminReg05hmustbesettothecorrectvaluebeforeAutoCalisexecuted.Formoreinformationseesection1.19.

1.2.1.2 Auto-reLock on Lock Detect FailureIt is possible by settingReg 07h[13] to have the VCO subsystem automatically re-run the calibrationroutineandre-lockitselfifLockDetectindicatesanunlockedconditionforanyreason.Withthisoptionthesystemwillattempttore-Lockonlyonce.Auto-reLockisrecommended.

1.2.2 Manual VCO Calibration for Fast Frequency HoppingIfitisdesirabletoswitchfrequenciesveryquicklyitispossibletoeliminatetheAutoCaltimebycalibratingtheVCOinadvanceandstoringtheswitchnumbervsfrequencyinformationinthehost.ThiscanbedonebyinitiallylockingthePLLwithIntegratedVCOoneachdesiredfrequencyusingAutoCal,thenreading,andstoringtheVCOswitchsettingsselected.TheVCOswitchsettingsareavailableinReg10h[7:0]aftereveryAutoCaloperation.ThehostmustthenprogramtheVCOswitchsettingsdirectlywhenchangingfrequencies.ManualwritestotheVCOswitchesareexecutedimmediatelyasarewritestotheintegerandfractionalregisterswhenAutoCalisdisabled.HencefrequencychangeswithmanualcontrolandAutoCaldisabled,requiresaminimumoftwoserialporttransferstothePLL,oncetosettheVCOswitches,andoncetosetthePLLfrequency.

IfAutoCalisdisabledReg0Ah[11]=1,theVCOwillupdateitsregisterswiththevaluewrittenviaReg05himmediately.TheVCOinternaltransferrequires16VSCKclockcyclesafterthecompletionofawriteto



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Reg05h.VSCKandtheAutoCalcontrollerclockareequaltotheinputreferencedividedby0,4,16or32ascontrolledbyReg0Ah[14:13].

1.2.2.1 Registers required for Frequency Changes in Fractional ModeAlargechangeoffrequency,infractionalmode(Reg06h[11]=1),mayrequireMainSerialPortwritesto:

1. theintegerregisterintg,Reg03h (only required if the integer part changes)

2.theVCOSPIregister,Reg05h

• requiredformanualcontrolofVCOifReg0Ah[11]=1 (AutoCal disabled)

• requiredtochangetheRFDividervalueifneeded(“VCO_Reg02hBiases”)

• requiredtoturnon/offthedoublermodeifneeded(VCO_Reg03h[0])

3.thefractionalregister,Reg04h.ThefractionalregisterwritetriggersAutoCalifReg0Ah[11]=0,andisloadedintothemodulatorautomaticallyafterAutoCalruns.IfAutoCalisdisabled,Reg0Ah[11]=1,thefractionalfrequencychangeisloadedintothemodulatorimmediatelywhentheregisteriswrittenwithnoadjustmenttotheVCO.

Smallstepsinfrequencyinfractionalmode,withAutoCalenabled(Reg0Ah[11]=0),usuallyonlyrequireasinglewritetothefractionalregister.Worstcase,5MainSerialPorttransferstotheHMC833LP6GEcouldberequiredtochangefrequenciesinfractionalmode.Ifthefrequencystepissmallandtheintegerpartofthefrequencydoesnotchange,thentheintegerregisterisnotchanged.Inallcases,infractionalmode,itisnecessarytowritetothefractionalregisterReg04hforfrequencychanges.

1.2.2.2 Registers Required for Frequency Changes in Integer ModeAchangeoffrequency,inintegermode(Reg06h[11]=0),requiresMainSerialPortwritesto:

1.VCOSPIregister,Reg05h

• requiredformanualcontrolofVCOifReg0Ah[11]=1 (AutoCal disabled)

• requiredtochangetheRFDividervalueifneeded(“VCO_Reg02hBiases”)

• requiredtoturnon/offthedoublermodeifneeded(VCO_Reg03h[0])

2.theintegerregisterReg03h.

• Inintegermode,anintegerregisterwritetriggersAutoCalifReg0Ah[11]=0,andisloadedintotheprescalerautomaticallyafterAutoCalruns.IfAutoCalisdisabled,Reg0Ah[11]=1,theintegerfrequency change is loaded into theprescaler immediatelywhenwrittenwith noadjustmenttotheVCO.NormallychangestotheintegerregistercauselargestepsintheVCOfrequency,hencetheVCOswitchsettingsmustbeadjusted.AutoCalenabledistherecommendedmethodforintegermodefrequencychanges.IfAutoCalisdisabled(Reg0Ah[11]=1),aprioriknowledgeof the correctVCOswitch settingand the correspondingadjustment to theVCO is requiredbeforeexecutingtheintegerfrequencychange.

1.2.3 VCO AutoCal on Frequency ChangeAssuming Reg 0Ah[11]=0, the VCO calibration starts automatically whenever a frequency change isrequested.IfitisdesiredtoreruntheAutoCalroutineforanyreason,atthesamefrequency,simplyrewritethefrequencychangewiththesamevalueandtheAutoCalroutinewillexecuteagainwithoutchangingfinalfrequency.



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1.2.4 VCO AutoCal Time & AccuracyTheVCOfrequencyiscountedforTmmt,theperiodofasingleAutoCalmeasurementcycle.

Tmmt = Txtal · R · 2n (EQ1)

n issetbyReg0Ah[2:0]andresultsinmeasurementperiodswhicharemultiplesofthePDperiod,TxtalR.

R isthereferencepathdivisionratiocurrentlyinuse,Reg02h

Txtal istheperiodoftheexternalreference(crystal)oscillator.

TheVCOAutoCalcounterwill,onaverage,expectNcounts,roundeddown(floor)tothenearestinteger,everyPDcycle.

N istheratioofthetargetVCOfrequency,fvco,tothefrequencyofthePD,fpd,whereNcanbeanyrationalnumbersupportedbytheNdivider.

Nissetbytheinteger(Nint = Reg03h)andfractional(Nfrac = Reg04h)registercontents

N = Nint + Nfrac / 224 (EQ2)

TheAutoCalstatemachineandthedatatransferstotheinternalVCOsubsystemSPI(VSPI)runattherateoftheFSMclock,TFSM,wheretheFSMclockfrequencycannotbegreaterthan50MHz.

TFSM = Txtal · 2m (EQ3)

m is0,2,4or5asdeterminedby Reg0Ah[14:13]

TheexpectednumberofVCOcounts,V,isgivenby

V = floor (N · 2n) (EQ4)

ThenominalVCOfrequencymeasured,fvcom,isgivenby

fvcom = V · fxtal / (2n · R) (EQ5)

wheretheworstcasemeasurementerror,ferr,is:

ferr ≈ ±fpd / 2n + 1 (EQ6)

Figure 31. VCO CalibrationA 5-bit step tuned VCO, for example, nominally requires 5measurements for calibration, worst case6measurements, andhence7VSPIdata transfersof 20 clock cycleseach.Themeasurementhasaprogrammablenumberofwait states, k, of 100FSMcyclesdefinedbyReg0Ah[7:6] = k.Hence totalcalibrationtime,worstcase,isgivenby:

Tcal = k128TFSM + 6TPD 2n + 7 · 20TFSM(EQ7)



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orequivalently

Tcal = Txtal (6R · 2n + (140+128k) · 2m)where k = Reg0Ah[7:6] decimal

(EQ8)

For guaranteed hold of lock, across temperature extremes, the resolution should be better than1/8ththefrequencystepcausedbyaVCOsub-bandswitchchange.Betterresolutionsettingswillshownoimprovement.

1.2.4.1 VCO AutoCal ExampleTheVCOsubsystemmustsatisfythemaximumfpdlimitedbythetwofollowingconditions:

a.N≥16(fint),N≥20.0(ffrac),whereN=fVCO/fpd

b.fpd≤100MHz

SupposetheVCOsubsystemoutputfrequencyistooperateat2.01GHz.Ourexamplecrystalfrequencyisfxtal= 50 MHz, R=1, and m=0 (Figure31),henceTFSM=20ns(50MHz).Note,whenusingAutoCal,themaximumAutoCalFiniteStateMachine(FSM)clockcannotexceed60MHz(seeReg0Ah[14:13]).TheFSMclockdoesnotaffecttheaccuracyofthemeasurement,itonlyaffectsthetimetoproducetheresult.Thissameclockisusedtoclockthe16bitVCOserialport.

Iftimetochangefrequenciesisnotaconcern,thenonemaysetthecalibrationtimeformaximumaccuracy,andthereforenotbeconcernedwithmeasurementresolution.

Usinganinputcrystalof50MHz(R=1andfpd=50MHz)thetimesandaccuraciesforcalibrationusing(EQ6)and(EQ8)areshowninTable1.Whereminimaltuningtimeis1/8thoftheVCObandspacing.

Across all VCOs, ameasurement resolution better than 800 kHzwill produce correct results. Settingm=0,n=5,provides781kHzofresolutionandadds8.6µsofAutoCaltimetoanormalfrequencyhop.OncetheAutoCalsetsthefinalswitchvalue,8.64µsafterthefrequencychangecommand,thefractionalregisterwillbeloaded,andtheloopwilllockwithanormaltransientpredictedbytheloopdynamics.HencewecanseeinthisexamplethatAutoCaltypicallyaddsabout8.6µstothenormaltimetoachievefrequ-encylock.Hence,AutoCalshouldbeusedforallbutthemostextremefrequencyhoppingrequirements.

Table 1. AutoCal Example with Fxtal = 50 MHz, R = 1, m = 0

ControlValueReg0Ah[2:0]

n 2nTmmt(µs)

Tcal(µs)

FerrMax

0 0 1 0.02 4.92 ±25MHz

1 1 2 0.04 5.04 ±12.5MHz

2 2 4 0.08 5.28 ±6.25MHz

3 3 8 0.16 5.76 ±3.125MHz

4 5 32 0.64 8.64 ±781kHz

5 6 64 1.28 12.48 ±390kHz

6 7 128 2.56 20.16 ±195kHz

7 8 256 5.12 35.52 ±98kHz

1.2.5 VCO Output Mute FunctionTheoutputmutefunctionenablestheHMC833LP6GEtodisabletheVCOoutputwhilemaintainingthePLLandVCOsubsystemsfullyfunctional.Themutefunctionprovidesover40dBofisolationthroughouttheoperatingrangeoftheHMC833LP6GE.TomutetheoutputoftheHMC833LP6GE,thefollowingregisterwritesarenecessary:

1. Initially,andonlyonce,typicallyafterpower-up,pre-configuretheVCOsubsystembywritingVCO_Reg01h[8:0]=3h(accomplishedbywriting toReg05h=188h).Thiswriteeffectivelyenables themasterenable,andPLLbufferenable,anddisablesthemanualmodeRFbuffer,divide-by1,andRF



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divideroftheVCOsubsystem,asshowninFigure27.AlthoughthiswritedisablesthemanualmodeenablesoftheVCOsubsystem,ithasnoaffectonthePLLorVCOsubsystembecausetypicallyandbydefaulttheVCOsubsystemisoperatinginautomode.

2. ThentomutethePLLoutputsimplywriteVCO_Reg03h[2]=1(accomplishbywritingtoPLLReg05h=2218hindoublermode,andReg05h=2A98hinfundamentalmodeoftheVCO),whicheffectivelyplacestheVCOsubsysteminmanualmode.Manualmodeenableshavebeenpre-configuredinstep1tomutethePLLoutput.

3. IfitisrequiredtotunetheHMC833LP6GEwhiletheoutputismutedafinalwrite,Reg05h=0h,isrequired.

ToenabletheHMC833LP6GEoutputaftermuting:1. WriteVCO_Reg03h[2]=0(accomplishbywritingtoPLLReg05h=2018hindoublermode,orReg

05h=2898hinfundamentalmode).2. AfinalwritetoReg05h=0hisrequired.

PleaserefertoFigure27formoreinformation.AlsonotethattheVCOsubsystemregistersarenotdirectlyaccessible. They are written to the VCO subsystem via PLL Reg 05h. More information about VCOsubsystemSPIinsection1.19.

1.3 VCO Built in Test with AutoCalThefrequencylimitsoftheVCOcanbemeasuredusingtheBISTfeaturesoftheAutoCalmachine.

ThisisdonebysettingReg0Ah[10]=1whichfreezestheVCOswitchesinoneposition.VCOswitchesmaythenbewrittenmanually,withthevaractorbiasedatthenominalmid-railvoltageusedforAutoCal.ForexampletomeasuretheVCOmaximumfrequencyuseswitch0,writtentotheVCOsubsystemviaReg05h=[0000000000000VCOID].WhereVCOID=‘000’b.

IfAutoCalisenabled,(Reg0Ah[11]=0),andanewfrequencyiswritten,AutoCalwillrun,butwithswitchesfrozen.TheVCOfrequencyerrorrelativetothecommandfrequencywillbemeasuredandresultswrittentoReg11h[19:0]whereReg11h[19]isthesignbit.TheresultwillbewrittenintermsofVCOcounterror(EQ4).ForexampleiftheexpectedVCOis2GHz,referenceis50MHz,andnis6,weexpecttomeasure2560counts.Ifwemeasureadifferenceof-5countsinReg11h,thenitmeansweactuallymeasured2555counts.HencetheactualfrequencyoftheVCOis5/2560low,or1.99609375GHz,±1Count~±781kHz.

1.4 Spurious Performance

1.4.1 Integer Operation and Reference SpuriousTheVCOalwaysoperatesatanintegermultipleofthePDfrequencyinanintegersynthesizer.Ingeneral,spurioussignalsoriginatingfromanintegersynthesizercanonlyoccuratmultiplesofthePDfrequency.These unwanted outputs closest to the carrier are often simply referred to as reference sidebands.Unwantedreferenceharmonicscanalsoexistfarfromthecarrierduetocircuitisolation.

Spursunrelatedtothereferencefrequencymustoriginatefromoutsidesources.ExternalspurioussourcescanmodulatetheVCOindirectlythroughpowersupplies,ground,oroutputports,orbypasstheloopfilterduetopoorisolationofthefilter.ItcanalsosimplyaddtotheoutputofthePLL.

Referencespuriouslevelsaretypicallybelow-100dBcwithawelldesignedboardlayout.Aregulatorwithlownoiseandhighpower supply rejection, suchas theHMC1060LP3E, is recommended tominimizeexternalspurioussources.

Referencespuriouslevelsofbelow-100dBcrequiresuperbboardisolationofpowersupplies,isolationoftheVCOfromthedigitalswitchingofthesynthesizerandisolationoftheVCOloadfromthesynthesizer.Typicalboardlayout,regulatordesign,evalboardsandapplicationinformationareavailableforverylowspuriousoperation.Operationwithlowerlevelsofisolationintheapplicationcircuitboard,fromthoserec-ommendedbyHittite,canresultinhigherspuriouslevels.



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IftheapplicationenvironmentcontainsotherinterferingfrequenciesunrelatedtothePDfrequency,andiftheapplicationisolationfromtheboardlayoutandregulationareinsufficient,theunwantedinterferingfrequencieswillmixwith thedesiredsynthesizeroutputandcauseadditionalspuriousemissions.Theleveloftheseemissionsisdependantuponisolationandsupplyregulationorrejection(PSRR).

1.4.2 Fractional Operation and SpuriousUnlikeanintegerPLL,spurioussignalsinafractionalPLLcanoccurduetothefactthattheVCOoperatesatfrequenciesunrelatedtothePDfrequency.HenceintermodulationoftheVCOandthePDharmonicscancausespurioussidebands.SpuriousemissionsarelargestwhentheVCOoperatesveryclosetoanintegermultipleofthePD.WhentheVCOoperatesexactlyataharmonicofthePDthen,noin-closemixingproductsarepresent.

AsshowninFigure32,interferenceisalwayspresentatmultiplesofthePDfrequency,fpd,andtheVCOfrequency,fvco.Thedifference,Δ,betweentheVCOfrequencyandthenearestharmonicofthereference,will createwhat are referred to as integer boundary spurs.Dependingupon themodeof operationofthesynthesizer,higherorder, lowerpowerspursmayalsooccuratmultiplesof integer fractions(sub-harmonics)ofthePDfrequency.Thatis,fractionalVCOfrequencieswhicharenearnfpd+fpdd/m,wheren,dandmareallintegersandd<m(mathematiciansrefertod/masarationalnumber).Wewillrefertofpdd/masanintegerfraction.Thedenominator,m,istheorderofthespuriousproduct.HighervaluesofmproducesmalleramplitudespuriousatoffsetsofmΔandusuallywhenm>4spursaresmallorunmeasurable.

Theworstcase,infractionalmode,iswhend=0,andtheVCOfrequencyisoffsetfromnfpdbylessthantheloopbandwidth.Thisisthe“in-bandintegerboundary”case.

Figure 32. Fractional Spurious ExampleCharacterizationofthelevelsandordersoftheseproductsisnotunlikeamixerspurchart.Exactlevelsoftheproductsaredependentuponisolationofthevarioussynthesizerparts.Hittitecanofferguidanceaboutexpected levelsofspuriouswithHMC833LP6GEevaluationboards.Regulatorswithhighpowersupplyrejectionratios(PSRR)arerecommended,especiallyinnoisyapplications.

1.4.2.1 Charge Pump and Phase Detector Spurious ConsiderationsCharge pump and phase detector linearity are of paramount importancewhen operating in fractionalmode.Anynon-linearitydegradesphasenoiseandspuriousperformance.



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Wedefinezerophaseerrorwhen the referencesignaland thedividerVCOsignalarriveat thePhaseDetectorat thesame time. Phasedetector linearitydegradeswhen thephaseerror isverysmallandwhentherandomphaseerrorscausethephasedetectortoswitchbackanforthbetweenreferenceleadandVCOlead.

Theseswitchingnon-linearitiesinfractionalmodeareeliminatedbyoperatingthephasedetectorwithanaveragephaseoffsetsuchthateitherthereferenceorVCOalwaysleads.

AprogrammablechargepumpoffsetcurrentsourceisusedtoaddDCcurrenttotheloopfilterandcreatethedesiredphaseoffset.PositivecurrentcausestheVCOtolead,negativecurrentcausesthereferencetolead.

TheoffsetchargepumpiscontrolledviaReg09h.Thephaseoffsetisscaledfrom0degrees,thatisthereferenceandtheVCOpatharriveinphase,to360degrees,wheretheyarriveafullcyclelate.Theoffsetcanalsobethoughtofinabsolutetimedifferencebetweenthearrivals.

Therecommendedoperatingpointforthechargepumpinfractionalmodeisonewherethetimeoffsetatthephasedetectoris~2.5ns+4TVCO,whereTVCOistheRFperiodatthefractionalprescalerinput.TherequiredCPoffsetcurrentshouldneverexceed25%oftheprogrammedCPcurrent.

The specific level of chargepumpoffset currentReg09h[20:14] is determinedby this timeoffset, thecomparisonfrequencyandthechargepumpcurrent:

( ) ( )( )92.5 10 4 sec ,0.25Required CP Offset min VCO comparison CP CPT F I I− • + • • • • =

where:

TVCO: is the RF period at the fractional prescaler input

ICP: is the full scale current setting of the switching charge pump Reg09h[6:0] Reg09h[13:7]

(EQ9)

OperationwithchargepumpoffsetinfluencestherequiredconfigurationoftheLockDetectfunction.RefertothedescriptionofLockDetectfunctioninsection1.11.Notethatthiscalculationcanbeperformedforthecenterfrequencyof theVCO,anddoesnotneedrefinementforsmalldifferences<25%incenterfrequencies.

AnotherfactorinthespectralperformanceinFractionalModeisthechoiceoftheDelta-SigmaModulatormode.ModeAcanofferbetterin-bandspectralperformance(insidetheloopbandwidth)whileModeBoffersbetteroutofbandperformance.SeeReg06h[3:2] forDSMmodeselection.Finally,all fractionalsynthesizerscreatefractionalspursatsomelevel.Hittiteoffersthelowestlevelfractionalspuriousintheindustryinanintegratedsolution.

1.4.2.2 Spurious Related to Channel Step Size (Channel Spurs)ManyfractionalPLLsalsocreatespuriousemissionsatoffsetswhicharemultiplesofthechannelstepsize.WerefertotheseasChannelSpurs.Itiscommonintheindustrytosetthechannelstepsizebyuseoftheso-calledmodulus.Forexample,channelstepsizeof100kHzrequiresasmallmodulusrelatedtothestepsize,andoftenresultsin100kHzChannelSpurs.

The HMC833LP6GE uses a large fixedmodulus unrelated to the channel step size. As a result, theHMC833LP6GEhasextremelyloworunmeasurableChannelSpurs.InadditionExactFrequencyMode(1.12.2.2)allowsexactchannelstepsizewithnoChannelSpurs.

ThelackofChannelSpursmeansthattheHMC833LP6GEhaslargeregionsofoperationbetweenIntegerBoundarieswithlittleornospursofanykind.LargespuriousfreezonesenabletheHMC833LP6GEtobeusedwithatunablereference,toeffectivelymovethespurfreezonesandhenceachievespur-freeoperationatallfrequencies.TheresultingPLLisvirtuallyspur-freeatallfrequencies.

Formoreinformationsee1.4.2.3.



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1.4.2.3 Spurious Reduction with Tunable ReferenceSection 1.4.2 discussed fractional mode Integer Boundary spurious caused by VCO operation nearreferenceharmonics. It ispossible,withHittite fractionalsynthesizers, tovirtuallyeliminate the integerboundaryspuriousatagivenVCOfrequencybychangingthefrequencyofthereference.Thereferencefrequencyisnormallygeneratedbyacrystaloscillatorandisnottunable.However,anyofHittite’swidebandPLLswithIntegratedVCOs,includingHMC833LP6GE,canbeusedasahigh-qualitytunablereferencesource,asshowninFigure33.

Figure 33. TunablereferencesourceWiththesetupshowninFigure33,theHMC833LP6GEiscapableofoperatingacrossallofitsfrequencyrangewithoutsacrificingphasenoise,whilevirtuallyeliminatingspuriousemissions.Optimumoperationrequiresappropriateconfigurationofthetwosynthesizerstoachievethisperformance.Hittiteapps-supportcanassistwiththerequiredalgorithmsforultra-lowspurioustunablereferenceapplications.

An HMC833LP6GE tunable reference PLL typically uses a high frequency crystal reference for bestperformance.PhasenoisefromtheMC830LP6GEtunablereferenceoutputat100kHzoffsetvariestypicallyfrom-145dBcat100MHzoutputto-157dBcat25MHzoutput.ThisperformanceofHMC833LP6GEasatunablereferenceisequivalenttothephasenoiseofhighperformancecrystaloscillators.

Figure 34. Phase noise performance of the HMC833LP6GE

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curves respectively.)Worst case spurious levels (largest spurs at any offset) of conventional fixed reference vs. a tunablereferencecanbecomparedbymultipleindividualphasenoisemeasurementsandsummarizedonasingleplotvs.carrierfrequency.

Forexample,Figure35showsthespectrumofacarrieroperatingat2000.1MHzwitha50MHzfixedreference.Thiscaseis100kHzawayfromanIntegerBoundary(50MHzx40).Worstcasespuriouscanbeobservedat100kHzoffsetandabout-52dBcinmagnitude.

Figure36showsthesameHMC833LP6GEPLLVCOoperatingatthesame2000.1MHzcarrierfrequency,usingatunablereferenceat47.5MHzgeneratedbyHMC830LP6GE.Worstcasespuriousinthiscasecanbeobservedat5MHzoffsetandabout-100dBcinmagnitude.

The resultsofFigure35andFigure36show that the tunable referencesourceachieves50dBbetterspuriousperformance,whilemaintainingessentiallythesamephasenoiseperformance.



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-160

-140

-120

-100

-80

-60

-40

-20

0

0.1 1 10 100 1000 10000 100000

PH

AS

E N

OIS

E (

dBc/

Hz)

OFFSET (kHz)

2000.1 MHz Carrier Frequency

Worst Spur at 5.1 MHz offsetat -100 dBc with TunableReference

(B)

Figure 35. HMC833LP6GE Worst spur at any offset, fixed 50 MHz reference, output frequency = 2000.1

MHz

Figure 36. HMC833LP6GE worst spur at any offset, tunable reference (HMC830LP6GE), output

frequency = 2000.1 MHz

Manyspuriousmeasurements,suchastheonesinFigure35andFigure36canbesummarizedintoasingleplotofworstcasespuriousatanyoffsetvs.carrierfrequencyasshowninFigure37.Alogfrequencydisplayrelativetothe2000MHzfixedreferenceIntegerBoundarywasusedtoemphasizetheimportanceoftheloopbandwidthonspuriousperformanceofthefixedreferencecase.Thistechniqueclearlyshowsthelogarithmicroll-offoftheworstcasespuriouswhenoperatingneartheIntegerBoundary.InthiscasetheloopfilterbandwidthoftheHMC833LP6GEwas100kHz.

Figure 37.

-120

-110

-100

-90

-80

-70

-60

-50

2GHz +1kHz 2GHz +10kHz 2GHz +100kHz 2GHz +1000kHz 2GHz +10000k

Fixed 50 MHz ReferenceTunable Reference

WO

RS

T S

PU

R (

dBc)

OUTPUT FREQUENCY

(A)

(B)

Largest observed spurious, at any offset, using a fixed 50 MHz reference source and a tunable reference source.

Forexampleworstcasespuriousoperatingat2000.1MHz(point(A)) inFigure35withafixed50MHzreference)isrepresentedbyasinglepointinFigure37(point(A))onthebluecurve.Similarly,worstcasespuriousfromFigure36withvariablereference,operatingat2000.1MHzisrepresentedbyasinglepointinFigure37(point(B))onthegreencurve.

The plot in Figure 37 is generated by tuning the carrier frequency away from Integer Boundary andrecordingtheworstcasespurious,atanyoffset,ateachoperatingfrequency.Figure37showsthattheworstcasespurious for the50MHzfixedreferencecase, isnearlyconstantbetween-51dBcand-55dBcwhenoperatingwithacarrierfrequencylessthan100kHzfromtheIntegerBoundary(bluecurve).Italsoshowsthattheworstcasespuriousrollsoffatabout25dB/decaderelativeto1loopbandwidth.Forexample,atanoperatingfrequencyof2001MHz(equivalentto10loopbandwidthsoffset)worstcasespuriousis-80dBc.Similarly,atanoperatingfrequencyof2010MHz(equivalentto100loopbandwidths)worstcasespuriousis-100dBc.



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Incontrast, thegreencurveofFigure37shows that theworstcasespuriousover thesameoperatingfrequency range,whenusinganHMC830LP6GEtunable reference, isbelow-100dBcatalloperatingfrequencies!

IngeneralallfractionalPLLshavespuriouswhenoperatingnearIntegerBoundaries.HighperformancetunablereferencemakesitpossibletooperateHMC833LP6GE,virtuallyspur-freeatallfrequencies,withlittleornodegradationinphasenoise.

1.5 Integrated Phase Noise & JitterThestandarddeviationofVCOsignaljittermaybeestimatedwithasimpleapproximationifitisassumedthatthelockedVCOhasaconstantphasenoise,o|2(fo),atoffsetslessthantheloop3dBbandwidthanda20dBperdecaderoll-offatgreateroffsets.ThesimplelockedVCOphasenoiseapproximationisshownontheleftofFigure38.

Figure 38. PLL with Integrated VCO Phase Noise & JitterWiththissimplificationthetotalintegratedVCOphasenoise,o|2,inrads2inthelinearformisgivenby

o|2=o|2(fo) Bπ (EQ10)

whereo|2(fo) isthesinglesidebandphasenoiseinrads2/Hzinsidetheloopbandwidth,andBisthe3dB

cornerfrequencyoftheclosedloopPLL

Theintegratedphasenoiseatthephasefrequencydetector,o|2pd

isjustscaledbyN2

/N2=o|2pd o|2 (EQ11)

ThermsphasejitteroftheVCOinrads,o|,isjustthesquarerootofthephasenoiseintegral.

Sincethesimpleintegralof(EQ10)isjustaproductofconstants,wecaneasilydotheintegralinthelogdomain.ForexampleiftheVCOphasenoiseinsidetheloopis-100dBc/Hzat10kHzoffsetandtheloopbandwidthis100kHz,andthedivisionratiois100,thentheintegratedphasenoiseatthephasefrequencydetector,indB,isgivenby:

o|2=10log(o|2(fo)Bπ/N2)=-100+50+5-40=-85dBcpddB

orequivalently,o|=10-85/20=53.6e-6rads=3.2e-3degrees.

Whilethephasenoisereducesbyafactorof20logNafterdivisiontothereference,duetotheincreasedperiodofthePDreferencesignal,thejitterisconstant.

Thermsjitterfromthephasenoiseisthengivenby

Tjpn = Tpdo|pd/2π (EQ12)

InthisexampleifthePDreferencewas50MHz,Tpd=20ns,andhenceTjpn=179femto-sec.

Itshouldbenotedthatthislastexpressionisbaseduponaclosedformintegraloftheentirespectrumoftheoscillatorphasenoise.ThisintegralstartsatDC.Itiscommonforrealsystemtoevaluatejitterovershorterintervalsoftime,hencetheintegraloftenstartsatsomefinitefrequencyoffsetandwillproducea



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jitterthatislessthanthatgivenbythefullexpression.Finallyrealoscillatorshavenoisefloorsthatalsocontributetojitter.Thephasenoiseofawhitenoisefloorisasimpleintegralofnoisefloordensitytimesbandwidthof interest to thesystem.Thisadditionalnoisepowershouldbeadded to theexpressionof(EQ16)togiveamoreaccuratejitternumber.Dependinguponthebandwidthofthesysteminquestionthisnoisefloorcontributionmaybeanimportantfactor.

1.6 Reference Input Stage

Figure 39. Reference Path Input StageThe referencebuffer provides thepath fromanexternal reference source (generally crystal based) totheRdivider,andeventuallytothephasedetector.ThebufferhastwomodesofoperationcontrolledbyReg08h[21].HighGain(Reg08h[21]=0),recommendedbelow200MHz,andHighfrequency(Reg08h[21]=1),for200to350MHzoperation.ThebufferisinternallyDCbiased,with100Ωinternaltermination.For50Ωmatch,anexternal100Ωresistortogroundshouldbeadded,followedbyanACcouplingcapacitor(impedance<1Ω),thentotheXREFPpinofthepart.

Atlowfrequencies,arelativelysquarereferenceisrecommendedtokeeptheinputslewratehigh.Athigherfrequencies,asquareorsinusoidcanbeused.Thefollowingtableshowstherecommendedoperatingregionsfordifferentreferencefrequencies. Ifoperatingoutsidetheseregionsthepartwillnormallystilloperate,butwithdegradedreferencepathphasenoiseperformance.

Minimumpulsewidthatthereferencebufferinputis2.5ns.ForbestspurperformancewhenR=1,thepulsewidthshouldbe(2.5ns+8TPS),whereTPSistheperiodoftheVCOattheprescalerinput.WhenR>1minimumpulsewidthis2.5ns.

Table 2. Reference Sensitivity TableSquareInput SinusoidalInput

ReferenceInputFrequency

(MHz)

Slew>0.5V/ns RecommendedSwing(Vpp) RecommendedPowerRange(dBm)

Recommended Min Max Recommended Min Max

<10 YES 0.6 2.5 x x x

10 YES 0.6 2.5 x x x

25 YES 0.6 2.5 ok 8 15

50 YES 0.6 2.5 YES 6 15

100 YES 0.6 2.5 YES 5 15

150 ok 0.9 2.5 YES 4 12

200 ok 1.2 2.5 YES 3 8

Input referredphasenoiseof thePLLwhenoperatingat50MHz isbetween -150and -156dBc/Hzat



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10kHzoffsetdependinguponthemodeofoperation.Theinputreferencesignalshouldbe10dBbetterthanthisfloortoavoiddegradationofthePLLnoisecontribution.ItshouldbenotedthatsuchlowlevelsareonlynecessaryifthePLListhedominantnoisecontributorandtheselevelsarerequiredforthesystemgoals.

1.7 Reference Path ’R’ DividerThereferencepath“R”dividerisbasedona14-bitcounterandcandivideinputsignalsbyvaluesfrom1to16,383andiscontrolledbyrdiv (Reg02h).

Minimumpulsewidthatthereferencebufferinputis2.5ns.ForbestspurperformancewhenR=1,thepulsewidthshouldbe(2.5ns+8Tps),whereTpsistheperiodoftheVCOattheprescalerinput.WhenR>1minimumpulsewidthis2.5ns.

1.8 RF Path ’N’ DividerThemainRFpathdivideriscapableofaveragedivideratiosbetween219-5(524,283)and20infractionalmode,and219-1(524,287)to16inintegermode.TheVCOfrequencyrangedividedbytheminimumNdividervaluewillplacepracticalrestrictionsonthemaximumusablePDfrequency.ForexampleaVCOoperatingat1.5GHzinfractionalmodewithaminimumNdividervalueof20willhaveamaximumPDfrequencyof75MHz.

1.9 Charge Pump & Phase DetectorThePhasedetector(PD)hastwoinputs,onefromthereferencepathdividerandonefromtheRFpathdivider.When in lock these two inputsareat thesameaverage frequencyandarefixedataconstantaveragephaseoffsetwithrespecttoeachother.WerefertothefrequencyofoperationofthePDasfpd.Most formulae related to step size, delta-sigmamodulation, timersetc., are functionsof theoperatingfrequencyofthePD,fpd.fpdisalsoreferredtoasthecomparisonfrequencyofthePD.

ThePDcomparesthephaseoftheRFpathsignalwiththatofthereferencepathsignalandcontrolsthechargepumpoutputcurrentasa linear functionof thephasedifferencebetween the twosignals.Theoutputcurrentvarieslinearlyoverafull±2πradians(±360°)ofinputphasedifference.

1.10 Phase Detector FunctionsPhasedetectorregisterReg0Bhallowsmanualaccesstocontrolspecialphasedetectorfeatures.

PD_up_en(Reg0Bh[5]), if 0, masksthePDupoutput,whichpreventsthechargepumpfrompumpingup.̀

PD_dn_en(Reg0Bh[6]), if 0,masksthePDdownoutput,whichpreventsthechargepumpfrompumpingdown.

Clearing bothPD_up_en andPD_dn_en effectively tri-states the charge pumpwhile leaving all otherfunctionsoperatinginternally.

PDForceUPReg0Bh[9] = 1andPDForceDN Reg0Bh[10] = 1allowsthechargepumptobeforcedupordownrespectively.ThiswillforcetheVCOtotheendstothetuningrangewhichcanbeusefulintestoftheVCO.

1.11 Phase Detector Window Based Lock DetectLock Detect Enable Reg07h[3]=1isaglobalenableforalllockdetectfunctions.

The window based Lock Detect circuit effectivelymeasures the difference between the arrival of thereferenceandthedividedVCOsignalsatthePD.Thearrival timedifferencemustconsistentlybelessthantheLockDetectwindowlength,todeclarelock.Eithersignalmayarrivefirst,onlythedifferenceinarrivaltimesiscounted.



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1.11.1 Analog Window Lock DetectThelockdetectwindowmaybegeneratedbyeitherananalogoneshotcircuitoradigitaloneshotbaseduponaninternaltimer.SettingReg07h[6]=0willresultinafixed,analog,nominal10nswindow,asshowninFigure40.TheanalogwindowcannotbeusedifthePDrateisabove50MHz,oriftheoffsetistoolarge.

Figure 40. Normal Lock Detect Window - Integer Mode, Zero OffsetForexamplea25MHzPDratewitha1mAchargepumpsetting(Reg09h[6:0]=Reg09h[13:7]= 32h)and400µAoffsetdowncurrent(Reg09h[20:14]=50h Reg09h[22]= 1),wouldhaveanoffsetofabout400/1000=40%ofthePDperiodorabout16ns.InsuchanextremecasethedividedVCOwouldarrive16nsafterthePDreference,andwouldalwaysarriveoutsideofthe10nslockdetectwindow.Insuchacasethelockdetectcircuitwouldalwaysreadunlocked,eventhoughtheVCOmightbelocked.Whenusingthe10nsanaloglockdetectwindow,witha40nsPDperiod,theoffsetmustalwaysbelessthan25%ofthechargepumpsetting,20%toallowfortolerances.Hencea1mAchargepumpsettingcannotusemorethan200µAoffsetwitha25MHzPDandananalogLockdetectwindow.Chargepumpcurrent,chargepumpoffset,phasedetectorrateandlockdetectwindowarerelated.

1.11.2 Digital Window Lock DetectSettingReg07h[6]=1willresultinavariablelengthlockdetectwindowbaseduponaninternaldigitaltimer.ThetimerperiodissetbythenumberofcyclesoftheinternalLDclockasprogrammedbyReg07h[9:7].TheLDclockfrequencyisadjustablebyReg07h[11:10].TheLDclocksignalcanbeviewedviatheGPOtestpins.Refer1.16fordetails.

1.11.3 Declaration of Lockwincnt_maxinReg07h[2:0]definesthenumberofconsecutivecountsofthedividedVCOthatmustlandinsidethelockdetectwindowtodeclarelock.Ifforexamplewesetwincnt_max=2048,thentheVCOarrivalwouldhavetooccur insidethewindow2048times inarowtobedeclared locked,whichwouldresultinaLockDetectFlaghigh.Asingleoccurrenceoutsideofthewindowwillresultinanoutoflock,i.e.LockDetectFlaglow.Oncelow,theLockDetectFlagwillstaylowuntilthewincnt_max=2048conditionismetagain.

TheLockDetectFlagstatus isalwaysreadable inReg12h[1], if locked=1.LockDetectstatus isalsooutputtotheLD_SDOpinifReg0Fh[4:0]=1.Again,iflocked,LD_SDOwillbehigh.Setting Reg0Fh[6]=0 willdisplaytheLockDetectFlagonLD_SDOexceptwhenaserialportreadisrequested,inwhichcasethepinrevertstemporarilytotheSerialDataOutpin,andreturnstotheLockDetectFlagafterthereadiscompleted.Referto1.11.5forTimingoftheLockDetectinformation.



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1.11.4 Phase Offset & Fractional LinearityWhenoperatinginfractionalmodethelinearityofthechargepumpandphasedetectoraremuchmorecritical than in integermode.Thephasedetector linearity isdegradedwhenoperatingwithzerophaseoffset.HenceinfractionalmodeitisnecessarytooffsetthephaseofthePDreferenceandtheVCOatthephasedetector.Insuchacase,forexamplewithanoffsetdelay,asshowninFigure41,theVCOarrivalwillalwaysoccurafterthereference.Thelockdetectcircuitwindowmayneedtobeadjustedtoallowforthedelaybeingused.fordetailsseesection“DigitalLockDetectwithDigitalWindowExample”.

Figure 41. Lock Detect Window - Fractional Mode with Offset

1.11.5 Digital Lock Detect with Digital Window ExampleTypicalDigitalLockdetectwindowwidthsareshowninTable3.LockDetectwindowstypicallyvary±10%vsvoltageand±25%overtemperature(-40°Cto+85°C).

Table 3. Typical Digital Lock Detect WindowLD Timer Speed

Reg07[11:10]Digital Lock Detect Window

Nominal Value ±25% (ns)

Fastest00 6.5 8 11 17 29 53 100 195

01 7 8.9 12.8 21 36 68 130 255

10 1.7 9.2 13.3 22 38 72 138 272

Slowest11 7.6 10.2 15.4 26 47 88 172 338

LDTimerDivideSettingReg07[9:7]

0 1 2 3 4 5 6 7

LDTimerDivideValue

0.5 1 2 4 8 16 32 64

Asanexample,ifweoperateinfractionalmodeat2GHzwitha50MHzPD,chargepumpcurrentgainof2mAandadownleakageof400uA.ThenouraverageoffsetatthePDwillbe0.4mA/2mA=0.2ofthePDperiodorabout4ns(0.2x1/50MHz).However,thefractionalmodulationoftheVCOdividerwillresultintimeexcursionsoftheVCOdivideroutputof+/-4Tvcofromthisaveragevalue(2nsinthisexample).Hence,wheninlock,thedividedVCOwillarriveatthePD4+/-2nsafterthedividedreference.TheLockDetectwindowalwaysstartsonthearrivalofthefirstsignalatthePD,inthiscasethereference.TheLockDetectwindowmustbelongerthan4ns+2ns(6ns)andshorterthantheperiodofthePD,inthisexample,20ns.AperfectLockDetectwindowwouldbemidwaybetweenthesetwovalues,or13ns.

There is a always a good solution for the LockDetectwindow for a given operating point. The user



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shouldunderstandhoweverthatonesolutiondoesnotfitalloperatingpoints.IfchargepumpoffsetorPDfrequencyarechangedsignificantlythenthelockdetectwindowmayneedtobeadjusted.

Figure 42. Lock Detect Window Example with 50 MHz PD and 3.9 ns VCO Offset

1.11.6 Cycle Slip Prevention (CSP)When changing VCO frequency and the VCO is not yet locked to the reference, the instantaneousfrequenciesofthetwoPDinputsaredifferent,andthephasedifferenceofthetwoinputsatthePDvariesrapidlyoverarangemuchgreaterthan±2πradians.SincethegainofthePDvarieslinearlywithphaseupto±2π,thegainofaconventionalPDwillcyclefromhighgain,whenthephasedifferenceapproachesamultipleof2π,tolowgain,whenthephasedifferenceisslightlylargerthanamultipleof0radians.TheoutputcurrentfromthechargepumpwillcyclefrommaximumtominimumeventhoughtheVCOhasnotyetreacheditsfinalfrequency.

Thechargeontheloopfiltersmallcapmayactuallydischargeslightlyduringthelowgainportionofthecycle.ThiscanmaketheVCOfrequencyactuallyreversetemporarilyduringlocking.Thisphenomenaisknownascycleslipping.Cycleslippingcausesthepull-inrateduringthelockingphasetovarycyclically.CycleSlipping increases the time to lock toavaluegreater than thatpredictedbynormalsmallsignalLaplaceanalysis.

ThesynthesizerPDfeaturesanabilitytoreducecycleslippingduringacquisition.TheCycleSlipPreven-tion(CSP)featureincreasesthePDgainduringlargephaseerrors.ThespecificphaseerrorthattriggersthemomentaryincreaseinPDgainissetviaReg0Bh[8:7]

1.11.7 Charge Pump GainAsimplifieddiagramofthechargepumpisshowninFigure43.ChargepumpUpandDowngainsaresetbyCP DN GainandCP UP Gainrespectively(Reg09h[6:0] and Reg09h[13:7]).ThecurrentgainofthepumpinAmps/radianisequaltothegainsettingofthisregisterdividedby2π.

ForexampleifbothCP DN GainandCP UP Gainaresetto‘50d’theoutputcurrentofeachpumpwillbe1mAandthephasefrequencydetectorgainkp=1mA/2πradians,or159µA/rad.Seesection1.4formoreinformation.

1.11.8 Charge Pump Phase Offset - Fractional ModeInintegermode,thephasedetectoroperateswithzerooffset.ThedividedreferencesignalandthedividedVCOsignalarriveatthephasedetectorinputsatthesametime.Infractionalmodeofoperation,chargepumplinearityandultimately,phasenoise,ismuchbetteriftheVCOandreferenceinputsareoperatedwithaphaseoffset.AphaseoffsetisimplementedbyaddingaconstantDCoffsetcurrentattheoutputofthechargepump.

DC offset may be added to the UP or DN switching pumps using Reg 09h[21] or Reg 09h[22]. The



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magnitudeoftheoffsetiscontrolledbyReg09h[20:14],andcanrangefrom0to635µAinstepsof5µA.Downoffsetishighlyrecommendedinfractionalmodeofoperation.Integermodeofoperationworksbestwithzerooffset.

Asanexample,aPDcomparisonoffPD=50MHz(20nsperiod)withthemainpumpgainsetat2mA,andadown(DN)offsetof-385µAwouldrepresentaphaseoffsetofabout(-385/2000)*360=-69degrees.ThisisequivalenttothedividedVCOarriving3.8nsafterthereferenceatthePDinput.Itiscriticalthatphaseoffsetbeusedinfractionalmode.Normally,downoffsetslargerthan3nsaretypical.

If the charge pump gain is changed, for example to compensate for changes in VCO sensitivity, it isrecommendedtochangethechargepumpoffsetproportionallytomaintainaconstantphaseoffset.

Figure 43. Charge Pump Gain & Offset Control

1.12 Frequency TuningHMC833LP6GEVCOsubsystemalwaysoperates in fundamental frequencyofoperation(1500MHzto3000MHz).TheHMC833LP6GEgeneratesfrequenciesbelowitsfundamentalfrequency(25MHzto1500MHz)by tuning to theappropriate fundamental frequencyandselecting theappropriateOutputDividersetting(divideby2/4/6.../60/62)in“VCO_Reg02hBiases”[5:0].ConverselytheHMC833LP6GEgeneratesfrequenciesgreaterthanitsfundamentalfrequency(3000MHzto6000MHz)bytuningtotheappropriatefundamentalfrequencyandenablingthedoublermode(VCO_Reg03h[0]=0).

TheHMC833LP6GEautomaticallycontrols frequency tuning in the fundamentalbandofoperation, formoreinformationsee“1.2.1VCOAuto-Calibration(AutoCal)”.

To tune to frequenciesbelow the fundamental frequency range (<1500MHz) it is required to tune theHMC833LP6GE to the appropriate fundamental frequency, then select the appropriate output dividersetting(divideby2/4/6.../60/62)in“VCO_Reg02hBiases”[5:0].Similarly,totunetofrequenciesabovethefundamentalfrequencyrange(>3000MHz)itisrequiredtotunetheHMC833LP6GEtotheappropriatefundamentalfrequency,andthenenablethedoublermodeofoperation(VCO_Reg03h[0]=0).

1.12.1 Integer ModeTheHMC833LP6GEiscapableofoperatinginintegermode.ForIntegermodesetthefollowingregisters

a.DisabletheFractionalModulator,Reg06h[11]=0

b.BypasstheModulatorcircuit,Reg06h[7]=1

InintegermodetheVCOstepsizeisfixedtothatofthePDfrequency,fpd.Integermodetypicallyhas3dBlowerphasenoisethanfractionalmodeforagivenPDoperatingfrequency.Integermode,however,oftenrequiresalowerPDfrequencytomeetstepsizerequirements.Thefractionalmodeadvantageisthat



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higherPDfrequenciescanbeused,hencelowerphasenoisecanoftenberealizedinfractionalmode.ChargePumpoffsetshouldbedisabledinintegermode.

1.12.1.1 Integer Frequency TuningInintegermodethedigitalΔ∑modulatorisshutoffandtheN(Reg03h)dividermaybeprogrammedtoanyintegervalueintherange16to219-1.ToruninintegermodeconfigureReg06hasdescribed,thenprogramtheintegerportionofthefrequencyasexplainedby(EQ13),ignoringthefractionalpart.

a.DisabletheFractionalModulator,Reg06h[11]=0b.Bypassthedelta-sigmamodulatorReg06h[7]=1c. To tune to frequencies (<1500 MHz), select the appropriate output divider value “VCO_Reg 02h

Biases”[5:0].d.Totunetofrequencies(>3000MHz),enablethedoublermodeofoperation(VCO_Reg03h[0]=1).

WritingtoVCOsubsystemregisters(“VCO_Reg02hBiases”[5:0]andVCO_Reg03h[0]inthiscase)isaccomplishedindirectlythroughPLLregister5(Reg05h).MoreinformationoncommunicatingwiththeVCOsubsystemthroughPLLReg05hisavailablein“1.19VCOSerialPortInterface(SPI)”section.

1.12.2 Fractional ModeTheHMC833LP6GEisplacedinfractionalmodebysettingthefollowingregisters:

a.EnabletheFractionalModulator,Reg06h[11]=1

b.Connectthedeltasigmamodulatorincircuit,Reg06h[7]=0

1.12.2.1 Fractional Frequency TuningThisisagenericexample,withthegoalofexplaininghowtoprogramtheoutputfrequency.Actualvariablesaredependantuponthereferenceinuse.

TheHMC833LP6GEinfractionalmodecanachievefrequenciesatfractionalmultiplesofthereference.ThefrequencyoftheHMC833LP6GE, fvco,isgivenby

fvco=(Nint+Nfrac)=fint+ffrac

fxtal

R(EQ13)

fout=fvco/ k (EQ14)

Where:

fout istheoutputfrequencyafteranypotentialdividersordoublers.

k is0.5fordoubler,1forfundamental,ork=1,2,4,6,…58,60,62accordingtotheVCOSubsystemtype

Nint istheintegerdivisionratio,Reg03h,anintegernumberbetween20and 524,284

Nfrac isthefractionalpart,from0.0to0.99999...,Nfrac=Reg04h/224

R isthereferencepathdivisionratio,Reg02h

fxtal isthefrequencyofthereferenceoscillatorinput

fpd isthePDoperatingfrequency,fxtal/R



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Asanexample:

fout 1402.5MHz

k 2

fvco 2,805MHz

fxtal =50MHz

R =1

fpd =50MHz

Nint =56

Nfrac =0.1

Reg04h =round(0.1x224)=round(1677721.6)=1677722

fVCO=(56+)=2805 MHz +1.192 Hz error1677722

224

50e6

1(EQ15)

fout= =1402.5 MHz +0.596 Hz errorfVCO

2(EQ16)

Inthisexampletheoutputfrequencyof1402.5MHzisachievedbyprogrammingthe19-bitbinaryvalueof56d=38hinto intg_reginReg03h,andthe24-bitbinaryvalueof1677722d=19999Ahinto frac_regin Reg04h.The0.596Hzquantizationerrorcanbeeliminatedusingtheexactfrequencymodeifrequired.Inthisexampletheoutputfundamentalisdividedby2.Specificcontroloftheoutputdividerisrequired.Seesection3.0anddescriptionformoredetails.

1.12.2.2 Exact Frequency TuningDue toquantizationeffects, theabsolute frequencyprecisionofa fractionalPLL isnormally limitedbythenumberofbitsinthefractionalmodulator.Forexample,a24bitfractionalmodulatorhasfrequencyresolutionsetbythephasedetector(PD)comparisonratedividedby224.Thevalue224inthedenominatorissometimesreferredtoasthemodulus.HittitePLLsuseafixedmoduluswhichisabinarynumber.InsometypesoffractionalPLLsthemodulusisvariable,whichallowsexactfrequencystepstobeachievedwithdecimalstepsizes.Unfortunatelysmallstepsusingsmallmodulusvaluesresultsinlargespuriousoutputsatmultiplesof themodulusperiod(channelstepsize).ForthisreasonHittitePLLsusea largefixedmodulus.Normally,thestepsizeissetbythesizeofthefixedmodulus.Inthecaseofa50MHzPDrate,amodulusof224wouldresultina2.98Hzstepresolution,or0.0596ppm.Insomeapplicationsitisnecessarytohaveexactfrequencysteps,andevenanerrorof3Hzcannotbetolerated.

Fractional PLLs are able to generate exact frequencies (with zero frequency error) if N can beexactly represented in binary (eg. N = 50.0,50.5,50.25,50.75 etc.). Unfortunately, some commonfrequencies cannot be exactly represented. For example,Nfrac = 0.1 = 1/10must be approximated asround((0.1x224)/224)≈0.100000024.AtfPD=50MHzthistranslatesto1.2Hzerror.Hittite’sexactfrequencymodeaddressesthisissue,andcaneliminatequantizationerrorbyprogrammingthechannelstepsizetoFPD/10inReg0Chto10(inthisexample).Moregenerally,thisfeaturecanbeusedwheneverthedesiredfrequency,fVCO,canbeexactlyrepresentedonastepplanwherethereareanintegernumberofsteps(<214) across integer-N boundaries. Mathematically, this situation is satisfied if:

gcd gcd gcd1 14mod 0 where gcd( , )

2PD

PDVCOk VCOf

f f f f f and f

= = ≥ (EQ17)



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Where:

gcdstandsforGreatestCommonDivisor

fN=maximumintegerboundaryfrequency<fVCO1

fPD =frequencyofthePhaseDetector

andfVCOk arethechannelstepfrequencieswhere0<k<224-1,AsshowninFigure44.

Figure 44. Exact Frequency TuningSomefractionalPLLsareabletoachievethisbyadjusting(shortening)thelengthofthePhaseAccumulator(thedenominatororthemodulusoftheDelta-Sigmamodulator)sothattheDelta-Sigmamodulatorphaseaccumulator repeatsatanexactperiod related to the interval frequency (fVCOk - fVCO(k-1)) inFigure44.Consequently,theshortenedaccumulatorresultsinmorefrequentrepeatingpatternsandasaresultoftenleads tospuriousemissionsatmultiplesof the repeatingpatternperiod,oratharmonic frequenciesoffVCOk-fVCO(k-1).Forexample,insomeapplications,theseintervalsmightrepresentthespacingbetweenradiochannels,andthespuriouswouldoccuratmultiplesofthechannelspacing.

TheHittitemethodontheotherhandisabletogenerateexactfrequenciesbetweenadjacentinteger-Nboundarieswhilestillusing the full24bitphaseaccumulatormodulus, thusachievingexact frequencystepswithahighphasedetectorcomparisonrate,whichallowsHittitePLLstomaintainexcellentphasenoiseandspuriousperformanceintheExactFrequencyMode.

1.12.2.3.3 Using Hittite Exact Frequency ModeIftheconstraintin(EQ17)issatisfied,HMC833LP6GEisabletogeneratesignalswithzerofrequencyerroratthedesiredVCOfrequency.ExactFrequencyModemaybere-configuredforeachtargetfrequency,orbeset-upforafixedfgcdwhichappliestoallchannels.

1.12.2.4.4 Configuring Exact Frequency Mode For a Particular Frequency1. Calculate and program the integer register setting Reg 03h = NINT = floor(fVCO/fPD), where the

floor function is the rounding down to the nearest integer. Then the integer boundary frequencyfN=NINT ∙fPD

2. Calculate and program the exact frequency register value Reg 0Ch = fPD/fgcd, wherefgcd=gcd(fVCO,fPD)

3. CalculateandprogramthefractionalregistersettingReg04h( )242

ceil NVCOFRAC

PD

f fN

f

−= = ,whereceil

istheceilingfunctionmeaning“rounduptothenearestinteger.”

Example: To configure the HMC833LP6GE for exact frequency mode at fVCO = 2800.2 MHz where Phase Detector (PD) rate fPD = 61.44 MHz Proceed as follows:



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Check(EQ17)toconfirmthattheexactfrequencymodeforthisfVCOispossible.

( )

gcd gcd 14

66 6 3

gcd 14

gcd( , )2

61.44 10gcd 2800.2 10 ,61.44 10 120 10 37502

PDPDVCO

ff f f and f

f

= ≥

×= × × = × > =

Since (EQ 17) is satisfied, the HMC833LP6GE can be configured for exact frequency mode atfVCO=2800.2MHzasfollows:

1. NINT=Reg03h=6

62800.2 10 45 261.44 10

VCO

PD

ffloor floor d Dh

f

×= = =×

2. Reg0Ch=( ) ( )

6 6

6 6

61.44 10 61.44 10 512 200120000gcd , gcd 2800.2 10 ,61.44 10

PD

PDVCO

fd h

f f× ×= = = =

× ×

3. To program Reg 04h, the closest integer-N boundary frequency fN that is less than thedesired VCO frequency fVCO must be calculated. fN = fPD ∙ NINT. Using the current example:

( ) ( )6

24 6 624

6

45 61.44 10 2764.8 .

2 2800.2 10 2764.8 102Then Reg04h 9666560 938000

61.44 10

INTN PD

NVCO

PD

Nf f MHz

f fceil ceil d h

f

= × = × × =

× − ×−= = = =

×

1.12.2.5.5 Hittite Exact Frequency Channel ModeIf it is desirable to have multiple, equally spaced, exact frequency channels that fall withinthe same interval (ie. fN ≤ fVCOk < fN+1) where fVCOk is shown in Figure 44 and 1 ≤ k ≤ 214,itispossibletomaintainthesameinteger-N(Reg03h)andexactfrequencyregister(Reg0Ch)settingsandonlyupdatethefractionalregister(Reg04h)setting.TheExactFrequencyChannelModeispossibleif(EQ17)issatisfiedforatleasttwoequallyspacedadjacentfrequencychannels,i.e.thechannelstepsize.

ToconfiguretheHMC833LP6GEforExactFrequencyChannelMode,initiallyandonlyatthebeginning,integer(Reg03h)andexactfrequency(Reg0Ch)registersneedtobeprogrammedforthesmallestfVCO frequency(fVCO1inFigure44),asfollows:

1. CalculateandprogramtheintegerregistersettingReg03h=NINT=floor(fVCO1/fPD),where fVCO1 isshown inFigure44andcorresponds tominimumchannelVCOfrequency.Then the lower integerboundaryfrequencyisgivenbyfN=NINT∙fPD.

2. Calculate and program the exact frequency register value Reg 0Ch = fPD/fgcd,where fgcd=gcd((fVCOk+1- fVCOk),fPD)=greatestcommondivisorofthedesiredequidistantchannelspacingandthePDfrequency((fVCOk+1-fVCOk)andfPD).

Then,toswitchbetweenvariousequallyspacedintervals(channels)onlythefractionalregister(Reg04h)needstobeprogrammedtothedesiredVCOchannelfrequencyfVCOkinthefollowingmanner:

Reg04h=( )242

ceil NVCOkFRAC

PD

f fN

f

−= wherefN=floor(fVCO1/fPD),andfVCO1,asshowninFigure44,represents

thesmallestchannelVCOfrequencythatisgreaterthanfN.

Example: To configure the HMC833LP6GE for Exact Frequency Mode for equally spaced intervals of 100 kHz where first channel (Channel 1) = fVCO1 = 2800.200 MHz and Phase Detector (PD) rate fPD = 61.44 MHz proceed as follows:

First check that the exact frequency mode for this fVCO1 = 2800.2 MHz (Channel 1)andfVCO2=2800.2MHz+100kHz=2800.3MHz(Channel2)ispossible.



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( )( )

gcd1 gcd1 gcd2 gcd21 214 14

66 6 3

gcd1 14

66 6 3

gcd2 14

gcd( , ) gcd( , )2 2

61.44 10gcd 2800.2 10 ,61.44 10 120 10 37502

61.44 10gcd 2800.3 10 ,61.44 10 20 10 37502

PD PDPD PDVCO VCO

f ff f f and f and f f f and f

f

f

= ≥ = ≥

×= × × = × > =

×= × × = × > =

If(EQ17)issatisfiedforatleasttwooftheequallyspacedinterval(channel)frequenciesfVCO1,fVCO2,fVCO3,...fVCON,asitisabove,HittiteExactFrequencyChannelModeispossibleforalldesiredchannelfrequencies,andcanbeconfiguredasfollows:

1. Reg03h=6

16

2800.2 10 45 261.44 10

VCO

PD

ffloor floor d Dh

f

×= = =×

2. Reg0Ch=( )( ) ( )

6 6

3 61

61.44 10 61.44 10 3072 0020000gcd 100 10 ,61.44 10gcd ,

PD

PDVCOk VCOk

fd C h

f f f+

× ×= = = =× ×−

where(fVCOk+1- fVCOk)isthedesiredchannelspacing(100kHzinthisexample).

3. ToprogramReg04htheclosestinteger-NboundaryfrequencyfNthatislessthanthesmallestchannelVCOfrequencyfVCO1mustbecalculated.fN=floor(fVCO1/fPD).Usingthecurrentexample: 6

66

2800.2 10 45 61.44 10 2764.861.44 10N PDf f floor MHz

×= × = × × =×

ThenReg04h

( )

( )

241

1

24 6 6

6

2 for channel 1 where 2800.2

2 2800.2 10 2764.8 109666560 938000

61.44 10

NVCOVCO

PD

f fceil f MHz

f

ceil d h

−= =

× − ×= = =

×

4. Tochangefromchannel1 (fVCO1=2800.2MHz)tochannel2(fVCO2=2800.3MHz),onlyReg04hneedstobeprogrammed,aslongasallofthedesiredexactfrequenciesfVCOk(Figure44)fallbetweenthesameinteger-Nboundaries(fN<fVCOk<fN+1).InthatcaseReg04h=

( )24 6 6

6

2 2800.3 10 2764.8 109693867 93

61.44 10ceil d EAABh

× − ×= =

×,andsoon.

1.12.2.6 Seed Register & AutoSeed ModeThestartphaseofthefractionalmodulatordigitalphaseaccumulator(DPA)maybesettooneoffourpossibledefaultvaluesviatheseedregisterReg06h[1:0].IfAutoSeedReg06h[8]isset,thentheHMC833LP6GEwillautomaticallyreloadthestartphaseintotheDPAeverytimeanewfractionalfrequencyisselected.IfAutoSeedisnotset,thentheHMC833LP6GEwillstartnewfractionalfrequencieswiththelastvalueleftintheDPAfromthelastfrequency.Hencethestartphasewilleffectivelyberandom.Certainzeroorbinaryseedvaluesmaycausespuriousenergycorrelationatspecificfrequencies.Correlatedspursareadvantageousonly inveryspecialcaseswhere thespuriousareknown tobe faroutofbandandareremovedintheloopfilter.Formostcasesarandom,ornonzero,non-binarystartseedisrecommended.Further,sincetheAutoSeedalwaysstartstheaccumulatorsatthesameplace,performanceisrepeatable

ifAutoSeedisused.Reg06h[1:0]=2isrecommended.



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1.13 Soft Reset & Power-On ResetTheHMC833LP6GEfeaturesahardwarePoweronReset(POR).Allchipregisterswillberesettodefaultstatesapproximately250µsafterpowerup.

ThePLLsubsystemSPIregistersmayalsobesoftresetbyanSPIwritetoregister rst_swrst (Reg00h).NotethatthesoftresetdoesnotcleartheSPImodeofoperationreferredtoinsection1.17.2.ThesoftresetisappliedbywritingReg00h[5]=1.Theresetisaonetimeeventthatoccursimmediately.Theresetbitdoesnothavetobereturnedto0afterareset.ItshouldbenotedthattheVCOsubsystemisnotaffectedbythePLLsoftreset.TheVCOsubsystemregisterscanonlyberesetbyremovingthepowersupply.

NOTE: if external power supplies or regulators have rise times slower than 250 µs, then it is advised to write to the SPI reset register (Reg00h[5]=1) immediately after power up, before any other SPI activity. This will ensure starting from a known state.

1.14 Power Down Mode NotethattheVCOsubsystemisnotaffectedbytheCENorsoftreset.Hencedevicepowerdownisatwostepprocess.FirstpowerdowntheVCObywriting0toVCOregister1viaReg05handthenpowerdownthePLLbypullingCENpin17low(assumingnoSPIoverrides(Reg01h[0]=1)).Thiswillresultinallanalogfunctionsandinternalclocksdisabled.Currentconsumptionwilltypicallydropbelow10µAinPowerDownstate.TheserialportwillstillrespondtonormalcommunicationinPowerDownmode.

ItispossibletoignoretheCENpin,byclearing rst_chipen_pin_select (Reg01h[0]=0).ControlofPowerDownModethencomesfromtheserialportregisterrst_chipen_from_spi, Reg01h[1].

ItisalsopossibletoleavevariousblocksonwheninPowerDown(see Reg01h),including:

a.InternalBiasReferenceSources Reg01h[2]b.PDBlock Reg01h[3]c.CPBlock Reg01h[4]d.ReferencePathBuffer Reg01h[5]e.VCOPathbuffer Reg01h[6]f.DigitalI/OTestpads Reg01h[7]

ToturnofftheVCORFbufferbutleavetheVCOrunningandthePLLlockedwriteReg05h=D88h.To

re-enabletheRFbufferwriteReg05h=F88h.PriortoprogramminganewfrequencysetReg05h[6:0]=0.

1.15 Chip IdentificationPLLsubsystemversioninformationmaybereadbyreadingthecontentofreadonlyregister,chip_IDinReg00h.ItisnotpossibletoreadtheVCOsubsystemversion.

1.16 General Purpose Output (GPO) Pin ThePLLsharestheLD_SDO(Lock-Detect/SerialDataOut)pintoperformvariousfunctions.WhilethepinismostcommonlyusedtoreadbackregistersfromchipviatheSPI,itisalsocapableofexportingavarietyofinterestingsignalsandrealtimetestwaveforms(includingLockDetect).Itisdrivenbyatri-stateCMOSdriverwith~200ΩRout.Ithaslogicassociatedwithittodynamicallyselectwhetherthedriverisenabled,andtodecidewhichdatatoexportfromthechip.

In its default configuration, after power-on-reset, the output driver is disabled, and only drives duringappropriatelyaddressedSPIreads.Thisallowsittosharetheoutputwithotherdevicesonthesamebus.

DependingontheSPImode,thereadsectionofSPIcycleisrecognizeddifferently

HMCSPIMode:Thedriverisenabledduringthelast24bitsofSPIREADcycle(notduringwritecycles).

OpenSPIMode:Thedriverisenabledifthechipisaddressed-ie.Thelast3bitsofSPIcycle=



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‘000’bbeforetherisingedgeofSEN(NoteA).

Tomonitoranyof theGPOsignals, includingLockDetect,setReg0Fh[7]=1 tokeep theSDOdriveralwayson.ThisstopstheLDOdriverfromtri-statingandmeansthattheSDOlinecannotbesharedwithotherdevices.

ThechipwillnaturallyswitchawayfromtheGPOdataandexporttheSDOduringanSPIread(NoteB).Topreventthisautomaticdataselection,andalwaysselecttheGPOsignal,set“PreventAutoMuxofSDO”(Reg0Fh[6]=1).Thephasenoiseperformanceatthisoutputispooranduncharacterized.Also,theGPOoutputshouldnotbetogglingduringnormaloperation.Otherwisethespectralperformancemaydegrade.

Notethatthereareadditionalcontrolsavailable,whichmaybehelpfulifsharingthebuswithotherdevices:

• Toallowthedrivertobeactive(subjecttotheconditionsabove)evenwhenthechipisdisabled-setReg01h[7]=0.

• Todisablethedrivercompletely,setReg08h[5]=0(ittakesprecedenceoverallelse).

• Todisableeither thepull-uporpull-downsectionsof thedriver,Reg0Fh[8]=1orReg0Fh[9]=1respectively.

Note A: If SEN rises before SCK has clocked in an ‘invalid’ (non-zero) chip -address, the HMC833LP6GE will start to drive the bus.

Note B: In Open Mode, the active portion of the read is defined between the 1st SCK rising edge after SEN, to the next rising edge of SEN.

ExampleScenarios:

• DriveSDOduringreads,tri-stateotherwise(toallowbus-sharing)• Noactionrequired.

• DriveSDOduringreads,LockDetectotherwise• SetGPOSelectReg0Fh[4:0]=‘00001’(whichisdefault)• Set“PreventGPOdriverdisable”(Reg0Fh[7]=1)

• AlwaysdriveLockDetect• Set“PreventAutoMuxofSDO”Reg0Fh[6]=1• SetGPOSelectReg0Fh[4:0]=00001(whichisdefault)• Set“PreventGPOdriverdisable”(Reg0Fh[7]=1))

ThesignalsavailableontheGPOareselectedbychanging“GPOSelect”,Reg0Fh[4:0].

1.17 SERIAL PORT

1.17.1 Serial Port Modes of OperationTheHMC833LP6GEserialportinterfacecanoperateintwodifferentmodesofoperation.

a.HMCSPIHMCMode(HMCLegacyMode)-SingleslaveperHMCSPIBus

b.HMCSPIOpenMode-Upto8slavesperHMCSPIBus.

BothModessupport5-bitsof registeraddressspace.HMCModecansupportup to6bitsof registeraddress.

Register 0 has a dedicated function in eachmode. OpenMode allows wider compatibility with othermanufacturersSPIprotocols.



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Table 4. Register 0 Comparison - Single vs Multi-User ModesSingle UserHMC Mode

Multi-UserOpen Mode

READChipID24-bits

ChipID24-bits

WRITESoftReset,

GeneralStrobes

ReadAddress[4:0]Softreset[5]

GeneralStrobes[23:6]

1.17.2 HMCSPI Protocol Decision after Power-On ResetOnpowerupbothtypesofmodesareactiveandlistening.

AdecisiontoselectthedesiredSPIprotocolismadeonthefirstoccurrenceofSENorSCLKfollowingahardreset,afterwhichtheprotocolisfixedandonlychangeablebycyclingthepowerOFFandON.

a.IfarisingedgeonSENisdetectedfirstHMCModeisselected.b.IfarisingedgeonSCLKisdetectedfirstOpenmodeisselected.

1.17.3 Serial Port HMC Mode - Single PLLHMCMode(LegacyMode)serialportoperationcanonlyaddressandtalktoasinglePLL,andiscompatiblewithmostHittitePLLsandPLLswithIntegratedVCOs.

TheHMCModeprotocol,showninfiguresFigure45andFigure46,isdesignedfora4wireinterfacewithafixedprotocolfeaturing

a.1Read/Writebitb.6Addressbitsc.24databitsd.3wireforWriteonly,4wireforRead/Writecapability

1.17.3.1 HMC Mode - Serial Port WRITE OperationAVDD=DVDD=3V±10%,AGND=DGND=0V

Table 5. SPI HMC Mode - Write Timing CharacteristicsParameter Conditions Min. Typ. Max Units

t1 SENtoSCLKsetuptime 8 ns

t2 SDItoSCLKsetuptime 3 ns

t3 SCLKtoSDIholdtime 3 ns

t4 SENlowduration 20 ns

t5 SCKtoSENfall 10 ns

MaxSerialportClockSpeed 50 MHz

AtypicalHMCModeWRITEcycleisshowninFigure45.

a. TheMaster(host)bothassertsSEN(SerialPortEnable)andclearsSDItoindicateaWRITEcycle,followedbyarisingedgeofSCK.

b. Theslave(synthesizer)readsSDIonthe1strisingedgeofSCKafterSEN.SDIlowindicatesaWritecycle(/WR).

c. HostplacesthesixaddressbitsonthenextsixfallingedgesofSCK,MSBfirst.d. SlaveshiftstheaddressbitsinthenextsixrisingedgesofSCK(2-7).e. Hostplacesthe24databitsonthenext24fallingedgesofSCK,MSBfirst.f. Slaveshiftsthedatabitsonthenext24risingedgesofSCK(8-31).g. Thedataisregisteredintothechiponthe32ndrisingedgeofSCK.h. SENisclearedafteraminimumdelayoft5.Thiscompletesthewritecycle.



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Figure 45. HMC Mode - Serial Port Timing Diagram - WRITE

1.17.3.2 HMC Mode - Serial Port READ OperationAtypicalHMCModeREADcycleisshowninFigure46.

a.TheMaster(host)assertsbothSEN(SerialPortEnable)andSDItoindicateaREADcycle,followedbyarisingedgeSCLK.Note:TheLockDetect(LD)functionisusuallymultiplexedontotheLD_SDOpin.ItissuggestedthatLDonlybeconsideredvalidwhenSENislow.InfactLDwillnottoggleuntilthefirstactivedatabittogglesonLD_SDO,andwillberestoredimmediatelyafterthetrailingedgeoftheLSBofserialdataoutasshowninFigure46.

b.Theslave(HMC833LP6GE)readsSDIonthe1strisingedgeofSCLKafterSEN.SDIhighinitiatestheREADcycle(RD)

c.HostplacesthesixaddressbitsonthenextsixfallingedgesofSCLK,MSBfirst.

d.SlaveregisterstheaddressbitsonthenextsixrisingedgesofSCLK(2-7).

e.SlaveswitchesfromLockDetectandplacestherequested24databitsonSD_LDOonthenext24risingedgesofSCK(8-31),MSBfirst.

f.Hostregistersthedatabitsonthenext24fallingedgesofSCK(8-31).

g.SlaverestoresLockDetectonthe32ndrisingedgeofSCK.

h.De-assertionofSENcompletesthecycle

Table 6. SPI HMC Mode - Read Timing CharacteristicsParameter Conditions Min. Typ. Max Units

t1 SENtoSCLKsetuptime 8 ns

t2 SDItoSCLKsetuptime 3 ns

t3 SCLKtoSDIholdtime 3 ns


t5 SCLKtoSDOdelay8.2ns+0.2

ns/pFns

t6 RecoveryTime 10 ns



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Figure 46. HMC Mode - Serial Port Timing Diagram - READ

1.17.4 Serial Port Open ModeTheSerialPortOpenMode,showninFigure47andFigure48,features:

a.Compatibilitywithgeneralserialportprotocolsthatuseshiftandstrobeapproachtocommunication

b.CompatiblewithHittitePLLwithIntegratedVCOsolutions,usefultoaddressmultiplechipsofvarioustypesfromasingleserialportbus.

TheOpenModeprotocolhasthefollowinggeneralfeatures:

a.3-bitchipaddress,canaddressupto8devicesconnectedtotheserialbus

b.Widecompatibilitywithmultipleprotocolsfrommultiplevendors

c.SimultaneousWrite/ReadduringtheSPIcycle

d.5-bitaddressspace

e.3wireforWriteOnlycapability,4wireforRead/Writecapability

HittitePLLswith integratedVCOs supportOpenMode.Some legacyPLL andmicrowavePLLswithintegratedVCOsonlysupportHMCMode.Consulttherelevantdatasheetsfordetails.

TypicalserialportoperationcanberunwithSCLKatspeedsupto50MHz.

1.17.4.1 Open Mode - Serial Port WRITE OperationAVDD=DVDD=3V±10%,AGND=DGND=0V

Table 7. SPI Open Mode - WRITE Timing CharacteristicsParameter Conditions Min. Typ. Max Units

t1 SDIsetuptimetoSCLKRisingEdge 3 ns

t2 SCLKRisingEdgetoSDIholdtime 3 ns


t4 SENhighduration 10 ns

t5 SCLK32RisingEdgetoSENRisingEdge 10 ns

t6 RecoveryTime 20 ns

MaxSerialportClockSpeed 50 MHz



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AtypicalWRITEcycleisshowninFigure47.

a.TheMaster(host)places24-bitdata,d23:d0,MSBfirst,onSDIonthefirst24fallingedgesofSCLK.

b.theslave(HMC833LP6GE)shiftsindataonSDIonthefirst24risingedgesofSCLK

c.Masterplaces5-bitregisteraddresstobewrittento,r4:r0,MSBfirst,onthenext5fallingedgesofSCLK(25-29)

d.Slaveshiftstheregisterbitsonthenext5risingedgesofSCLK(25-29).

e.Masterplaces3-bitchipaddress,a2:a0,MSBfirst,onthenext3fallingedgesofSCLK(30-32).Hittitereserveschipaddressa2:a0=000forallRFPLLwithIntegratedVCOs.

f. Slaveshiftsthechipaddressbitsonthenext3risingedgesofSCLK(30-32).

g.MasterassertsSENafterthe32ndrisingedgeofSCLK.

h.SlaveregisterstheSDIdataontherisingedgeofSEN.

Figure 47. Open Mode - Serial Port Timing Diagram - WRITE

1.17.4.2 Open Mode - Serial Port READ OperationAtypicalREADcycleisshowninFigure48.

Ingeneral, inOpenModetheLD_SDOlineisalwaysactiveduringtheWRITEcycle.DuringanyOpenModeSPIcycleLD_SDOwillcontainthedatafromthecurrentaddresswritteninReg0h[4:0].IfReg0h[4:0]isnotchangedthenthesamedatawillalwaysbepresentonLD_SDOwhenanOpenModecycleisinprogress.IfitisdesiredtoREADfromaspecificaddress,itisnecessaryinthefirstSPIcycletowritethedesiredaddresstoReg0h[4:0],theninthenextSPIcyclethedesireddatawillbeavailableonLD_SDO.

AnexampleoftheOpenModetwocycleproceduretoreadfromanyrandomaddressisasfollows:

a.TheMaster(host),onthefirst24fallingedgesofSCLKplaces24-bitdata,d23:d0,MSBfirst,onSDIasshowninFigure48.d23:d5shouldbesettozero.d4:d0=addressoftheregistertobeREADonthenextcycle.

b.theslave(HMC833LP6GE)shiftsindataonSDIonthefirst24risingedgesofSCLK

c.Masterplaces5-bitregisteraddress,r4:r0,(theREADADDRESSregister),MSBfirst,onthenext5fallingedgesofSCLK(25-29).r4:r0=00000.

d.Slaveshiftstheregisterbitsonthenext5risingedgesofSCLK(25-29).

e.Masterplaces3-bitchipaddress,a2:a0,MSBfirst,onthenext3fallingedgesofSCLK(30-32)..Chipaddressisalways000forRFPLLwithIntegratedVCOs.

f. Slaveshiftsthechipaddressbitsonthenext3risingedgesofSCLK(30-32).

g. MasterassertsSENafterthe32ndrisingedgeofSCLK.



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h.SlaveregisterstheSDIdataontherisingedgeofSEN.

i. MasterclearsSENtocompletethetheaddresstransferofthetwopartREADcycle.

j. Ifonedoesnotwishtowritedatatothechipatthesametimeaswedothesecondcycle,thenitisrecommendedtosimplyrewritethesamecontentsonSDItoRegisterzeroontheREADbackpartofthecycle.

k. MasterplacesthesameSDIdataasthepreviouscycleonthenext32fallingedgesofSCLK.

l. Slave(HMC833LP6GE)shiftstheSDIdataonthenext32risingedgesofSCLK.

m.Slaveplacesthedesiredreaddata(ie.datafromtheaddressspecifiedinReg00h[4:0]ofthefirstcycle) on LD_SDOwhich automatically switches to SDOmode from LDmode, disabling the LDoutput.

n.MasterassertsSENafterthe32ndrisingedgeofSCKtocompletethecycleandrevertbacktoLockDetectonLD_SDO.

Table 8. SPI Open Mode - Read Timing CharacteristicsParameter Conditions Min. Typ. Max Units

t1 SDIsetuptimetoSCLKRisingEdge 3 ns

t2 SCLKRisingEdgetoSDIholdtime 3 ns


t4 SENhighduration 10 ns

t5 SCLKRisingEdgetoSDOtime 8.2ns+0.2ns/pF ns

t6 RecoveryTIme 10 ns

t7 SCK32RisingEdgetoSENRisingEdge 10 ns



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1.17.4.3 HMCSPI Open Mode READ Operation - 2 Cycles

Figure 48. Serial Port Timing Diagram - READFormoreinformationonusingtheGPOpinwhileinSPIOpenModepleaseseesection1.16.

1.18 Configuration at Start-UpToconfigurethePLLafterpowerup,followtheinstructionsbelow:

1. Configurethereferencedivider(writetoReg02h),ifrequired.

2. Configurethedelta-sigmamodulator(writetoReg06h).



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• Configuration involvesselecting themodeof thedelta-sigmamodulator (ModeAorModeB),selectionofthedelta-sigmamodulatorseedvalue,andconfigurationofthedelta-sigmamodulatorclockscheme. It is recommended touse thevalues found in theHittitePLLevaluationboardcontrolsoftwareregisterfiles.

3. Configurethechargepumpcurrentandchargepumpoffsetcurrent(writetoReg09h)

4. Configure theVCOSubsystem (write toReg05h, formore informationseesection1.19,and “3.0VCOSubsystemRegisterMap”.DetailedwritestotheVCOsubsystemviaPLLReg05hatstart-upareavailableintheRegisterSettingFilesfoundintheHIttitePLLEvaluationSoftwarereceivedwithaproductevaluationkitordownloadedfromwww.hittite.com.

5. Programthefrequencyofoperation• Programtheintegerpart(writetoReg03h)• Programthefractionalpart(writetoReg04h)

6. Configure the VCO output divider/doubler, if needed in the VCO subsystem via PLL Reg 05h.

Once the HMC833LP6GE is configured after startup, in most cases the user only needs to changefrequenciesbywritingtoReg03hintegerregister,Reg04hfractionalregister,andReg05htochangetheVCOoutputdividerordoublersettingifneeded,andpossiblyadjustthechargepumpsettingsbywritingtoReg09h.

Fordetailedandmostup-to-datestart-upconfigurationpleaserefertotheappropriateRegisterSettingFilesfoundintheHIttitePLLEvaluationSoftwarereceivedwithaproductevaluationkitordownloadedfromwww.hittite.com.

1.19 VCO Serial Port Interface (SPI)TheHMC833LP6GEcommunicateswith the internalVCOsubsystemviaan internal16bitVCOSerialPort,(e.g.seeFigure29).TheinternalserialportisusedtocontrolthesteptunedVCOandotherVCOsubsystemfunctions,suchasRFoutputdivider/doublercontrolandRFbufferenable.

NotethattheinternalVCOsubsystemSPI(VSPI)runsattherateoftheAutoCalFSMclock,TFSM,(section1.2.1)where theFSMclock frequency cannot be greater than 50MHz.TheVSPI clock rate is set byReg0Ah[14:13].

WritestotheVCO’scontrolregistersarehandledindirectly,viawritestoReg05hofthePLL.AwritetoPLLReg05hcausesthePLLsubsystemtoforwardthepacket,MSBfirst,acrossitsinternalseriallinktotheVCOsubsystem,whereitisinterpreted.

TheVCOserialporthasthecapabilitytocommunicatewithmultiplesubsystemsinsidetheIC.ForthisreasoneachsubsystemhasasubsystemID,Reg05h[2:0].

Eachsubsystemhasmultipleregisterstocontrolthefunctionsinternaltothesubsystem,whichmaybedifferent fromone subsystem to thenext.Henceeach subsystemhas internal register addressesbits(Reg05h[6:3])

FinallythedatarequiredtoconfigureeachregisterwithintheVCOsubsystemiscontainedinReg05h[15:7].

1.19.1 VSPI Use of Reg05hThepacketdatawritteninto,Reg05hissub-parsedbylogicattheVCOsubsystemintothefollowing3fields:

1. [2:0]-3bits-VCO_ID,targetsubsystemaddress=000b.

2. [6:3]-4bits-VCO_REGADDR,theinternalregisteraddressinsidetheVCOsubsystem.

3. [15:7]-9-bits-VCO_DATA,datafieldtowriteintotheVCOregister.

Forexample,towrite0_1111_1110intoregister2oftheVCOsubsystem(VCO_ID=‘000’b),andsetthe



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VCOoutputdividertodivideby62,thefollowingneedstobewrittentoReg05h=’0_1111_1110,0010,000’b.

DuringAutoCal,theAutoCalcontrolleronlyupdatesthedatafieldofReg05h.TheVCOsubsystemregisteraddress(Reg05h[6:3])mustbesetto0000fortheAutoCaldatatobesenttothecorrectaddress.

VCO subsystem ID and register address are notmodified by the AutoCal statemachine. Hence, if amanualaccess isdone toaVCOSubsystemregister theusermust reset the registeraddress tozerobeforeachangeoffrequencywhichwillre-runAutoCal.

Since every write to Reg 05h will result in a transfer of data to the VCO subsystem, if the VCOsubsystemneeds to be resetmanually, it is important tomake sure that theVCOswitch settings arenot changed. Hence the switch settings in Reg 10h[7:0] need to be read first, and then rewritten toReg05h[15:8].

Insummary,firstreadReg10h,thenwritetoReg05hasfollows:

Reg10h[7:0] =vvxyyyyy

Reg05h =vvxyyyyy00000iii

Reg05h[2:0] =iii,subsystemID,3bits(000)

Reg05h[6:3] =0000,subsystemregisteraddress

Reg05h[7] =0,calibrationtunevoltageoff

Reg05h[12:8] =yyyyy,VCOcaps

Reg05h[13] =x,don’tcare

Reg05h[15:14] =vv,VCOSelect



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2.0 PLL Register Map

2.1 Reg 00h ID Register (Read Only)Bit Type Name Width Default Description

[23:0] RO chip_ID 24 A7975 HMC833LP6GEchipID

2.2 Reg 00h Open Mode Read Address/RST Strobe Register (Write Only)Bit Type Name Width Default Description

[4:0] WO ReadAddress 5 -(WRITEONLY)ReadAddressfornextcycle-OpenModeOnly

[5] WO SoftReset 1 -SoftReset-bothSPImodesreset(setto0forproperoperation)

[23:6] WO NotDefined 18 - NotDefined(setto0forproperoperation)

2.3 Reg 01h RST Register (Default000002h)

Bit Type Name Width Default Description

[0] R/W rst_chipen_pin_select 1 0

1=takePLLenableviaCENpin,seePowerDownModedescription

0=takePLLenableviaSPI(rst_chipen_from_spi)Reg01[1]

[1] R/W rst_chipen_from_spi 1 1 SPI’sPLLenablebit

[2] R/W Keep_bias_on 1 0whenPLLisdisabled,keepsinternalbiasgeneratorson,ignoreschipenablecontrol.

[3] R/W Keep_PD_on 1 0whenPLLisdisabled,keepsPDcircuiton,ignoresChipenablecontrol

[4] R/W Keep_CP_on 1 0whenPLLisdisabled,keepsChargePumpon,ignoresChipenablecontrol

[5] R/W Keep_Ref_buf_on 1 0whenPLLisdisabled,keepsReferencebufferblockon,ignoresChipenablecontrol

[6] R/W Keep_VCO_on 1 0whenPLLisdisabled,keepsVCOdividerbufferon,ignoresChipenablecontrol

[7] R/W Keep_GPO_driver_on 1 0whenPLLisdisabled,keepsGPOoutputDriverOn,ignoresChipenablecontrol

[8] R/W Reserved 1 0 Reserved

[9] R/W Reserved 1 0 Reserved

2.4 Reg 02h REFDIV Register (Default000001h)


[13:0] R/W rdiv 14 1

ReferenceDivider’R’Value“(EQ13)”)DividerusealsorequiresrefBufEnReg08[3]=1andDividermin1dmax16383d



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2.5 Reg 03h Frequency Register - Integer Part (Default000019h)


[18:0] R/W intg 19 25d

VCODividerIntegerpart,usedinallmodes,see(EQ13)

FractionalModemin20dmax219-4=7FFFCh=524,284d

IntegerModemin16dmax219-1=7FFFFh=524,287d

2.6 Reg 04h Frequency Register - Fractional Part (Default000000h)


[23:0] R/W frac 24 0

VCODividerFractionalpart(24-bitunsigned)seeFractionalFrequencyTuning

UsedinFractionalModeonly(Nfrac=Reg04h/224

min0dmax224-1

2.7 Reg 05h VCO SPI Register (Default000000h)


[2:0] R/W VCOSubsystem_ID, 3 0 InternalVCOSubsystemID

[6:3] R/W VCOSubsystemregisteraddress 4 0 ForinterfacingwiththeVCOpleaseseesection1.19.

[15:7] R/W VCOSubsystemdata 9 0

Note: Reg05h is a special register used for indirect addressing of the VCO subsystem.Writes to Reg05h areautomaticallyforwardedtotheVCOsubsystembytheVCOSPIstatemachinecontroller.

Reg05hisaRead-Writeregister.However,Reg05honlyholdsthecontentsofthelasttransfertotheVCOsubsystem.HenceitisnotpossibletoreadthefullcontentsoftheVCOsubsystem.OnlythecontentofthelasttransfertotheVCOsubsystemcanberead.PleasetakenotespecialconsiderationsforAutoCalrelatedtoReg05h



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2.8 Reg 06h SD CFG Register (Default200B4Ah)


[1:0] R/W seed 2 2

SelectstheSeedinFractionalMode00:0seed01:lsbseed02:B29D08hseed03:50F1CDhseedNote;WritestothisregisterarestoredintheHMC833LP6GEandareonlyloadedintothemodulatorwhenafrequencychangeisexecutedandifAutoSeedReg06h[8] =1

[3:2] R/W order 2 2

SelecttheModulatorType0:1storder1:2ndorder2:ModeBRecommended3:ModeA

[6:4] R/W Reserved 3 4 Programto4d

[7] R/W frac_bypass 1 0

0:UseModulator,RequiredforFractionalMode,

1:BypassModulator,RequiredforIntegerMode

Note:Inbypassfractionalmodulatoroutputisignored,butfractionalmodulatorcontinuestobeclockediffrac_rstb =1,CanbeusedtotesttheisolationofthedigitalfractionalmodulatorfromtheVCOoutputinintegermode

[8] R/W AutoSeed 1 11:loadstheseedwheneverthefracregisteriswritten0:whenfracregisterwritechangesfrequency,modulatorstartswithpreviouscontents

[9] R/W clkrq_refdiv_sel 1 1

selectsthemodulatorclocksource-forTestOnly1:VCOdividerclock(Recommendedfornormaloperation)0:RefdividerclockIgnoredifbits[10]or[21]areset

[10] R/W SDModulatorClkSelect 1 0 Program1

[11] R/W SDEnable 1 1

0:disablefraccore,useforIntegerModeorIntegerModewithCSP1:EnableFracCore,requiredforFractionalMode,orIntegerisolationtestingThisregistercontrolswhetherAutoCalstartsonanIntegeroraFractionalwrite

[12] R/W Reserved 1 0


[15:14] R/W Reserved 2 0

[17:16] R/W Reserved 2 0 Programto3d

[18] R/W BISTEnable 1 0 EnableBuiltinSelfTest

[20:19] R/W RDivBISTCycles 2 0

RDivBISTCycles00:103201:204710:307111:4095

[21] R/W auto_clock_config 1 1 Program0




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2.9 Reg 07h Lock Detect Register (Default00014Dh)


[2:0] R/W lkd_wincnt_max 3 5d

lockdetectwindowsetsthenumberofconsecutivecountsofdividedVCOthatmustlandinsidetheLockDetectWindowtodeclareLOCK0:51:322:963:2564:5125:20486:81927:65535

[3] R/W EnableInternalLockDetect 1 1 seesection1.16

[5:4] R/W Reserved 2 0 Reserved

[6] R/W LockDetectWindowtype 1 1LockDetectionWindowTimerSelection1:Digitalprogrammabletimer0:Analogoneshot,nominal10nswindow

[9:7] R/W LDDigitalWindowduration 3 2

0LockDetection-DigitalWindowDuration0:1/2cycle1:1cycle2:2cycles3:4cycles4:8cycles5:16cycles6:32cycles7:64cycles

[11:10] R/W LDDigitalTimerFreqControl 2 0LockDetectDigitalTimerFrequencyControl“00”fastest“11”slowest

[12] R/W LDTimerTestMode 1 01:forceTimerClockONContinuously-ForTestOnly0:NormalTimeroperation-oneshot

[13] R/W AutoRelock-OneTry 1 01:AttemptstorelockifLockDetectfailsforanyreasonOnlytriesonce.



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2.10 Reg 08h Analog EN Register (DefaultC1BEFFh)


[0] R/W bias_en 1 1 Enablesmainchipbiasreference.Program1

[1] R/W cp_en 1 1 chargepumpenable.Program1

[2] R/W PD_en 1 1 PDenable.Program1

[3] R/W refbuf_en 1 1 Referencepathbufferenable.Program1

[4] R/W vcobuf_en 1 1 VCOpathRFbufferenable.Program1

[5] R/W gpo_pad_en 1 1

0-PinLD_SDOdisabled

1-andRegFh[7]=1,PinLD_SDOisalwaysonrequiredforuseofGPOport

1-andRegFh[7]=0SPILDO_SPIisoffifunmatchedchipaddressisseenontheSPI,allowingasharedSPIwithothercompatibleparts

[6] R/W reserved 1 1 Program1

[7] R/W VCO_Div_Clk_to_dig_en 1 1 Program1


[9] R/W PrescalerClockenable 1 1 Program1

[10] R/WVCOBufferandPrescalerBiasEnable

1 1 Program1

[11] R/WChargePumpInternalOpampenable

1 1 Program1

[14:12] R/W reserved 3 011 Program011

[17:15] R/W reserved 3 011 Program011

[18] R/W spare 1 0 Don’tcare



[21] R/W HighFrequencyReference 1 0 Program1forRefin>=200MHz,0<200MHz

[22] R/W reserved 1 1 Don’tcare

[23] R/W reserved 1 1 Don’tcare



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2.11 Reg 09h Charge Pump Register(Default403264h)


[6:0] R/W CPDNGain 7100d64h

ChargePumpDNGainControl20µA√stepAffectsfractionalphasenoiseandlockdetectsettings0d=0µA1d=20µA2d=40µA...127d=2.54mA

[13:7] R/W CPUPGain 7100d64h

ChargePumpUPGainControl20µAperstepAffectsfractionalphasenoiseandlockdetectsettings0d=0µA1d=20µA2d=40µA...127d=2.54mA

[20:14] R/W OffsetMagnitude 7 0

ChargePumpOffsetControl5µA/stepAffectsfractionalphasenoiseandlockdetectsettings0d=0µA1d=5µA2d=10µA...127d=635µA

[21] R/W OffsetUPenable 1 0 recommendedsetting=0

[22] R/W OffsetDNenable 1 1 recommendedsetting=1inFractionalMode,0otherwise

[23] R/W HiKcp 1 0 HiKcpHighCurrentChargePump



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2.12 Reg 0Ah VCO AutoCal Configuration Register (Default002205h)


[2:0] R/W VtuneResolution 3 5

RDividerCycles0-11-22-43-84-325-646-128typicalconfiguration7-256

[5:3] R/W VCOCurveAdjustment 3 0

Program000VCOCurveAdjustmentvsTempforAutoCal0-Disabled1:+1Curve2:+2Curves3:+3Curves4:-4Curves5:-3Curves6:-2Curves7:-1Curve

[7:6] R/W WaitStateSetUp 2 0

Program01

WaitStateSetup100TFSMseesection1.2.4

Tmmt=1measurementcycleofAutoCal0:WaitOnlyatStartup

1:WaitonstartupandafterfirstTmmtcycle

2:WaitonstartupandafterfirsttwoTmmtcycles

3:WaitonstartupandafterfirstthreeTmmtcycles

[9:8] R/W NumofSARBItsinVCO 2 2

NumberofSARbitsinVCO0:8Recommended1:7Donotuse2:6Donotuse3:5Donotuse

[10] R/W ForceCurve 1 0 Program0

[11] R/W BypassVCOTuning 1 0 Program0fornormaloperationusingautocalibration

[12] R/W NoVSPITrigger 1 0Program0fornormaloperation.If1,serialtransfersto

VCOsub-system(viaReg05h)aredisabled

[14:13] R/W FSM/VSPIClockSelect 2 1

SettheAutoCalFSMandVSPIClock(50MHzmaximum)0:InputCrystalReference1:InputCrystalReference/42:InputCrystalReference/163:InputCrystalReference/32

[15] R/W XtalFallingEdgeforFSM 1 0Program0fornormaloperation.Program1onlyforBISTuse

[16] R/W ForceRDividerBypass 1 0 Program0



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2.13 Reg 0Bh PD Register (DefaultF8061h)


[2:0] R/W PD_del_sel 3 1 SetsPDresetpathdelay(Recommendedsetting001)

[3] R/W ShortPDInputs 1 0Program0fornormaloperation.ShortstheinputsofthePhasefrequencydetector-TestOnly

[4] R/W pd_phase_sel 1 0 Program0fornormaloperation.InvertsPDpolaritywhen1.

[5] R/W PD_up_en 1 1 EnablesthePDUPoutput

[6] R/W PD_dn_en 1 1 EnablesthePDDNoutput

[8:7] R/W CSPMode 2 0

CycleSlipPreventionModeExtracurrentisdrivenintotheloopfilterwhenthephaseerrorislargerthan:0:Disabled1:5.4ns2:14.4ns3:24.1nsThisdelayvariesby+-10%withtemperature,and+-12%withprocess.

[9] R/W ForceCPUP 1 0 ForcesCPUPoutputon-UseforTestonly

[10] R/W ForceCPDN 1 0 ForcesCPDNoutputon-UseforTestonly

[11] R/W ForceCPMIdRail 1 0 ForceCPMIdRail-UseforTestonly

[14:12] R/W Reserved 3 0 Programto100

[16:15] R/W CPInternalOpAmpBias 2 3 programto11

[18:17] R/W MCounterClockGating 2 3

Program11MCounterClockGating0:MCounterOff1:N<1282:N<10233:AllClocksON(Recommendedsetting11)

[19] R/W Spare 1 1 Don’tcare

[21:20] R/W reserved 2 0 programto00

[23:22] R/W reserved 2 0 programto00

2.14 Reg 0Ch Exact Frequency Mode Register (Default000000h)


[13:0] R/W NumberofChannelsperFpd 14 0

ComparisonFrequencydividedbytheCorrectionRate,Mustbeaninteger.Frequenciesatexactlythecorrectionratewillhavezerofrequencyerror.0:Disabled1:Disabled2:16383d(3FFFh)



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2.15 Reg 0Fh GPO_SPI_RDIV Register (Default000001h)


[4:0] R/W gpo_select 5 1d

SignalselectedhereisoutputtoSDOpinwhenenabled

0:DatafromReg0F[5]1:LockDetectOutput2.LockDetectTrigger3:LockDetectWindowOutput4:RingOscTest5.PullupHardfromCSP6.PullDNhardfromCSP7.Reserved8:ReferenceBufferOutput9:RefDividerOutput10:VCOdividerOutput11.ModulatorClockfromVCOdivider12.AuxiliaryClock13.AuxSPIClock14.AuxSPIEnable15.AuxSPIDataOut16.PDDN17.PDUP18.SD3ClockDelay19.SD3CoreClock20.AutoStrobeIntegerWrite21.AutostrobeFracWrite22.AutostrobeAuxSPI23.SPILatchEnable24.VCODividerSyncReset25.SeedLoadStrobe26.-29NotUsed30.SPIOutputBufferEn31.SoftRSTB

[5] R/W GPOTestData 1 0 1-GPOTestData

[6] R/W PreventAutomuxSDO 1 01-OutputsGPOdataonly0-AutomuxesbetweenSDOandGPOdata

[7] R/W LDODriverAlwaysOn 1 01-LD_SDOPinDriveralwayson0-LD_SDOPindriveronlyonduringSPIreadcycle

[8] R/W DisablePFET 1 0 programto0

[9] R/W DisableNFET 1 0 programto0



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2.16 Reg 10h VCO Tune Register (Default000020h)


[7:0] RO VCOSwitchSetting 8 32d

ReadOnlyRegister.IndicatestheVCOswitchsettingselectedbytheAutoCalstatemachinetoyieldthenearestfreerunningVCOfrequencytothedesiredoperatingfrequency.NotvalidwhenReg10h[8]=1,AutoCalBusy.NoteifamanualchangeisdonetotheVCOswitchsettingsthisregisterwillnotindicatethecurrentVCOswitchposition.0=highestfrequency1=2ndhighest...256=lowestfrequencyNote:VCOsubsystemsmaynotusealltheMSBs,inwhichcasetheunusedbitsaredon’tcare

[8] RO AutoCalBusy 1 0BusywhenAutoCalstatemachineissearchingforthenearestswitchsettingtotherequestedfrequency.

2.17 Reg 11h SAR Register (Default7FFFFh)


[18:0] RO SARErrorMagCounts 19 219-1 SARErrorMagnitudeCounts

[19] RO SARErrorSign 1 0 SARErrorSign0=+ve1=-ve

2.18 Reg 12h GPO2 Register (Default000000h)


[0] RO GPO 1 0 GPOState

[1] RO LockDetect 1 0LockDetectStatus1=Locked0=Unlocked

2.19 Reg 13h BIST Register (Default1259h)


[15:0] RO BISTSignature 19 4697d BISTSignature

[16] RO BISTBusy 1 0 BISTBusy



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3.0 VCO Subsystem Register MapPleasenotethattheVCOsubsystemusesindirectaddressingviaReg05h.FormoredetailedinformationonhowtowritetotheVCOsubsystempleaseseesection“1.19VCOSerialPortInterface(SPI)”.

3.1 VCO_Reg 00h TuningBit Type Name Width Default Description

[0] WO Cal 1 0VCOtunevoltageisredirectedtoatemperaturecompensatedcalibrationvoltage

[8:1] WO CAPS 8 16d

VCOsub-bandselection.0-maxfrequency11111111-minfrequency.Notallsub-bandsareusedonthevariousproducts.

3.2 VCO_Reg 01h EnablesBit Type Name Width Default Description

[0] WO MasterEnableVCOSubsystem 1 1

0-AllVCOsubsystemblocksOffManualmode(VCO_Reg03h[2]=1)

1-ANDedwithlocalenablesonlyAutoMode(VCO_Reg03h[2]=0)

1-Masterenableignoreslocalenables

[1] WO ManualModePLLbufferenable 1 1 EnablesPLLBufferinmanualmodeonly

[2] WO ManualModeRFbufferenable 1 1 EnablesRFBuffertoOutputinmanualmodeonly

[3] WO ManualModeDivideby1enable 1 1 EnablesRFdivideby1inmanualmodeonly

[4] WO ManualModeRFDividerenable 1 1 EnablesRFdividerinmanualmodeonly

[8:5] WO don’tcare 4 0 don’tcare

Forexample,toturndisabletheRFbufferintheVCOsubsystemandmutetheoutputoftheHMC833LP6GE,bit2inVCO_Reg01hneedstobecleared.Iftheotherbitsareleftunchanged,then‘000011011’needstobewrittenintoVCOReg01h.TheVCOsubsystemregisterisaccessedviaawritetoPLLsubsystemReg05h=‘0000110110001000’=D88h

Reg05h[2:0]=000;VCOsubsystemID0Reg05h[6:3]=0001;VCOsubsystemregisteraddressReg05h[7]=1;MasterenableReg05h[8]=1;PLLbufferenableReg05h[9]=0;DisableRFbufferReg05h[10]=1;Divideby1enableReg05h[11]=1;RFDividerenableReg05h[16:12]=0;don’tcare



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3.3 VCO_Reg 02h BiasesBit Type Name Width Default Description

[5:0] WO RFDivideratio 6 1

0-Mute,VCOandPLLbufferOn,RFoutputstagesOff1-Fo2-Fo/23-invalid,defaultsto24-Fo/45-invalid,defaultsto46-Fo/6...60-Fo/6061-invalid,defaultsto6062-Fo/62>62-invalid,defaultsto62Note:Thisregisterautomaticallycontrolstheenablestothe,RFoutputbuffer,RFdivider,RFdivideby1path,andrequiresMasterEnable(VCO_Reg01h[0]=1)andAutoRFOmode(VCO_Reg03h[2]=0)Note:bit[0]isadon’tcareinManualRFOmode.

[7:6] WO RFoutputbuffergaincontrol 2 3

11-MaxGain10-MaxGain-3dB01-MaxGain-6dB00-MaxGain-9dB

[8] WO Divideroutputstagegaincontrol 1 0

1-MaxGain0-MaxGain-3dBUsedtoflattentheoutputpowerlevelacrossfrequency•Fordivide-by1ordivide-by2itisrecommendedtosetthisbitto1.0willreduceoutputpoweranddegradenoisefloorperformance.

•Fordivide-by4orhigher,itisrecommendedtosetthisbitto0tomaintainflatoutputpoweracrossdividersettings.Settingthisbitto1,withdivide-by4orhigherprovideshigheroutputpowercomparedtothedivide-by1or2case.

Forexample,towrite0_1111_1110intoVCO_Reg02hVCOsubsystem(VCO_ID=‘000’b),andsettheVCOoutputdividertodivideby62,thefollowingneedstobewrittentoReg05h=’0_1111_1110,0010,000’b.

Reg05h[2:0]=00;subsystemID0Reg05h[6:3]=0010;VCOregisteraddress2dReg05h[16:7]=0_1111_1110;Divideby62,maxoutputRFgain,Divideroutputstagegain=0

3.4 VCO_Reg 03h ConfigBit Type Name Width Default Description

[0] WOFundamental/DoublerModeSelection

1 10-Enablethefrequencydoublermodeofoperation1-Enablefundamentalmodeofoperation-Formoreinformationpleasesee“VCOSubsystem”section.

[1] WO reserved 1 0 reserved

[2] WO ManualRFOMode 1 0

0-AutoRFOmode(recommended)1-ManualRFOmodeAutoRFOmodecontrolsoutputbuffersandRFdivider

enablesaccordingtoRFdividersettingin“VCO_Reg02hBiases”[5:0]ManualRFOmoderequiresmanualenablesofindividualblocksviaVCO_Reg01h

[4:3] WO RFbufferbias 2 2

Programto‘10’bforoutputfrequencies<=3000MHz(whenVCO_Reg03h[0]=1).Programto‘00’bforoutputfrequencies>3000MHz(whenVCO_Reg03h[0]=0)



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3.4 VCO_Reg 03h ConfigBit Type Name Width Default Description

[8:5] WO Spare 4 2 don’tcare

3.5 VCO_Reg 04h Cal/BiasSpecifiedperformanceisonlyguaranteedwiththerequiredsettingsinthistable.Othersettingsarenotsupported.


[2:0] WO VCObias 3 1 Programto1d

[4:3] WO PLLbufferbias 2 1 Programto0d

[6:5] WO FndLmtrbias 2 2 Programto2d

[8:7] WO PresetCal0 2 1 Programto1d

3.6 VCO_Reg05h CF_CalBit Type Name Width Default Description

[1:0] WO CFL 2 2 Programto0d

[3:2] WO CFML 2 2 Programto3d

[5:4] WO CFMH 2 2 Programto2d

[7:6] WO CFH 2 2 Programto0d

[8] WO Spare 1 0 Programto0d

3.7 VCO_Reg06h MSB CalBit Type Name Width Default Description

[1:0] WO MSBL 2 3 Programto3d

[3:2] WO MSBML 2 3 Programto3d

[5:4] WO MSBMH 2 3 Programto3d

[7:6] WO MSBH 2 3 Programto3d

[8] WO Spare 1 0 don’tcare



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NOTES:



hmc833lp6ge · 2019-06-05 · 25 mhz to 6000 mhz. the integrated phase detector (pd) and...

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