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Homework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L = 20um/0.35um, n = 4 Size W/L to set the overdrive voltage of M1-M4 and M6 to roughly 100mV. Set n as 3, since the threshold voltage is 490mV, the Vgs of M1-M4 and M6 should be around 590mV. DC simulation result is shown below. In order to make sure that transistor M1-M4 and M6 have the overdrive voltage of approximately 0.1V, the width of transistor has been selected as 20um. 2) Sweep n and determine what (integer) value of n works best. The plot of X, Y, Z is shown below.

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Page 1: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

Homework 4 Solutions

Problem 1

1) Circuit schematic is shown as the problem.

W/L = 20um/0.35um, n = 4

Size W/L to set the overdrive voltage of M1-M4 and M6 to roughly

100mV. Set n as 3, since the threshold voltage is 490mV, the Vgs of

M1-M4 and M6 should be around 590mV. DC simulation result is

shown below.

In order to make sure that transistor M1-M4 and M6 have the

overdrive voltage of approximately 0.1V, the width of transistor has

been selected as 20um.

2) Sweep n and determine what (integer) value of n works best.

The plot of X, Y, Z is shown below.

Page 2: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

The plot of M1 overdrive voltage is shown below.

n = 4 is a good choice for the circuit. Firstly, increasing n, the voltage

of node X, Y and Z will increase, making the transistors more

saturated. Then, n = 4 makes the overdrive voltage of M1 closer to

Page 3: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

0.1V. If n is larger than 4, the voltage of node X will be high, reducing

the output voltage headroom. (Note that, it is also reasonable to

choose n = 3.)

3) Perform .op analysis, the small-signal parameters of M1 and M2

are shown below.

Small-signal parameters of M1

gds = 83.02u

gm = 1.168m

region = 2

vds = 200m

vgs = 593.6m

vth = 490.3m

Small-signal parameters of M2

gds = 21.93u

gm = 1.255m

region = 2

vds = 800m

vgs = 578.2m

vth = 490.1m

Small-signal parameters of M3

gds = 90.42u

gm = 1.157m

region = 2

Page 4: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

vds = 192.6m

vgs = 593.6m

vth = 490.3m

Small-signal parameters of M4

gds = 30.18u

gm = 1.225m

region = 2

vds = 401m

vgs = 585.6m

vth = 490.2m

Small-signal parameters of M5

gds = 238.7u

gm = 458.9u

region = 1

vds = 196.5m

vgs = 778.2m

vth = 490m

Small-signal parameters of M6

gds = 24.45u

gm = 1.24m

region = 2

vds = 581.7m

vgs = 581.7m

Page 5: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

vth = 490.2m

4) Calculate the Ro of M1 and M2 branch

1 2 2 1 2o o o m o oR r r g r r

where gds1 = 83.02u, gds2 = 90.42u, gm2 = 1.157m.

Therefore, Ro = 746.3kΩ.

5) To test the output resistance Ro, the AC input signal with 1V

magnitude is injected into the output of current mirror, and the current

flowing out of the AC voltage source is shown below.

So, the output impedance is, Ro = 1/1.339u = 746.3kΩ, which is the

same as the hand calculation, and both of them are close to gmro2.

6) Plot of Io vs. Vo

Page 6: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

Plot of Ro vs. Vo

Page 7: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

For region 1, the output voltage is between 0 and Vov, M1 and M2

both work at the linear region, the output impedance is very low, and

the output current is small. Here, the upper voltage limit for region 1 is

approximately 0.18V.

For region 2, the output voltage is between Vov to 2Vov, M1 goes into

the saturation region, and M2 still works in the linear region. The

voltage range for region 2 is from 0.18V to 0.36V.

For region 3, the output voltage is larger than 2Vov, M1 and M2 both

are in the saturation region, the output current and output resistance

increase quickly. Here, the lower voltage limit for region 3 is 0.36V.

Note that, Vov could change with varying the output voltage Vo.

7) Sweep the value of IB from 50uA to 200uA in 10uA step increment.

Plot of the voltage of nodes X, Y and Z and the overdrive voltage of

M1 is shown below.

Page 8: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

Based on the simulation results, the biasing condition of high-swing

cascode structure could almost linearly track the master current

variation.

8) Connect the bulk of transistors M2, M4 and M6 to ground, the plot

of the voltage of node X, Y, Z is shown below.

Compared with the simulation results in 7), it could be found that the

body effect does not have the effects of the high-swing cascode

current mirror.

Problem 2

1. “Fractional” band-gap reference (BGR) circuit is shown below.

Page 9: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

1) Derive a closed-form expression for the BGR output, VOUT. The

voltage across R1 is,

1 1 2 lnR BE BE TV V V V n

Where n = 8. So, the current flowing through R1 is,

11 2 1

1 1

lnR TR

V V nI I I

R R

The current flowing through R2 is,

12

2

BER

VI

R

Since M1, M2 and M3 have the same aspect ratio, the current flowing

through M3 should be,

2

2

1

1

ln lnT Tout R R

V n V nI I I

R R

Then, output voltage is,

Page 10: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

13 3

1 2

lnT BEout out

V n VV I R R

R R

2) Determine the ratios of R3/R1 and R2/R1 to produce a 0.5V

temperature independent VOUT.

Output voltage is,

3 21

2 1

lnout T BE

R RV V n V

R R

Where n = 8, VBE1 = 0.7V, VT = 25mV.

The factor M is,

2

1

ln 23.5R

M nR

So,

2

1

11.30R

R

Besides,

3 21

2 1

ln 0.5out T BE

R RV V n V

R R

3

2

0.388R

R

So,

3 3 2

1 2 1

4.38R R R

R R R

Page 11: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

3) Consider the finite r0 effect of M1, M2 and M3. Suppose the R1 =

1kΩ and ro = 0.1MΩ, determine the numerical value of VOUT.

The current flowing through M1, M2 and M3 is,

11 2 3 1 2

1 2

lnT BED D D R R

V n VI I I I I

R R

Where R1 = 1kΩ, R2 = 11.3 kΩ, n = 8.

So,

11 2 3

1 2

ln0.114T BE

D D D

V n VI I I mA

R R

Considering the channel-length modulation, for a single MOS

transistor,

1o

D

rI

10.088

o Dr I

For M1, M2 and M3, the current determined by VGS should be the

same. Assume that,

2

,

1

2GSD V p ox GS THI c V V

Therefore, for M1,

1 , 1 0.114GSD D V DSI I V mA

Where |VDS|=1.8V.

Then,

, 0.098GSD VI mA

Page 12: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

For M3,

,

3

[1 (V )]GS

OUTD V DD OUT

VI V

R

Where R3 = 4.38kΩ.

Therefore, considering the finite ro effect, output voltage is,

0.505OUTV V

4) Explain intuitively how the two feedback loops formed by the op-

amp and the left and right arms of the VT-reference circuit can be

stable.

Based on the schematic show above, the loop from node X to node Y

is the positive feedback for the op-amp, and the loop from node X to

node Z is the negative feedback for the op-amp.

For the positive feedback, the magnitude of gain is,

Page 13: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

, , 1 2

, 1

1| A | g (R || )V pos m M

m Qg

Where, gm,M1 is the transconductance of M1, gm,Q1 is the

transconductance of Q1.

For the negative feedback, the magnitude of gain is,

, , 2 2 1

, 1

1| A | g (R || ( R ))V neg m M

m Qg

Where gm,M1=gm,M2, gm,Q1=gm,Q2.

Therefore, the negative feedback gain is larger than the positive

feedback, which could make sure that the system could be stable. In

this analysis, R1 is critical.

2. Brokaw band-gap reference circuit is shown below.

1) Derive a closed-form expression for the BGR output, VOUT.

Page 14: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

The voltage across R1 is,

1 1 2 lnR BE BE TV V V V N

Where N = 16.

So, the current flowing through R1 is,

11 2 1

1 1

lnR TR

V V NI I I

R R

The current flowing through R2 is,

2 1

1

2 lnN2 T

R R

VI I

R

Then, output voltage is,

22 2 1 1

1

2 lnout R BE BE T

R NV I R V V V

R

If M = 23.5, then,

2

1

2 ln23.5

R NM

R

Therefore,

2

1

4.24R

R

2) Still ignore ∆R but include VOS, re-derive the expression for Vout.

Page 15: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

Considering the input offset voltage VOS of op-amp, the current

flowing through Q2 is,

11

1

DD X RV V VI

R R

And the current flowing through Q1 is,

2 1DD X OS OSV V V V

I IR R

Then, the voltage across R1 is,

21 1 2

1

ln( ) ln( )DD X OSR BE BE T T

DD X

V V VIV V V V N V N

I V V

Therefore, the output voltage is,

2 21 2 1 2 1

1

2ln( )DD X OS

out BE BE T OS

DD X

V V VR RV V R I I V V N V

R V V R

Page 16: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

1

2

ln DD X OSBE T

S

V V VV V

RI

Where, IS2 is the saturation current for bipolar transistor Q1.

Then,

2 1 21 2 /outT

OS DD X OS

V R R RV

V V V V R

In order to minimize the dependence of VOUT on VOS, the ratio of R2/R

should be minimized, and the ratio of R2/R1 is determined by the M

factor to achieve the temperature-independent output voltage.

Besides, the voltage VX should be reduced.

3) Include both ∆R and VOS, re-derive the expression for VOUT.

Considering the input offset voltage VOS of op-amp and ∆R, the

current flowing through Q2 is,

11

1

DD X RV V VI

R R

And the current flowing through Q1 is, (assume that ∆R/R<<1)

12 1

DD X OS OS OSV V V I R V VI I

R R R R R R

Then, the voltage across R1 is,

21 1 2

1

ln ln DD X OSR BE BE T T

DD X

V V VI RV V V V N V N

I V V R R

Therefore, the output voltage is, (assume that ∆R/R<<1)

Page 17: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

1 2 1 2

2 21

1

2 21

1

( )

2ln( )

2ln( )

out BE

DD X OSBE T OS

DD X

DD X OSBE T OS

DD X

V V R I I

V V VR RRV V N V

R V V R R R R

V V VR RV V N V

R V V R R

1

2

1ln( )DD X OS

BE T

S

V V VV V

R R I

Where, Is2 is the saturation current for bipolar transistor Q1.

4) Explain intuitively how the two feedback loops formed by the op-

amp and the left and right arms of the VT-reference circuit can be

stable.

The loop form node X to node Y is the positive feedback for the op-

amp, and the loop from node X to node Z is the negative feedback.

Page 18: Homework 4 Solutions Problem 1 - The University of …yxc101000/courses/6326/homework/hw4_soln.pdfHomework 4 Solutions Problem 1 1) Circuit schematic is shown as the problem. W/L =

Ignore the early effect, and assume that β>>1, for the positive

feedback, the magnitude of the gain is,

, 2

,

, 2 1 2

| A |1 (R )

m Q

V pos

m Q

g R

g R

For the negative feedback, the magnitude of the gain is,

, 1

,

, 1 2

| A |1

m Q

V neg

m Q

g R

g R

Assume that, the current flowing through Q1 and Q2 is the same,

then gm,Q1 = gm,Q2, therefore, the magnitude of negative feedback gain

is larger than that of positive feedback gain, and the system is stable.

R1 is critical to make sure that the system is stable, since it could

reduce the positive feedback gain with emitter degeneration.