Ch.7 - Exercises Solutions

Q.1Why might we choose to employ a CT filter inside a modulator loop rather than a DT filter? Briefly discuss your statements.

Solution:See Table 7.6 in the book. Further, some other reasons may include:

A typical DT-modulator has a maximum clock rate limited both by opamp bandwidths and by the fact that circuit waveforms need several time constants (i.e. clock period) to settle. For a modulator built in a process with maximum transistor speed f T , the maximum clock rate of a switched-capacitor modulator is on the order of f T /100. By contrast, waveforms vary continuously in a CT-modulator, and the restriction on opamp bandwidths are relaxed. In theory, a CT-modulator could be clocked up to an order of magnitude faster in the same technology without much performance penalty.

In a DT-modulator, large glitches appear on opamp virtual ground nodes due to switching transients. This is not the case in a CT-modulator: opamp virtual grounds can be kept very quiet.

One problem with working in the DT domain is aliasing: signals separated by a multiple of the sampling frequency are indistinguishable. DT Σ∆-modulators usually require a separate filter at their inputs to attenuate aliases sufficiently. By contrast, CT-modulators have free anti-aliasing properties.

Perhaps the major reason for the prevalence of DT Σ∆-modulators is that there is a natural allegory between the mathematics of the system and its circuit-level implementation. Fundamentally, Σ∆-modulators rely on having at least one integrator inside the loop; in the DT domain, we must usually construct a circuit to give us the 1/(z – 1) integrating function. It happens that there exist certain devices (i.e. like accelerometers and fluxgate magnetic sensors, etc.) which behave as physical continuous-time integrators - they implement a 1/s function. Circuits have been built which use these devices as the first stage of a Σ∆-modulator. Thinking in the CT domain, therefore, allows us to realize compact converters outside the voltage/current domain (i.e. time domain - see Chapter 10).

Q.2Design a second order CIFB modulator having an OSR = 64, single-bit quantizer and a frequency band of operation of 16 KHz. Simulate the modulator in Simulink®.

Solution:Run the code in the folder - 0_Exercises ->ch7 - named - Q2_MakeMod. Note that the student should develop a similar code. Open the - sweep_testbench - model and load the - Q2_mod3 - model into the - Modulator - block. Select the sinewave input by typing - simu.select = 2 -

into the Matlab Command Window and run the simulation in Simulink®. Type - mod_SNDR - into the Matlab Command Window to obtain the SNR and make sure that the results are in accordance to what given by the - Q2_MakeMod - code which uses the Schreier's Toolbox. The results should report an SNR around 80 to 83 dB.

Q.3Using the design of Q.2, simulate the effects of jitter using an NRZ DAC in Simulink®. Discuss the results.

Solution:Noting that the modulator of Q.2 already uses an NRZ DAC, it is sufficient to insert the - NRZ_DAC - model found in the folder - 7_CT_MOD - into the feedback loop of the CIFB modulator, similarly to the model - Q3_NRZ_DAC_mod3 - provided in the - 0_Exercises ->ch7 - folder. By inserting a small amount of jitter (e.g. 100ps, 50 ps, etc.) it should be noted that the SNR decreases and the noise floor increases, as a consequence of inserting jitter as an additive white noise source.

Q.4Using Simulink®, check that the - RZ_DAC - model found in the folder - 7_CT_MOD - provides an RZ pulse. What can be said about the input and output of the model in relation to the RZ pulse (i.e. Hint: enter into the model to inspect the blocks arrangement)? What are the advantages and disadvantages of using such feedback DAC pulse type?

Solution:To verify the pulse of the - RZ_DAC - model, a similar model to the one provided in the folder - 0_Exercises ->ch7 - named - Q4_RZ_DAC - should be developed. Running the Simulink® model - RZ_DAC_Q2 - and inspecting the scope, the clock signal and the RZ DAC pulse can be seen to behave as expected from theory.

Regarding the input of the RZ_DAC model it should be noted that the gain block of the input data is set to 2 in order to obtain an output that is twice the one of an NRZ pulse. This because the RZ waveform output value has to be doubled (i.e. considering a 50% duty cycle) to supply the same amount of charge of the respective NRZ pulse, due to the fact that the RZ pulse is shorter compared to the NRZ one.

Except for the function of immunity to excess loop delay, RZ DAC pulse also suppresses inter-symbol interference problems caused by non-symmetrical DAC pulse edge time. However, using a RZ DAC pulse would increase the power consumption and the DAC speed would be decreased since DAC outputs must return to zero every clock period.

Q.5Using the design of Q.2, simulate the effects of jitter using an RZ DAC in Simulink®. Discuss the results.

Solution:Noting that the modulator of Q.2 does not use an RZ DAC, the line 37 of the code - Q2_MakeMod - should be changed to - [0 0.5]. Once changed, the code should be run to design the new version of the CIFB modulator which implements an RZ feedback DAC pulse. The next step is to develop a Simulink® model similar to - Q4_RZ_DAC_mod3 - provided in the folder - 0_Exercises ->ch7. Running the simulation of the Simulink® model and inspecting the SNR should provide similar results to what previously found with NRZ pulses, which is an SNR of approximately 80 dB.

Q.6Discuss the advantages and disadvantages of the gmC, Active-gmC and Active-RC integrators.

Solution:See paragraph 7.4 in the main text.

gmC Active-gmC Active-RC

Frequency Range Highest High HighTunability High High LowMismatch Insensitivity High Medium LowLinearity Low High HighestDynamic Range Medium Low HighPower Consumption Low High HighLow Voltage Applicability Low Medium High

Q.7Explain the phenomenon of Excess Loop Delay. Why Excess Loop Delay is problematic only in CT ΣΔ-modulators although it exists also in DT designs?

Solution:Ideally, the DAC in the feedback loop of CT ΣΔ-modulators responds immediately to the quantizer clock edge. However, a finite delay between the quantizer and the DAC occurs due to the non-zero transistor switching time of the quantizer. ELD refers to the non-zero delay between the quantizer clock edge and the edge of the DAC pulse. Assuming that the ELD can be expressed by:

τ D=ρDT s

shown in Fig. 7.4 in the main text of the book for an ideal NRZ DAC pulse. The ELD τ D depends on the switching speed f Tof the transistors, quantizer clock frequency f s, the number of transistors in the system feedback loop ni, and the loads on each transistor. For a rough approximation, we can assume that all transistors switch after 1/ f T , which is:

ρD=ni f s

f T

Excess loop delay exits in both DT and CT ΣΔ-modulators. It is only problematic in CT-modulators because these timing errors are accumulated continuously by the integrator through the DAC in the feedback loop. ELD imposes a real problem by changing the value of α and β. In other words, excess loop delay can affect the equivalence of H(z) and H(s).

Q.8Considering a high-order modulator with a sampling period T s=163 μs, OSR = 150, and a resolution of 16-bit find the maximum asymmetry allowed in the feedback DAC pulse to avoid ISI.

Solution:The first thing is to find the achievable SNR for a 16-bit system, such as:

SNR=6.02∗ENOB+1.76≈ 98dB

Having the desired SNR, the formula presented in paragraph 7.5.2 can be applied, such as:

τ ≤4T s√OSRSN Rdesired

=4 ∙0.000163 ∙√150

10(9820 )

≈100 ps

Q.9In order to design ΣΔ-modulators using Continuous Time blocks in Simulink®, it is necessary to transform the DT Transfer Function into a Continuous Time one (i.e. note that the coefficients derived by the Schreier's Toolbox with the method discussed would not always work with Continuous Time blocks!). One method mentioned in the book is the Impulse Invariant Transform. Assuming an ideal NRZ feedback DAC pulse is used, the shape of the DAC pulse is perfectly a rectangular pulse of magnitude 1 that lasts from α to β:

rD={1 , α ≤ t ≤ β ,0≤α≤β ≤10 , otherwise

Using Laplace transform, the equation above can be expressed as:

R(α , β )=exp (−αs )−exp (−βs)

s

(7.6)

(7.7)

What is found is a z-domain pole of multiplicity l at zk which maps to one at sk with the same multiplicity, such as:

sk=ln zk

(this makes sense when you think of z=exp (sT s)). Poles at dc (i.e., zk=1) end up giving 0l /0 l as the numerator of the s-domain equivalent, which necessitates l applications of l’Hôpital’s rule; this has been done in the right column of Table 7.7.

For a second-order low-pass design of a DT ΣΔ-ADCs, the NTF ( z )=( z−1 )2 such as:

H ( z )=−2 z+1( z−1 )2

To obtain the CT equivalent, H(z) is written as a partial fraction expansion first, such as:

H ( z )= −2z−1

+ −1( z−1 )2

Thus zk=1, which means sk=0 from Eq.7.8. Applying the first row of Table 7.7 to the first term of Eq.7.10 and the second row to the second term with (α ,β )= (0,1 )gives:

−2s

+−1+0.5 ss2~H (s )=−1+1.5 ss2

Where in a CIFB second-order modulator the first term refers to the feedback gain connecting at the modulator's input, while the term 1.5 to the feedback gain after the first integrator. Having H(s), design and simulate the second-order, 1-bit CIFB modulator in Simulink® using only CT-blocks.

(i.e. Hint: to achieve correct scaling in Simulink®, use a gain block prior to the Continuous Time integrators with a gain of F s)

Table 7.7 s-domain Equivalences for z-domain Loop Filter Poles

(7.8)

(7.9)

(7.10)

(7.11)

Solution:The Simulink® model can be found in the folder -

0_Exercises->ch7 - named - Q9_CT_mod2. To simulate the model type - load_par - into the Matlab Command Window and ensure the setting suggested in paragraph 7.7.1 are set. Running the simulation and inspecting the Time Scope and - mod_SNDR - results should illustrate that the model is able to convert signals according to what expected from the theory of a second order modulator, achieving an SNDR of approximately 73 dB.

Q.10As discussed in paragraph 7.5, there are some advantages of using a return-to-zero DAC pulse in low-pass modulators. These DACs produce a rectangular pulse which lasts from 0 to T s /2 only. Starting from the double integration modulator of Eq.7.9, find the CT-equivalent applying Table 7.7 with (α ,β )= (0,0.5 ). Explain your results.

Solution:

Lim

it fo

r s-

dom

ain

equi

vale

ntz-

dom

ain

pole

Write Eq.7.9 as a partial fraction expansion as Eq.7.10. Then Table 7.7 is applied to get:

H s=−4s

+−1+1.5 ss2

=−2+2.5 ss2

The numerator coefficients are larger than what found in Eq.7.11 for NRZ pulses, which makes sense intuitively because in order to get the same quantizer input voltage with a shorter DAC pulse larger integrator gains are required.Q.11A CT double integration modulator as in Q.8 is being design but the NRZ feedback pulse is effected by excess loop delay, such as (α ,β )=τd ,1+τ D¿. Using Table 7.8, what is the equivalent H (z ) for such an H (s) and DAC pulse?

Hint: The formulae in Table 7.8 only apply for a pulse with β≤1, but note that by using superposition it is possible to write a τ d-delayed NRZ pulse as:

r ( τ D ,1+τD ) ( t )=r ( τD ,1 ) ( t )+ r (0 , τ D ) ( t−1 )

that is, as a linear combination of a DAC pulse from τ d to 1 and a one sampled-delayed DAC pulse from 0 to τ d.

Table 7.8 z-domain Equivalences for s-domain Loop Filter Poles

(7.12)

Lim

it fo

r z-

dom

ain

equi

vale

nts-

dom

ain

pole

Solution:Writing the CT double integrator H (s) in partial fractions gives:

H (s )=−1.5s

∙−1s2

Applying Table 7.8 to each term of the two DAC pulses in 7.12, gives:

−1.5s

→−1.5(1−τ D)

z−1+z−1−1.5 τD

z−1

−1s2

→(−0.5+τ D−0.5 τD

2 ) z+0.5(−1+τ D2 )

( z−1 )2+z−1 τ D (−1+0.5 τ D ) z−0.5 τ D

2

( z−1 )2

Adding the two equations above yields:

H ( z , τD )=(−2+2.5 τ D−0.5 τ D

2 ) z2+(1−4 τ D+τD2 ) z+(1.5 τD−0.5 τ D

2 )

z (z−1 )2

it can be easily verified that for zero-delay (i.e. τ D=0) results:

H ( z )=−2 z+1( z−1 )2

as it should.

Q.12Briefly state the main advantages and disadvantages of the Continuous-Time and Discrete-Time ΣΔ-implementations.

Solution:CONTINUOUS TIME DISCRETE TIME

Sampling Frequency Potentially higher operation speed achievable

Lower

Power Consumption Lower Higher

Anti-Aliasing Not required - Inherent for narrow-band applications

Required before the ADC

Sampling Error Shaped by the loop filter Appear directly at ADC output

Clock Jitter Sensitive to clock jitter in feedback DAC

Robust to clock jitter

Loop Delay Sensitive Very little effect

Mismatch Sensitivity High - need additional calibration circuitry

Low - as they rely on precise capacitor ratios

CMOS Compatibility Low High

Simulation/Prototype Difficult / Easy to prototype Easy / Difficult to prototype

Other Advantages SNR not limited by capacitor size

Reduced op-amp speed requirements

Reduced impact from supply and ground noise

Less glitch and switching noise

Accurate transfer function as pole-zero locations is set by accurate capacitor ratios

Switched Capacitor integrator highly linear

Only capacitive loads

Other Disadvantages Requires accurate RC time constants

Require highly linear op-amps

Large capacitors for high SNR required

Q.13Briefly state the main non-idealities affecting Continuous-Time ΣΔ-implementations as wwll as their effect and common counteraction used to limit their effects.

Solution:NON-IDEALITY EFFECT

Integrators Finite, non-linear DC Gain Noise floor and distortion

Integrator Time-Constant error Stability and noise floor

Integration Incomplete Transient Response

Noise floor and distortion

Circuit Element tolerances Stability, signal amplitude, noise floor and distortion

Flicker (1/f) and Thermal Noise Noise

Quantizer Meta-Stability and hysteresis Signal amplitude, noise floor and distortion

Feedback DAC

Delay (ELD) Stability, signal amplitude, noise floor and distortion

Inter-Symbol Interference (ISI)

Non-linearity (i.e. multibit, etc.)

Clock Jitter Noise and signal skirt

NON-IDEALITY IMPACTS SOLUTION

Overload More Noise Distortion Unstable System

Limited Input Range Time Constant Scaling Multi-Bit Quantizer Reset Circuitry

Excess Loop Delay

More Noise Unstable System

Use Simple Circuits (e.g. 1-Bit Quantizer, no DEM, etc.)

Use RZ DAC Use Compensation Techniques

Clock Jitter More Noise Accurate Clock Source Multi-Bit Quantizer Jitter Insensitive DAC Pulse

Shapes Jitter Insensitive ΣΔ-

Architectures (e.g. Hybrid, etc.)

Unequal DAC Rise/Fall Time

More Noise Distortion

Use RZ/HRZ DAC Pulses Differential Circuitry

Amplifier Finite Gain/GBW

More Noise Distortion

Design Amplifier With Enough Gain and GBW

Amplifier Finite Slew Rate

More Noise Design Amplifier With Enough Slew Rate

Distortion

Time Constant Variation

Unstable System Poorer Performance

Trimming Resistance/Capacitance Tuning

Quantizer Hysteresis

More Noise Reset Circuitry