How to use virtuoso for SOI logic simulation w/ hospice

(Example for making inverter)

Manabu Togawa

1

Make work directory and copy setup files

• Make work directory and change directory to that. • Copy following files to your work directory from /usr2/lapislib-2014/

soi020_kek_LAPIS_Semi_ic61/ • .cdsPCskill • .cdsenv • .cdsinit • .simrc • cds.lib • -display.drf • object.map • streamIn.template • streamOut.template

• Modify following line in cds.lib • DEFINE PC_020umSOI_KEK [pass install directory of PC_020umSOI_KEK lib]

• Copy definition file of LAPISA library to your work directory. • /home/soi/togawa/1401_typ.inc

2

Environment files (@Osaka)

• Set environment by reference to, • /home/soi/.bashrc • /home/soi/Env/bashrc_cadence • /home/soi/Env/bashrc_synopsys • /home/soi/Env/bashrc_mentor • /home/soi/Env/bashrc_HyENEXSS

!• (Only cadence and synopsys are necessary to do logic simulation)

3

Running virtuoso

4

cd [work directory]; virtuoso

2 windows are popped up

Name of LAPIS library appears

Main window

Library Manager

If you do not have correct setting files in your working directory..

5

Only one window is popped up and no name of LAPIS library

Make your library directory

6

Select [File]->[New]->[Library] in Library Manager then put directory name

“test2” will be created

Open schematic view

• Clock OK, schematic windows will be popped up.7

[File]->[New]->[Cellview] in main window Change as,

Library : your library directory Cell name : library name (in this case, I will make inverter, so “inv”) Type : schematic Application : Schematics XL and check Always…

Put PMOS and NMOS in schematic window

8

1) Click “create instance” button, then component browser will be shown

2) Select library as PC_020… , check Flatten, and select pmos3 or nmos3 then Add Instance window will be popped up

3) After 2), You can see yellow colored CMOS figure following cursor when your cursor is on schematic view. Instance can be placed by left click.In Add Instance, parameters for SOI

CMOS is written. We should not change them except for special study.

Wiring

9

Push “ESC” button, then yellow CMOS will be vanished. Push “w” button start at wiring point, cursor turns on wring mode. If you want to delete the item, Push “ESC”, then push “delete”. it turns on delete mode.

Place vdd and gnd

10

Click “create instance” (page.8) and select, Library:analogLib and check Flatten. Select gnd or vdd and place it to schematic.

Place PIN (input, output)

11

Push “ESC” button and push “p” butto, then Add Pin window is popped up. Specify Direction (input, output or …) and put the name. and palace pin in the schematic view

Check and Save

12

Select [File]->[Check and Save]. If there is no errors, “Schematic check completed with errors” is shown in main window. Please fix if you have errors by reference to the error log.

Create ADE view to run hspice

13

Select [Launch]->[ADE XL], then Launch ADE (G)XL windows will be popped up. select [Create New View] and examples of parameters for ADE (G)XL are shown here. (Cell name should be same as schematic name)

In this case, ADE XL opens in tab in the schematic view window

14

Schematic view ADE view

Click “Create Test” button to set simulation parameters In Choosing Design window, push just OK Then, ADE XL Test Editor is popped up.

Check simulator

15

Just make sure simulator is selected as “hspiceD”

[Setup]->[Simulator]

Add definition of LAPIS library in simulation

16

[Setup]->[Simulation Files…] And add 1401_typ.inc file in Definition Files

Setting output

17

1) Click “Seup Outouts” button, then “Seup Outouts” windows will be shown

2) Select “From Schematic”

3) You can choose outputs by left click. In this case, I selected wiring btw in-PIN and CMOSs and wiring btw CMOSs and out-PIN. The name will be shown in “Setting Outputs” and “Test Editor” windows.

Choose analysis sequence

18

1) Click “Choose Analyses” button, then “Choosing Anakyses” windows will be shown

2) Setting parameters. In this case, analysis as function of time 0 - 100 nsec w/ 1 nsec steps

If click oh, setting is shown in Test Editor

Define parameters for input and vdd

19

[Setup]->[Stimuli]

Set input as pulse w/ following parameters

Need to check “Enables”

Define parameters for input and vdd

20

[Setup]->[Stimuli]->Click [Global Sources]

Set vdd as 3 V

Need to check “Enables”

Analysis and result

21

Click to look at ADE XL

Result is shown by double click

If everything OK, it will be shown as finished and graph appears

Run simulation

Re-open your library

22

1) Double clock adexl or schematic of your library in Library Manager

2) Double clock ****:1 in case of adexl