hs t2 14-15 cadence accelerating system level verification ... · yafitsnir arindam guha cadence...

Yafit SnirArindam GuhaCadence Design Systems, Inc.

Accelerating System level Verification of SOC Designs with MIPI Interfaces

©2017MIPIAlliance,Inc.

• Overview:MIPIVerificationapproachesandchallenges• Accelerationmethodologyoverviewandadvantages• AcceleratedverificationIPArchitecture• Migrationguidelines:fromsimulationtoacceleration• VirtualemulationusingMIPIvirtualdevicemodels• Demonstration

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CadenceDesignSystems

Agenda


Agenda


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MIPICSI-2℠&MIPIDSI℠

• Widelyadoptedserialhigh-speedprotocols.• Implementedincomplexsystems,foravarietyof

applicationsindifferentmarkets:– Mobile– Automotive– Multimedia– Virtualreality,augmentedrealityandothers

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MIPIInterfacesusageexampleinComplex/LargeSOC’sCustomer’sApplicationSpecificComponents

SoCInterconnect

ARMCPUSubsystem

3DGraphicsCore

DSPA/V

Highspeed,wiredinterfaceperipherals

LPDDR3

PHY

Storage&Memory

SAS

SD

SATA

MIPIUFS

OtherMemory

Low-speedperipheralsubsystem

MIPIhighspeedperipheralinterfaces,andother.

MIPISLIMbus®

MIPILLI℠

MIPIUniPro℠

MIPID-PHY℠

MIPIM-PHY®

I2C

JTAG

MIPICSI-2

MIPIDSI

MIPIDigRF℠

ApplicationAccelerators

…

AES

…

A15

L2cache

USB3.0

3.0PHY

2.0PHY

PCIeGen2,3

PHY

Ether-net

PHY

A15 A7

L2cache

A7

CacheCoherentFabric

Software

Furthercomplicatedbyhardware/software

interactions


SystemLevelVerificationChallenges

• ComplexandLargeDesigns.– Longsimulationtime– NeedtoreachsystemcoveragegoalspriortoRTLfreeze.

• Timetomarket:Requiresparalleldevelopmentofhardwareandsoftwaredesign,earlyindevelopmentcycle..

• Validatingsoftwareandhardwareintegration.• Createandvalidaterealworldscenariosinapre-silicon

environment.

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• PureSimulationverification– Fullcontrollabilityandcoveragecollection.– Acceptableperformanceformodule/subsystem.

• Hardwareassistedverification– EnablesHighperformanceforsubsystem/systemverification.– Enablespre-siliconHW/SWverification.– Enablesrunninglongertests,withhighthroughputtoreach

interestingsystemscenarios,andvalidateperformance.

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OverviewofCurrentverificationapproaches

©2017MIPIAlliance,Inc. 8


Overviewofhardwareassistedverificationmethods

• SimulationAcceleration– Acceleratinghardwareverification.

• VirtualEmulation– SWDrivenHWVerification,SW/HWValidation

• In-CircuitEmulation– Enablesrealdeviceconnection

• FPGAPrototyping



Block/IPVerification

Sub-system/SoCVerification

SoClevelHW/FWIntegration

SoftwareSimulation

Signal-BasedAcceleration

Transaction-BasedAcceleration

In-CircuitEmulation

SynthesizableTestbench(STB)

Performance

SoftwareSimulationEmulatorSimulator

TB

DUT

SignalBasedAccelerationEmulatorSimulator

TB

DUT

TransactionBasedAccelerationEmulatorSimulator

TB

DUT

FullSystemValidationw.AppSW

10x

100x

1,000x

10,000x

1x

VirtualEmulation

Hybrid

VirtualEmulation(usingVirtualDeviceModels)EmulatorWorkstation

VirtualDeviceModels

DUTVirtualInterface

SynthesizableTestbenchEmulatorSimulator

TB

DUT

In-CircuitEmulationEmulator

DUT

Simulator

Hybrid

EmulatorVirtualPlatform

DUTProcessorModel

EmulatorUseModes

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Agenda


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Simulationvs.Acceleration

Testbench

DesignUnder Test

Workstation

Testbench

DesignUnder Test

TBA

TBA

PROXY

BFM

Workstation Emulator

Simulation

Acceleration

DesignSize

Performance

Performancegapincreasesformorecomplexdesigns

ForsmalldesignsorIPlevelverification,simulation

performanceis“good-enough”

IP Sub-system System

Simulation-Accelerationmode• DUTrunsathigherspeedsthaningeneralpurposeCPU

• AccelerationfactordeterminedbyTBtimeandsynchronizationsbetweenTBandEmulator

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SignalBasedAcceleration• Bit-by-bitsignallevelexchangebetweentestbenchandDUT

• Performancebottleneckcanbethecommunicationchannelortestbenchtime

TransactionBasedAcceleration(TBA)• Reducescommunicationchanneloverheadfromsignalbasedtotransactionbased

• LeveragesfasthardwareforDUTexecution


CommunicationChannel

Testbench DesignUnder Test

AccelerationSignalBasedAcceleration&TransactionBasedAcceleration


TBAI/F

TBAI/F

PROXY

BFM

EmulatorWorkstation

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AcceleratedVerificationIP(AVIP)

TestbenchDesignUnder Test

TBAI/F

TBAI/F

OptimizedCore

EmulatorWorkstation

Drv

Mon

Seq

Accelerated Verification IPs optimized for performance

AVIP

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AccelerationMethodologyAdvantages

• Enablesorders-of-magnitudegainsinthroughputoverSimulation• Enablesreusingselectedpartsofyoursimulationverification

environment• Enablesadvancedtechnologieswithvirtualemulation,like:

– HybridoperationforoptimalpartitionofthedesignbetweenHWandSWtoachievemaximumspeedup

– ConnectiontoVirtualDevices,Virtualmachines,etc.

• EnablesOS-levelbenchmarksanddriverbring-up

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Agenda


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ArchitectureofAcceleratedVerificationIP(AVIP)Host (SW)

Emulator (HW)

SW Proxy

AccelerationOptimizedCore

DUT

Transactionsend/receivechannels

control/statuschannel

memrd/wrchannels

UserAPI(C/CPP/TLM2/UVM-SV)

FunctionsCallBacks

Optimizetransfertypesusingvariousstandardsforsimulator/emulator

communication.

Dynamic batching/reactive user controltooptimizeperformance

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Agenda


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©2017MIPIAlliance,Inc. 18


OptimizingAccelerationperformance Color Legend % of time spent in testbench

% of time spent in DUT% of time spent in channel

Signal Based AccelerationWith DUT running in HW

Introduces channel overhead

SimulationTB DUT

• Profile simulation runs to identify acceleration candidates

• Select runs that are long & spend large amount of time in DUT

• Quickest path to acceleration• Maximize re-use of testbench

• Increase acceleration factor• Reduce communication overhead• Transactor may need modeling effort

Transaction Based AccelerationWith optimized channelTB

Transaction Based AccelerationWith optimized testbench

• Optimize testbench by removing verification redundancies from IP-level -stimulus generation.

• High level of acceleration• Focus on sub-system & system level

verification

Testbench optimization

Hig

her a

ccel

erat

ion

perfo

rman

ce

TB CH


AccelerationFriendlyUVC(attheSimulationStage)

SVInterfaceAgent

BFMWrapper

VirtualInterface BFM

SWDomain SWDomain

DUT

CLK

SVInterface

BFM DUT

CLK

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AccelerationReady– UVC(attheEmulationStage)

Agent

Data(DPI-C)

Events

Callbacks

SWDomain HWDomain

ProxyTasks

SVInterface

SynthesizableBFM DUT

CLK

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Agenda


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Workstation

DSIVirtualDevice

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Emulator

SOC Design

DSI Host Controller

Frame buffer

SW stack/drivers

GPUImage

processor

DSI AVIP BFM

DSI AVIP SW Proxy

DSI AVIP DSI Virtual Device Model

DSI ModelLogic

Virtual Display

Enables you to visualize the HW/SW operation of your video/image processing subsystem in real time

DSI Virtual Device



Workstation

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Emulator

SOC Design

CSI-2 Host

Controller

Enables you to visualize the HW/SW operation of your video/image processing subsystem in real time

Frame buffer

SW stack/drivers

GPUImage

processor

CSI-2 AVIP BFM

CSI-2 AVIP SW

Proxy

CSI-2 AVIP CSI-2 Virtual Device Model

CSI-2 ModelLogic

Image filesCSI-2 Virtual Device

CSI-2VirtualDevice



VirtualDeviceModelsusageexample

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LPDDRDRAM NANDFLASH

NANDFlash

Cellularmodem

WiFi

LLI

DigRF

LPDD

R 2

eMM

C4.

5

UFS

LPDD

R 3

SD 3

.0SD

4.0

UFS

SLIMbus

DSI

CSI2CSI3

Bluetooth

SDIO3

FMreceiver

GPSreceiver

RFF

E

SLIM

bus

Motionsensors

cJTAG

GBT

SPM

I

Powercontrol

Multimediaprocessor

I2C

USB

2.0

Memorycard

HDMI 1.4

Touch screencontroller

Displaydriver

Audiointerface

Applicationsprocessor

AMBA®4 ACE™

Camerainterface

USB 3.0 OTG

AMBA AXI™, AHB™OCP 2.0

OCP 3.0SSIC Emulator Simulator

Application/firmware code running to capture image file on camera and route image to display

Image files

CSI-2VirtualDevice

CSIAVIP

CSIVirtualDeviceModel

DSIVirtualDevice

DSIAVIP

DSIVirtualDeviceModel


Agenda


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TodiscussCadenceMIPIAcceleratedVIPsavailability,Pleasecontact:[email protected]

D-PHYDSIDeviceController

C-PHY

C-PHYDSI2DeviceController

D-PHYCSI2

DeviceController

D-PHY

C-PHY

C-PHY

D-PHY

DSIHostController

DSI2HostController

CSI2HostController

I2CController I2CController

VDMCamera

SoC

VDMDisplay

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hs t2 14-15 cadence accelerating system level verification ... · yafitsnir arindam guha cadence...

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