hsdsl lab final presentation cordic implementation on fpga winter 2013-14
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HSDSL Lab final presentation CORDIC implementation on FPGA winter 2013-14. supervisor Moni Orbach. Students: Or Rotem Malachi Levi. overview. Project process: Understanding the algorithm Architecture examination Golden model – C lang Simulation environment buildup Coding - PowerPoint PPT PresentationTRANSCRIPT
HSDSL Lab
final presentation CORDIC implementation on FPGA
winter 2013-14
supervisorMoni Orbach
Students:Or Rotem Malachi Levi
overviewProject process:
Understanding the algorithmArchitecture examinationGolden model – C langSimulation environment buildup CodingSimulation Synthesis
Theory
Block diagram
לחישוב בלוקσ
התוספת סימן
לחישוב בלוקהתוצאה
לחישוב בלוקσ
התוספת סימן
לחישוב בלוקהתוצאה
compareThis block compares the current angle with
the desired oneIncrement the current angle according the
result
calculatePerform the matrix calculationUses the result from the compare block
LUTLut is Decimal at it’s source – conversion to
binary took place according to architecture needs
Simulation environment
SynthesisChip: Cyclon llSynthesizer: quartos 12.1
Synthesis issuesThe design was modified for resources
optimizationPin planner was done and led was programed
to show calculation result – counter clock
Synthesis statists
The resources usage is approx. the same as the Altera build in block
Clk frequency ~120MHz
Limited by longest path Was improved dramatically over the processThe pipeline is improving the frequency by
~30 times
System Latency is 30 clk cycles
Pipeline appearance
Usage of the cyclon2 logic and cell and registers
Cyclone 2 vs cyclone 3
Signal TapThe results was checked and found correctExpected vals came from the simulation
environmentThis is the way to test the “real” system
output
Summery & conclusionsArchitectureSimulation environmentHigh level coding not always come in one
hand with FPGAOther synthesis programs might give better
resultsimportance of clk frequency
end
Appendix – the codecalculate
Appendix – the codecompare