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C U S TO ME R E D U C A TI O N S E R V I C E S

HSPICE Advanced Topics Workshop

Student Guide 60-I-032-BSG-005 2007.03

Synopsys Customer Education Services

700 East Middlefield Road

Mountain View, California 94043

Workshop Registration: 1-800-793-3448

www.synopsys.com

Synopsys Customer Education Services

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Table of Contents

Synopsys 60-I-032-BSG-005 i HSPICE Advanced Topics

Unit i: Introduction & Overview

Introductions ..................................................................................................................... i-2

Facilities............................................................................................................................ i-3

Workshop Goal ................................................................................................................. i-4

Target Audience................................................................................................................ i-5

Agenda: Day 1................................................................................................................... i-6

Workshop Objectives: Day 1 ............................................................................................ i-7

Agenda: Day 2................................................................................................................... i-8

Workshop Objectives: Day 2 ............................................................................................ i-9

Icons Used In This Workshop......................................................................................... i-10

Unit 1: Introduction

Unit Objectives ................................................................................................................ 1-2

HSPICE Fundamentals .................................................................................................... 1-3

Files and Suffixes............................................................................................................. 1-4

Starting HSPICE .............................................................................................................. 1-5

Netlist Structure ............................................................................................................... 1-6

Netlist Structure: Overview ............................................................................................. 1-7

Netlist Structure: Topology.............................................................................................. 1-8

Node Naming Conventions (1/2) ..................................................................................... 1-9

Node Naming Conventions (2/2) ................................................................................... 1-10

Element Naming Conventions ....................................................................................... 1-11

Units and Scale Factors.................................................................................................. 1-12

.MEASURE ................................................................................................................... 1-13

.MEASURE: Rise/Fall (1/2) ......................................................................................... 1-14

.MEASURE: Rise/Fall (2/2) ......................................................................................... 1-15

.MEASURE: AVG, RMS, MIN, MAX, PP (1/2) .......................................................... 1-16

.MEASURE: AVG, RMS, MIN, MAX, PP (2/2) .......................................................... 1-17

.MEASURE: FIND-WHEN........................................................................................... 1-18

.MEASURE: FIND-WHEN Examples .......................................................................... 1-19

.MEASURE: Equation Evaluation................................................................................. 1-20

.MEASURE: Derivative Function ................................................................................. 1-21

.MEASURE: Integral Function...................................................................................... 1-22

.ALTER: Description ..................................................................................................... 1-23

.ALTER: Limitations ..................................................................................................... 1-24

.ALTER Rules (1/2)....................................................................................................... 1-25

.ALTER Rules (2/2)....................................................................................................... 1-26

.ALTER: Example ......................................................................................................... 1-27

Discovery AMS Simulation Interface Basics................................................................. 1-28

Discovery AMS Simulation Interface............................................................................ 1-29

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Synopsys 60-I-032-BSG-005 ii HSPICE Advanced Topics

Discovery AMS Simulation Interface – Project Management....................................... 1-30

Discovery AMS Simulation Interface – Project Management....................................... 1-31

Discovery AMS Simulation Interface – Setup............................................................... 1-32

Discovery AMS Simulation Interface – Netlist & Simulation....................................... 1-33

Discovery AMS Simulation Interface – Netlist & Simulation....................................... 1-34

Discovery AMS Simulation Interface – HSPICE Setup ................................................ 1-35

Discovery AMS Simulation Interface – HSPICE Setup ................................................ 1-36

Discovery AMS Simulation Interface – Run ................................................................. 1-37

Discovery AMS Simulation Interface – Run ................................................................. 1-38

Discovery AMS Simulation Interface - Output ............................................................. 1-39

Discovery AMS Simulation Interface - Simulation ....................................................... 1-40

Invoking CosmosScope.................................................................................................. 1-41

CosmosScope Basics ..................................................................................................... 1-42

CosmosScope Pulldown Menu Bar ............................................................................... 1-43

CosmosScope Icon Bar .................................................................................................. 1-44

CosmosScope Tool Bar.................................................................................................. 1-45

CosmosScope Mouse Usage .......................................................................................... 1-46

Opening a Plotfile .......................................................................................................... 1-47

CosmosScope File/Signal Control Forms...................................................................... 1-48

Scope Plotting Techniques (1/2) .................................................................................... 1-49

Scope Plotting Techniques (2/2) .................................................................................... 1-50

CosmosScope Measurements......................................................................................... 1-51



CosmosScope Calculator ............................................................................................... 1-54

Using the Calculator ...................................................................................................... 1-55

Lab 1: HSPICE............................................................................................................... 1-56

Unit 2: Verilog-A Modules

Unit Objectives ................................................................................................................ 2-2

Introduction to Verilog-A ................................................................................................ 2-3

Feature Overview (1/2) .................................................................................................... 2-4

Feature Overview (2/2) .................................................................................................... 2-5

Verilog-A Usage Overview ............................................................................................. 2-6

Loading Verilog-A Files (1/2) ........................................................................................ 2-7

Loading Verilog-A Files (2/2) ......................................................................................... 2-8

Defining the Verilog-A Module Path............................................................................... 2-9

Instantiation Syntax........................................................................................................ 2-10

Verilog-A Model Cards ................................................................................................ 2-11

Instantiation Examples (1/2) .......................................................................................... 2-12

Instantiation Examples (2/2) .......................................................................................... 2-13

Parameter Case Sensitivity............................................................................................. 2-14

Table of Contents

Synopsys 60-I-032-BSG-005 iii HSPICE Advanced Topics

Bus Support.................................................................................................................... 2-15

Output Control (1/2) ...................................................................................................... 2-16

Output Control (2/2) ...................................................................................................... 2-17

Output Control Example (1/2) ....................................................................................... 2-18

Output Control Example (2/2) ....................................................................................... 2-19

Overriding Subcircuits with Verilog-A Modules........................................................... 2-20

Disabling .option VAMODEL with .option SPMODEL............................................... 2-21

Addition Information – vamodel and spmodel .............................................................. 2-22

Stand-Alone Compiler ................................................................................................... 2-23

Verilog-A Examples .................................................................................................... 2-24

Lab 2: Verilog-A Modules ............................................................................................. 2-25

Unit 3: Simulating Variability - Design for Yield

Unit Objectives ................................................................................................................ 3-2

Wafer Yield in Nanometer Technologies ........................................................................ 3-3

Variation Components Across Wafer .............................................................................. 3-4

Variation Components From Reticle ............................................................................... 3-5

Variation Components Due To Discreteness of Atoms and Photons .............................. 3-6

Variation Components Due To Proximity: (not random) ................................................ 3-7

Quantifying Variability in Nanometer Technologies....................................................... 3-8

Contents ........................................................................................................................... 3-9

Cu Interconnect Stack Structure .................................................................................... 3-10

Random Variation in Interconnect ................................................................................. 3-11

Interconnect Variation Modeling: Current Approach .................................................... 3-12

Interconnect Variation Modeling: Statistical Extraction Flow ...................................... 3-13

Contents ......................................................................................................................... 3-14

Variation Model in HSPICE .......................................................................................... 3-15

Variation Block Overview ............................................................................................. 3-16

Variation Block Structure .............................................................................................. 3-17

Options and Common Parameters ................................................................................. 3-18

Independent Random Variables ..................................................................................... 3-19

Dependent Random Variables ....................................................................................... 3-20

Syntax for Specifying Variations ................................................................................... 3-21

Variations on Model and Element Parameters............................................................... 3-22

Simple Variation Block Example .................................................................................. 3-23

Principal Components Based Global Variation Modeling............................................. 3-24

Local Variations in Nanometer Technologies................................................................ 3-25

Spatial Variation Example ............................................................................................. 3-26

Designer’s Variation Block............................................................................................ 3-27

Variation Block Summary ............................................................................................. 3-28

Contents ......................................................................................................................... 3-29

Monte Carlo Analysis in HSPICE ................................................................................. 3-30

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Synopsys 60-I-032-BSG-005 iv HSPICE Advanced Topics

Monte Carlo Commands ................................................................................................ 3-31

Options for Monte Carlo Analysis ................................................................................. 3-32

Factorial Sampling ......................................................................................................... 3-33

One-Factor-At-a-Time Sampling................................................................................... 3-34

Latin Hypercube Sampling ............................................................................................ 3-35

Monte Carlo Analysis Flow ........................................................................................... 3-36

Monte Carlo Result Distributions .................................................................................. 3-37

Monte Carlo Convergence ............................................................................................. 3-38

Contents ......................................................................................................................... 3-39

Interpreting Results of Monte Carlo .............................................................................. 3-40

Data Mining: Pairs Plot.................................................................................................. 3-41

Data Mining: Pareto Plot ............................................................................................... 3-42

Monte Carlo Analysis Summary.................................................................................... 3-43

Contents ......................................................................................................................... 3-44

Mismatch Analysis......................................................................................................... 3-45

Mismatch........................................................................................................................ 3-46

Effects of Mismatch on DC Amplifier........................................................................... 3-47

HSPICE DCMatch Analysis Overview ......................................................................... 3-48

DCMatch Analysis Command ....................................................................................... 3-49

DCMatch Table Result Example ................................................................................... 3-50

Amplifier with Rail-to-Rail Input Range ....................................................................... 3-51

DCMatch Simulation Result .......................................................................................... 3-52

Benefits of DCMatch Analysis ...................................................................................... 3-53

HSPICE ACMatch Analysis Overview ......................................................................... 3-54

ACMatch Analysis Command ....................................................................................... 3-55

Fully Differential Amplifier........................................................................................... 3-56

Power Supply Feedthrough............................................................................................ 3-57

Benefits of ACMatch Analysis ...................................................................................... 3-58

Contents ......................................................................................................................... 3-59

Mismatch Versus Monte Carlo Analysis ....................................................................... 3-60

DCMatch and ACMatch Versus Monte Carlo............................................................... 3-61

HSPICE Documentation on Variability......................................................................... 3-62

References...................................................................................................................... 3-63

Presentation for Modeling Engineers............................................................................. 3-64

Lab 3: Simulating Variability – Design for Yield.......................................................... 3-65

Unit 4: S-Parameters and Linear Analysis

Unit Objectives ................................................................................................................ 4-2

S-Parameter Basics .......................................................................................................... 4-3

Two-Port Scattering Parameters ...................................................................................... 4-4

Linear Multi-Port Parameter Analysis ............................................................................ 4-5

Linear Characterization.................................................................................................... 4-6

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Synopsys 60-I-032-BSG-005 v HSPICE Advanced Topics

Port (P) Element............................................................................................................... 4-7

Port Element Syntax ........................................................................................................ 4-8

.LIN Analysis Syntax ....................................................................................................... 4-9

.LIN Keywords............................................................................................................... 4-10

HSPICE Linear Characterization ................................................................................... 4-11

.LIN Parameter Definitions (1/4) ................................................................................... 4-12




Introduction to Noise Analysis (1/3).............................................................................. 4-16



Noise Representation (1/2) ............................................................................................ 4-19

Noise Representation (2/2) ............................................................................................ 4-20

Noise Types (1/3)........................................................................................................... 4-21

Noise Types (2/3)........................................................................................................... 4-22

Noise Types (3/3)........................................................................................................... 4-23

Noise Calculation Example............................................................................................ 4-24

S-Element....................................................................................................................... 4-25

S-Element Syntax........................................................................................................... 4-26

S-Element Rules............................................................................................................. 4-27

S-Element Keywords (1/4)............................................................................................. 4-28





S-Parameter Model Syntax ............................................................................................ 4-33

SP Model Syntax............................................................................................................ 4-34

SP Model Keywords (1/3).............................................................................................. 4-35

SP Model Syntax (2/3)................................................................................................... 4-36

SP Model Syntax (3/3)................................................................................................... 4-37

SP Model Example ........................................................................................................ 4-38

Using S-Parameters Example ........................................................................................ 4-39

Mixed Mode S-Parameters ............................................................................................ 4-40

Mixed Mode Port Element............................................................................................. 4-41

Extracting Mixed-Mode S-Parameters (1/3).................................................................. 4-42



Mixed Mode S-Parameter Example............................................................................... 4-45

Mixed-Mode S-Parameter Example Results (1/2)......................................................... 4-46

Mixed-Mode S-Parameter Example Results (2/2)......................................................... 4-47

Using Mixed Mode S-Parameters (1/2) ......................................................................... 4-48

Using Mixed Mode S-Parameters (2/2) ......................................................................... 4-49

Lab 4: Using .LIN and S-Parameters ............................................................................. 4-50

Table of Contents

Synopsys 60-I-032-BSG-005 vi HSPICE Advanced Topics

Unit 5: Transmission Lines and Field Solver

Unit Objectives ................................................................................................................ 5-2

Introduction to Transmission Lines ................................................................................. 5-3

Transmission Lines (1/4) ................................................................................................. 5-4




Transmission Lines in HSPICE ....................................................................................... 5-8

Ideal Transmission Lines: T-Element (1/2) ..................................................................... 5-9

Ideal Transmission Lines: T-Element (2/2) ................................................................... 5-10

W-Element Transmission Line ...................................................................................... 5-11

Comparison of U vs. W-Elements ................................................................................. 5-12

W-Element ..................................................................................................................... 5-13

W-Element RLGC Matrices........................................................................................... 5-14

RLGC File...................................................................................................................... 5-15

W-Element Accepts U-Model........................................................................................ 5-16

W-Element Syntax ......................................................................................................... 5-17

W-Element Keywords.................................................................................................... 5-18

Benefits of DELAYOPT................................................................................................ 5-19

Optimal Number Of W-Element Segments ................................................................... 5-20

AC vs. TRAN Comparison At 1GHz ............................................................................ 5-21

AC vs. TRAN Comparison At 5GHz ........................................................................... 5-22

AC vs. TRAN Comparison At 20GHz .......................................................................... 5-23

Using S-Parameters in Transmission Lines ................................................................... 5-24

Using S-Parameters in W-Element Keywords............................................................... 5-25

Using S-Parameters in W-Element Syntax .................................................................... 5-26

Using S-Parameters In W-element Guidelines .............................................................. 5-27

W-Element Thermal Noise Modeling............................................................................ 5-28

Thermal Noise Model Keywords ................................................................................... 5-29

W-Element with Thermal Model Syntax ...................................................................... 5-30

Field Solver.................................................................................................................... 5-31

Filament Method............................................................................................................ 5-32

Modeling Geometry Basics............................................................................................ 5-33

What Input does the Field Solver Require? ................................................................... 5-34

.MATERIAL Definition................................................................................................. 5-35

Layerstack Rules ............................................................................................................ 5-36

.LAYERSTACK ............................................................................................................ 5-37

.SHAPE.......................................................................................................................... 5-38

.FSOPTIONS ................................................................................................................. 5-39

Field Solver .Model (1/2)............................................................................................... 5-40

Field Solver .Model (2/2)............................................................................................... 5-41

Table of Contents

Synopsys 60-I-032-BSG-005 vii HSPICE Advanced Topics

Field Solver .Model Rules (1/2)..................................................................................... 5-42

Field Solver .Model Rules (2/2)..................................................................................... 5-43

Field Solver Example..................................................................................................... 5-44

Partial Netlist for Field Solver Example........................................................................ 5-45

Modeling Coaxial Lines................................................................................................. 5-46

Coaxial Line Example.................................................................................................... 5-47

Shielded Twin Lead Example ........................................................................................ 5-48

Lab 5: Transmission Lines and Field Solver.................................................................. 5-49

Unit 6: IBIS

Unit Objectives ................................................................................................................ 6-2

What is IBIS? ................................................................................................................... 6-3

IBIS Model Characteristics .............................................................................................. 6-4

IBIS Buffers ..................................................................................................................... 6-5

IBIS Buffer Block Diagram ............................................................................................. 6-6

Buffer Output Model........................................................................................................ 6-7

IBIS Model I-V Curves (1/2) ........................................................................................... 6-8

IBIS Model I-V Curves (2/2) ........................................................................................... 6-9

IBIS I-V Curve Rules of Thumb.................................................................................... 6-10

Ramp and V-t Curve Measurements.............................................................................. 6-11

Schematic of an I/O Circuit ........................................................................................... 6-12

IBIS Buffer Basic Syntax ............................................................................................... 6-13

Supported Buffer Types and Syntax (1/2)...................................................................... 6-14

Supported Buffer Types and Syntax (2/2)...................................................................... 6-15

BUFFER Keyword......................................................................................................... 6-16

BUFFER Keyword Example.......................................................................................... 6-17

TYP Keyword ................................................................................................................ 6-18

Power On | Off ............................................................................................................... 6-19

INTERPOL and NOWARN Keywords ......................................................................... 6-20

XV_PU and XV_PD Keywords..................................................................................... 6-21

RAMP_FWF and RAMP_RWF Keywords.................................................................. 6-22

FWF_TUNE and RWF_TUNE Keywords .................................................................... 6-23

C_Comp ......................................................................................................................... 6-24

IBIS Buffer Scaling Keywords....................................................................................... 6-25

HSP_VER Keyword ...................................................................................................... 6-26

Using the .IBIS Command (1/2) .................................................................................... 6-27

.IBIS Command Syntax (2/2)......................................................................................... 6-28



.IBIS Command Examples............................................................................................. 6-31

Using the .PKG Command (1/2).................................................................................... 6-32

Using the .PKG Command (2/2).................................................................................... 6-33

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Synopsys 60-I-032-BSG-005 viii HSPICE Advanced Topics

Using the .EBD Command ............................................................................................ 6-34

.EBD Command Syntax................................................................................................. 6-35

.EBD Example ............................................................................................................... 6-36

EBD Example ................................................................................................................ 6-37

EBD Limitations ............................................................................................................ 6-38

Using the .ICM Command............................................................................................. 6-39

ICM Structure (1/2)........................................................................................................ 6-40

ICM Structure (2/2)........................................................................................................ 6-41

Additional ICM Constructs............................................................................................ 6-42

ICM Swath ..................................................................................................................... 6-43

.ICM Syntax ................................................................................................................... 6-44

.ICM Example................................................................................................................ 6-45

Multi-Lingual Model Support (1/2) ............................................................................... 6-46

Multi-Lingual Model Support (2/2) ............................................................................... 6-47

Example ......................................................................................................................... 6-48

Component Calls for [External Circuit] ........................................................................ 6-49

Name Limit Extension ................................................................................................... 6-50

Lab 6: IBIS Buffers ........................................................................................................ 6-51

Unit CS: Customer Support

Synopsys Support Resources ........................................................................................ CS-2

SolvNet Online Support Offers..................................................................................... CS-3

SolvNet Registration is Easy......................................................................................... CS-4

Support Center: AE-based Support............................................................................... CS-5

Other Technical Sources ............................................................................................... CS-6

Summary: Getting Support ........................................................................................... CS-7

Introduction & OverviewHSPICE Advanced Topics

i-1© 2007

HSPICEAdvanced Topics

Synopsys Customer Education Services© 2007 Synopsys, Inc. All Rights Reserved Synopsys 60-I-032-BSG-005

The Golden Standard for Accurate Circuit Simulation


i-2© 2007

2i-

Introductions

Name

Company

Job responsibilities

EDA experience

Main goals and expectations for this course

EDA = Electronic Design Automation


i-3© 2007

3i-

Facilities

Building Hours

Restrooms

Meals

Messages

Smoking

Recycling

Phones

Emergency EXIT

Please turn off cell phones and pagers


i-4© 2007

4i-

Workshop Goal

Enhance the student’s use of HSPICE for statistical analysis

and signal integrity applications.


i-5© 2007

5i-

Target Audience

Analog designers and engineers who

perform circuit simulation and analysis at the transistor level, and who are familiar with the basics of HSPICE.


i-6© 2007

6i-

Agenda: Day 1

Introduction1

Verilog-A Modules2

Simulating Variability – Design forYield

3

DAY

1111


i-7© 2007

7i-

Workshop Objectives: Day 1

Explain the HSPICE file structure

List the HSPICE output files

Use .MEASURE statements to verify circuit specifications

Invoke and use CosmosScope

Invoke and use the Discovery-AMS Simulation Interface

Use DCmatch analysis

Use Monte Carlo analysis


i-8© 2007

8i-

Agenda: Day 2

S-Parameters and Linear Analysis4

Transmission Lines and Field Solver5

IBIS6

DAY

2222


i-9© 2007

9i-

Workshop Objectives: Day 2

Use linear analysis to extract network parameters

Use S-parameter elements

Use W-element transmission lines

Describe how to use the S-element

Use the field solver

Explain how to use IBIS models


i-10© 2007

10i-

Lab Exercise Caution

RecommendationDefinition of

Acronyms

For Further Reference

“Under the Hood”

InformationGroup Exercise

Question

Icons Used In This Workshop

Lab Exercise: A lab is associated with this unit, module, or concept.

Recommendation: Recommendations to the students, tips, performance boost, etc.

For Further Reference: Identifies pointer or URL to other references or resources.

Under the Hood Information: Information about the internal behavior of the tool.

Caution: Warnings of common mistakes, unexpected behavior, etc.

Definition of Acronyms: Defines the acronym used in the slides.

Question: Marks questions asked on the slide.

Group Exercise: Test for Understanding (TFU), which requires the students to work in groups.

Introduction

HSPICE Advanced Topics1-1

© 2007

11-

Agenda

Introduction1

Verilog-A Modules2


3

DAY

1111

Synopsys 60-I-032-BSG-005 © 2007 Synopsys, Inc. All Rights Reserved

Introduction


© 2007

21-

Unit Objectives

After completing this unit, you should be able to:

Explain the HSPICE file structure

List what files HSPICE outputs

Demonstrate how to start HSPICE

Use .measure statements

Use .alter blocks

Use the Discovery AMS Simulation Interface

Use CosmosScope

Introduction


© 2007

31-

HSPICE Fundamentals

Files and suffixes

Netlist structure

Naming conventions

Units and scale factors

Introduction


© 2007

41-

Files and Suffixes

.ft# (e.g. .ft0)FFT

.lisOutput listing

All analysis data files

CosmosScope Input

.m*# (e.g. .mt0)Measure output

.ac# (e.g. .ac0)Analysis data, ac

.sw# (e.g. .sw0)Analysis data, dc

.tr# (e.g;. .tr0)Analysis data, transient

.st0Run Status

HSPICE Output

.inc, .libModel/libraries

.spInput netlist

HSPICE Input

Introduction


© 2007

51-

Starting HSPICE

Typical command line invocations:

hspice design.sp > design.lis (UNIX only)

hspice –i design.sp -o design.lis (Windows and UNIX)

.lis file contains results of:

.print

.op (operating point)

.options (results)

Introduction


© 2007

61-

Netlist Structure

One main program and one or more optional

submodules:

.ALTER

High-level call statements can restructure netlist

file modules:

.INCLUDE

.LIB

Calls to external data files:

.DATA

Order independent:

Last definition is used for parameters and options

Introduction


© 2007

71-

Netlist Structure: Overview

Title First line is always the title

Comment character * - comment for a line

$ - comment after a command

Options .option post

Print/Probe/Analysis .print v(d) i(rl)

.probe v(g)

.tran .1n 5n

Initial Conditions .ic v(b) = 0 $ input state

Sources Vg g 0 pulse 0 1 0 0.15 0.15 0.42

* example of a voltage source

Circuit Description MN d g gnd n nmos

RL vdd d 1K

Model Libraries .model n nmos level = 49

+ vto = 1 tox = 7n

* ‘+’ continuation character

END .end $ terminates the simulation

Introduction


© 2007

81-

+

-

V

Every node must have a DC path to ground

+

-

V

No dangling nodes

+

-

V

+

-

V

No voltage loops

+

-

I

No ideal current source in closed capacitor loop

Netlist Structure: Topology

No ideal voltage source in closed inductor loop

+

-

V

No stacked current sources

+

-

I

+

-

I

Introduction


© 2007

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Node Naming Conventions (1/2)

Node names:

Can be up to 1024 characters

Either names or numbers (e.g. n1, 33, in1, 100)

Numbers: 1 to 9999999999999999 (1 to 1e16)

Nodes with number followed by letter are all the same (e.g. 1a=1b)

Leading zeros in node names are ignored

Can begin with these characters: # _ ! %

0 is ALWAYS ground

Global vs. local

Introduction


© 2007

101-

Node Naming Conventions (2/2)

Guidelines for node naming:

Do not begin with a “/”

May contain: + - * / : ; $ # . [ ] ! < > _ %

May NOT contain: ( ) , = ‘ <space>

Ground may be either 0, GND, !GND or GROUND

The period (.) is reserved to indicate hierarchy

TIME, TEMPER, HERTZ, TRANSFORMER, VCVS, CCCS, VCCAP, VCR, CCVS, DELAY and OPAMP are reserve keywords

Every node must have at least two connections:

Except Tline or MOS substrate

Introduction


© 2007

111-

Element Naming Conventions

Element names:

Names must begin with an alphabetic character, but thereafter can contain numbers and the following characters: ! # $ % * + - / < > [ ] _

Names can be up to 1024 characters long

Names are not case sensitive

Element instances begin with the element key letter

Subcircuit instance names begin with X

Parameter names:

Follow the name syntax rules except that names must begin with an alphabetic character

The other characters must be either a number, or one of these characters: ! # $ % [ ] _

Introduction


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Units and Scale Factors

Units:

R - ohm

C - Farad

L - Henry

Technology scaling:

SCALE and SCALM

ALL lengths and widths are in METERS

Scale factors

A = 1e-18

F = 1e-15

P = 1e-12

N = 1e-9

U = 1e-6

M = 1e-3

K = 1e3

MEG = X = 1e6

G = 1e9

T = 1e12

MIL(S) = 25.4e-6

FT = .3048 (METERS)

DB = 20log10

Introduction


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.MEASURE

.MEASURE:

Prints user-defined electrical specifications of a circuit

.MEASURE is a post processor

Used extensively for optimization and curve fitting

Seven fundamental measurement modes

Rise, Fall, Delay

Average, RMS, Min, Max, and Peak-to-Peak

Find-When

Equation Evaluation

Derivative Evaluation

Integral Evaluation

Relative Error

Introduction


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.MEASURE: Rise/Fall (1/2)

Syntax:

.MEASURE <DC|TRAN|AC> result TRIG TARG

+ <optimization options>

Result - name given the measured value in the HSPICE output

TRIG trig_var VAL=trig_val <TD=timedelay>

+ <CROSS=#of> <RISE=#of> <FALL=#of>

TRIG AT=value

TARG targ_var VAL=targ_val <TD=timedelay>

+ <CROSS=#of|LAST><RISE=#of|LAST>

+ <FALLS=#of|LAST>

Introduction


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.MEASURE: Rise/Fall (2/2)

Example:

.MEAS TRAN TDELAY TRIG V(1)

+ VAL=2.5 TD=10ns RISE=2

+ TARG V(2)VAL=2.5 FALL=2

Delay 10ns

…

…

2.5v

2.5v

TDLAY

V(1)

V(2)

Introduction


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.MEASURE: AVG, RMS, MIN, MAX, PP (1/2)

Syntax:

.MEASURE <DC|TRAN|AC> result func out_var

+ <FROM=val> <TO=val> <optimization options>

Func

AVG, RMS, MIN, MAX, PP

Result

Name given the measured value in the HSPICE output

Out_var

Name of the output variable to be measured

Introduction


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.MEASURE: AVG, RMS, MIN, MAX, PP (2/2)

Examples:

.MEAS TRAN avgval AVG V(10)From=10ns To=55ns

Print out average nodal voltage of node 10 during tran time 10 to 55ns

Print as “avgval”

.MEAS TRAN maxval MAX V(1,2)

+ From=15ns To=100ns

Find the maximum voltage difference between nodes 1 and 2 from time 15ns to 100ns

Print as “maxval”

Introduction


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.MEASURE: FIND-WHEN

Allows any independent variables (time, frequency,

parameter), by using WHEN syntax, or any

dependent variables (voltage, current, etc), by using

Find-When syntax, to be measured when some specific event occurs

Syntax:

.MEASURE <DC|TRAN|AC> result WHEN out_var=val

+ <TD=val> <RISE=#of>|LAST> <FALL=#of|LAST>

+ <CROSS=#of|LAST> <optimization options>

Introduction


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.MEASURE: FIND-WHEN Examples

Example of WHEN:

.MEAS TRAN fifth WHEN V(osc_out)=2.5v RISE=5

Measure the time of the 5th rise of node “osc_out” at 2.5v

Store in variable fifth

Example of FIND-WHEN:

.MEAS TRAN result FIND v(out) WHEN v(in)=40m

Measure v(out) when v(in)=40m

Store in variable result

Introduction


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.MEASURE: Equation Evaluation

Equation Evaluation:

Use this statement to evaluate an equation that can be a function of the results of previous .MEASURE statements

The equation must not be a function of node voltages or branch currents

Syntax

.MEASURE <DC|TRAN|AC> result PARAM=‘equation’

+ <optimization options>

Result - name given the measured value in the HSPICE output file

Example:

.MEAS TRAN T_from WHEN V(out)=’0.5*vcc’ CROSS=1

.MEAS TRAN T_to WHEN V(out)=’0.5*vcc’ CROSS=2

.MEAS TRAN Tmid PARAM=‘(T_from+T_to)/2’

Introduction


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.MEASURE: Derivative Function

Derivative Function:

Provides the derivative of an output variable at a given time or frequency or for any sweep variable

Provides the derivative of a specified output variable when some specific event occurs

Syntax:

.MEASURE <DC|TRAN|AC> result DERIVATIVE

+ out_var WHEN var2=val <TD=val>

+ <RISE=#of>|LAST> <FALL=#of|LAST>

+ <CROSS=#of|LAST> <optimization options>

Example:

.MEAS TRAN slewrate DERIV v(1)

+ WHEN V(osc_out)=2.5v RISE=5

Introduction


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.MEASURE: Integral Function

Integral Function:

Provides the integral of an output variable over a specified period

Syntax:

.MEASURE <DC|TRAN|AC> result INTEGRAL out_var

+ <FROM=val1> <TO=val2> <optimization options>

Example:

.MEAS TRAN charge INTEG I(cload)

+ FROM=10ns TO=100ns

Introduction


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.ALTER: Description

Rerun a simulation several times with different:

Circuit topology

Models

Library components

Elements

Parameter values

Options

Source stimulus

Analysis variables

Print/probe commands

Must be parameterized

Introduction


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.ALTER: Limitations

CAN include:

Element Statements

.DATA, .LIB, .DEL LIB, .INCLUDE, .MODEL statements

.IC, .NODESET statements

.OP, .OPTIONS, .PARAM, .TEMP, .TF, .TRAN, .DC, .AC

CANNOT include:

.PRINT, .PROBE, or any other i/o statements

Unless they are parameterized

AVOID:

Adding analysis statements under each .ALTER block

Will cause huge penalty in simulation time and confusion in the output results

Introduction


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.ALTER Rules (1/2)

If the name of a new element, .MODEL statement, or a subckt is identical to the name of an original statement of the same type, the new statement replaces the old

Element and .MODEL statements within a subckt definition can be changed and new element and .MODEL statements can be added to a subckt definition

Topology modifications to subckt definitions should be put into libraries and added with .LIB and deleted with .DEL LIB

If elements or model parameter values were parameterized when using .ALTER, these parameter values must be changed through the .PARAM statement

Introduction


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.ALTER Rules (2/2)

If a parameter name of a new .PARAM statement in the

.ALTER module is identical to a previous parameter name,

the new assigned value replaces the old

Do not re-describe the elements or model parameters with

numerical values

Options turned on by an .OPTIONS statement in an original

input file or an .ALTER submodule can be turned off

Only the actual altered input is printed for each .ALTER run

A special .ALTER title identifies the run

But a .INCLUDE statements within a file called with a .LIB

statement can be accepted by .ALTER processing

Introduction


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.ALTER: Example

* ALTER Test

* CMOS Inverter

.OPTIONS ACCT LIST

.OP

.DC VIN 0 5 0.1

.PRINT DC v(3) v(2)

.PRINT tran v(3)

.PARAM VDD=5

.LIB ‘MOS.LIB’ NORMAL

VDD 1 0 VDD

VIN 2 0

M1 3 2 1 1 P 6U 15U

M2 3 2 0 0 N 6U 15U

.ALTER Change Supply

.PARAM VDD=10

.ALTER Fast Process

.DEL LIB ‘MOS.LIB’ NORMAL

.LIB ‘MOS.LIB’ FAST

.ALTER Add Transient

.TRAN .1 2

.END

alter to add transient(VDD=10v still in effect)(.lib ‘mos.lib’ FAST still in effect).OPDC SweepTransient

.OPDC Sweep

change VDD to 10v.OPDC Sweep

alter change to fast library (MUST delete first)(VDD=10v still in effect).OPDC Sweep

Introduction


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Discovery AMS Simulation Interface Basics

To start the Discovery AMS Simulation Interface

% simif

Setup a new project

Project name

New directory for all project test benches

Project location

Location of project directory

Open an existing project

Introduction


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Discovery AMS Simulation Interface

Introduction


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Discovery AMS Simulation Interface – Project Management

Manage the project test benches

Close the project

Delete the project

Create a new test

Import an older simulation (.wrk) file

Introduction


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Discovery AMS Simulation Interface – Project Management

Introduction


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Discovery AMS Simulation Interface – Setup

HSPICE simulation is divided into 3 major tasks

Setup Netlist and Simulation

HSPICE Setup

Run

Output

Selected by buttons near the top, left of the workbench

Each button selects a new set of screens

The GUI always starts in the Setup mode

Each task contains either tabs or buttons that allow the user to enter specific information and data required by HSPICE

Introduction


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Discovery AMS Simulation Interface – Netlist & Simulation

Netlist & Simulation is select from the tree on the

left of the GUI

Model Setup

Name and corner of any model files used by the design

Design Variables

Design parameters

Analog Options

Set SCALE and TNOM options

External Files

Specify the netlist file(s) used by the design

Specify the Verilog-A behavioral model files by the design

Specify the name of any vector file(s) used by the design

Introduction


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Discovery AMS Simulation Interface – Netlist & Simulation

Introduction


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Discovery AMS Simulation Interface – HSPICE Setup

Analysis

Supports all HSPICE analyses

Waveform

Output waveforms setup supports both .PROBE and .PRINT

Select waveform viewer Cosmos Scope (default)

AvanWaves

Post Proc

Setups for .MEAS, .STIM and .BIASCHK statements

Convergence

.IC and .NODESET setup

.SAVE and .LOAD

Options

Frequently used HSPICE options in its own category

Commands

Setup any options or commands not available from the setup screens

Behavioral

Verilog-A

Introduction


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Discovery AMS Simulation Interface – HSPICE Setup

Introduction


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Discovery AMS Simulation Interface – Run

Run any simulation that is setup

View listing (.lis) file

Errors and warnings are highlighted

View run script and header file

Start waveform viewer

CosmosScope

Introduction


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Discovery AMS Simulation Interface – Run

Introduction


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Discovery AMS Simulation Interface - Output

View Status file (*.st#)

View Subcircuit cross-listing (*.pa#)

View Initial condition (*.ic#)

View .MEASURE results

AC measures (*.ma#)

DC measures (*.ms#)

Transient measures (*.mt#)

.MEASURE file processing

Introduction


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Discovery AMS Simulation Interface - Simulation

Introduction


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Invoking CosmosScope

Unix/Linux Users

Type cscope at the command prompt:

% cscope

Windows Users:

Select Start Programs Synopsys 2006.03 Cosmos-Scope CosmosScope

Introduction


© 2007

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CosmosScope Basics

Pulldown Menu BarCosmosScope Icon Bar

Graph Window

Tool Bar

Help Field

Introduction


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431-

CosmosScope Pulldown Menu Bar

Edit/Preferences

Graph/Plot

File Control

Graph Window

Control

Alternate Tool BarIcon Control

CosmosScope

Window Control

CosmosScopeHelp

Introduction


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441-

CosmosScope Icon Bar

New XYGraph

New SmithChart

New PolarChart

Open

Reload

Save

Print

Cut

Copy

Paste

ZoomIn

Zoomto Fit

ZoomOut

CascadeWindows

TileWindows

ToggleGrid

ToggleSignal Grid

ConfigureDynamic

Waveform Display

CreateBus

BurstBus

At XMeas.

At YMeas.

Point toPoint Meas.

Clear

Introduction


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CosmosScope Tool Bar

Drawing Tool

AIM CommandLine

Signal Manager

MeasurementTool

Waveform Calculator

MacroRecorder

RF Tool

MatlabCommand

Line

Introduction


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CosmosScope Mouse Usage

Left click to select (buttons, objects, etc.)

Right click on anything to get a context-sensitive menu

Middle-click to paste what is selected in the pointed-to

location

Drag with the middle button held down for panning

For a two-button mouse, middle-click can be emulated by

clicking the right and left mouse buttons simultaneously

Shift-clicking the left mouse button adds to your selection if

working with graphical objects, and adds everything from your current selection to the click point in list boxes

Control-clicking the left mouse button adds to your selection

Dragging the left mouse button zooms (expands) the contents inside the box

Introduction


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Opening a Plotfile

In the Scope Window select File Open Plotfiles or press the button

Navigate to the directory where the desired plotfile is located

In the Files of type field, select the type of plotfile you would like to open

Select the plotfile and click

Introduction


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CosmosScope File/Signal Control Forms

PlotfileManager

SignalManager

Introduction


© 2007

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Scope Plotting Techniques (1/2)

Plot one signal at a time:

Method 1 Left click on the signal name in the signal manager

Press the plot button

Method 2 Double-click on the signal name

Plot multiple consecutive signals:

Method 1 Click on the first signal

Hold and drag to the last signal


Method 2 Click on the first signal and release

Hold down the shift key and click on the last desired signal


Introduction


© 2007

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Scope Plotting Techniques (2/2)

Plot multiple non-consecutive signals:

Click on the first signal

Hold down the control key while clicking on other signals

Then press the plot button

Plot signals on top of each other:

Plot the first signal using any of the above approaches

Select the signal to plot on top of the first signal

Middle click in the region of the first signal

Introduction


© 2007

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CosmosScope Measurements

Measurements are the the key to design analysis

Over 50 built-in measurements at your fingertips

Can be applied graphically in CosmosScope or in

"Batch" mode for automatic data collection

You can add custom measurements

Introduction


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Introduction


© 2007

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General Measurements:

At X, at Y, delta X, delta Y, length, slope, local min/max, crossing, horiz. level, vert. level, vert. cursor, point marker, point to point

Time Domain:

Duty cycle, frequency, period, pulsewidth, risetime, falltime, slew rate, delay, overshoot, undershoot, settle time, eye diagram

Reference or level measurements:

Max, min, X at max, X at min, peak to peak, topline, baseline, amplitude, average, RMS, AC-coupled RMS

Frequency Domain:

Lowpass, highpass, bandpass (Q, ripple, etc.), stopband, phase margin, gain margin, slope, magnitude, dB, phase, real, imaginary, Nyquist plot frequency

S Domain

Damping ratio, natural frequency, quality factor

Statistics:

Max, min, range, mean, median, std. deviation, mean (+/- 3 std dev), histogram, yield, Dpu, Cpk, pareto

Introduction


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CosmosScope Calculator

Entry Field (Register)

Icon Bar

Pulldown Menus

Programmable Buttons

Stack Display

Extended Operation Buttons

Keypad

Introduction


© 2007

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Using the Calculator

To get a waveform into the Register:

Select the waveform name on the graph window (or in the Plot File Window)

Middle-click in the Register

You can also select Edit Paste in the calculator to accomplish this task

Either Reverse Polish Notation (RPN) or Algebraic

input modes can be selected

To plot results from the calculator:

Click on the left-most icon in the Icon Bar

Introduction


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Lab 1: HSPICE

During this lab, you will:

1. Create a HSPICE netlist

2. Use the Discovery AMS Simulation Interface to set up and start HSPICE to simulate the netlist

3. View the results in CosmosScope

Netlist

Setup

Simulation

CosmosScope

90 minutes

Verilog-A ModulesHSPICE Advanced Topics

2-1© 2007

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Agenda

Introduction1

Verilog-A Modules2

DAY

1111



3


2-2© 2007

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Unit Objectives


Use Verilog-A modules


2-3© 2007

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Introduction to Verilog-A

What is Verilog-A

Standard analog hardware description language

The analog-only subset of Verilog-AMS

Verilog-AMS LRM, version 2.2, released in November 2004

Verilog-A applications

Multi-level design simulation

Compact models

Analog test benches

Verilog-A in HSPICE

Compiled Verilog-A Solution

Single kernel simulation


2-4© 2007

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Feature Overview (1/2)

Production since W-2005.03

Compiled-code Solution

High performance with golden accuracy

Supports up-to-date Verilog-A language features

Compatible with Verilog-AMS LRM 2.2

Provides industry standard compliant Verilog-A language support

Users can use existing Verilog-A code without any changes

Provides HSPICE Verilog-A device support with existing syntax

Verilog-A modules are instantiated in the same manner as HSPICE subcircuits

All major features available on HSPICE will be supported in Verilog-A based devices

Users do not lose any significant simulator functionality when simulating with Verilog-A based devices


2-5© 2007

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Feature Overview (2/2)

All major analysis types available on HSPICE are supported in Verilog-A based devices

DC analysis

AC analysis (.AC, .LIN, .NET)

Transient analysis (.TRAN, .FFT, .FOUR)

Noise analysis

Pole-Zero analysis

Sweeping, Monte Carlo, Optimization

Alter analysis


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Verilog-A Usage Overview

Verilog-A modules are loaded into the system via “.hdl” command

Modules are instantiated with the same syntax as HSPICE subcircuits

Verilog-A device data can be output using conventional output commands

* Simple Verilog-A amplifier

.hdl my_amp.va

vs 1 0 1

rs 1 0 1

x1 1 2 my_amp gain=10

rl 2 0 1

.print tran V(x1.in) I(x1.out) x1:gain

module my_amp(in, out);

electrical in, out;

parameter real gain = 1.0;

analog begin

V(out) <+ gain * V(in);

end

endmodule


2-7© 2007

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Loading Verilog-A Files (1/2)

Two ways to load Verilog-A files

.hdl netlist command

Follows the syntax of NanoSim

Examples:

.hdl “my_amp.va”

.hdl “va_res” $$ searching for va_res.va file

-hdl command line option

Allows simulations to choose whether Verilog-A modules are used or not

Verilog-A modules can be changed without netlist modification

Each Verilog-A file used needs one –hdl option

Examples:

hspice test.sp –hdl pll.va –vamodel –o test

hspice input.sp –hdl my_amp.va –o va_test

hspice pll.sp –hdl chrgp –hdl vco –o pll_test

A Verilog-A file is assumed to have the .va extension when only prefix is supplied


2-8© 2007

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Loading Verilog-A Files (2/2)

The .hdl command may be placed anywhere in the top-level circuit Can be placed in .alter blocks

Cannot be inside subcircuit definition

Cannot be inside if-else statement

The -hdl is the command line equivalent to the netlist .hdl command -hdl has higher priority than .hdl netlist command

If a Verilog-A module has the same name as a previously loaded module, or the names differ in case only, the later one will be ignored

If a Verilog-A module has name conflict with any HSPICE built-in model name, the Verilog-A definition will be ignored

Built-in model name: R, C, D, L, N/PMOS, NPN, PNP, etc.


2-9© 2007

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Defining the Verilog-A Module Path

Two methods to define the Verilog-A module search path

-hdlpath command line option

Example:

hspice amp.sp –hdlpath ~/vamodules –hdl amp.va

HSP_HDL_PATH environment variable

Example:

setenv HSP_HDL_PATH ~/shared_libs/veriloga

The directory search order for Verilog-A files

Current working directory

Path defined by –hdlpath

Path defined by HSP_HDL_PATH


2-10© 2007

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Instantiation Syntax

Verilog-A devices are X devices in HSPICE netlist

SyntaxX<inst> <nodes>* moduleName|modelName <param=value>*

Verilog-A devices may have zero or more nodes and, zero or more parameters

Example:Xva_r plus minus va_r res=100

Verilog-A module may be instantiated directly or instantiated via an associated Verilog-A model card

Default HSPICE search order for cell definition for X devices

Subcircuit Definition

Verilog-A Model Cards

Verilog-A Module Definition


2-11© 2007

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Verilog-A Model Cards

Model card is a parameter sharing mechanism

When parameter sets are almost the same they can be shared among many instances

Advantage to compact model

Syntax is the same for Verilog-A devices as for built-in devices

Verilog-A model syntax

.model modelName modelType param=value

modelType - Verilog-A module name, cannot conflict with built-in model types (e.g., R, C, D, etc.)

modelName - model name reference used by the instance

Example:

.model my_bjt_va bjt_va rb=6.5 rc=6.3 re=0.15


2-12© 2007

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Instantiation Examples (1/2)

// Verilog-A module example

module va_amp(in, out);

electrical in,out;

parameter real gain=1.0, fc=100e6;

analog begin

…

endmodule

One Verilog-A module can have one or more optional associated model cards

Examples:

.model myamp_model va_amp gain=2 fc=200e6

.model myamp_model_2 va_amp gain=10

Any module parameter can be specified on its model cards or on the instance

Instance parameters override model parameters


2-13© 2007

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Instantiation Examples (2/2)

Instantiations of Verilog-A module ‘va_amp’

x1 n1 n2 myamp

x2 n3 n4 myamp gain=2.0

x3 n5 n6 myamp2 fc=150e6

x4 n7 n8 va_amp

x1 inherits model ‘myamp’ parameters gain=2, fc=200e6

x2 inherits ‘fc=200e6’ from ‘myamp’ and overrides ‘gain’

x3 inherits parameter “gain=10” from model ‘myamp2’and overrides parameter ‘fc’ which is an implicit

parameter in ‘myamp2’

x4 directly instantiates the Verilog-A module ‘va_amp’


2-14© 2007

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Parameter Case Sensitivity

Verilog-A is case sensitive

HSPICE is case insensitive Module parameters that differ by case only cannot be redefined in its

netlist instantiations

Example:

module my_amp(in, out);

electrical in, out;

parameter real gain = 1.0;

parameter real Gain = 1.0;

analog V(out) <+ (Gain+gain)*V(in);

endmodule

If the user instantiates the module as:x1 n1 n2 my_amp Gain=1

The simulator cannot uniquely define which parameter is to be set A warning message regarding the ambiguity is issued and the definition of

the parameter is ignored


2-15© 2007

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Bus Support

Verilog-A supports the concept of bus (vector ports)

HSPICE does not

When instantiating a module which has vector ports, the individual bus lines need to be specified

The Verilog-A module will internally collapse the lines and connect them up to the vector portExample:

module d2a(in, out);

electrical [1:4] in;

electrical out;

analog

…

** Instantiation of module d2a

x1 in1 in2 in3 in4 o1

The lines in1 -> in4 are mapped to ports in[1] -> in[4]

Make sure that the instantiation order matches the vector port order defined in the module


2-16© 2007

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Output Control (1/2)

Output for Verilog-A devices:

Direct port voltage access

Direct port current probing

Internal node voltage access

Internal named branch probing

Module parameter value

Module variable value

V() and I() access functions

Port voltage and internal node voltages are accessed via the V() function

Internal node access requires the full hierarchical name

Port current and named branch currents are accessed via the I() function


2-17© 2007

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Output Control (2/2)

Reporting Convention for Currents

A positive branch current implies that current is flowing into the device terminal or internal branch

Module Parameter Output Syntax

Instance_name:parameter

Example:

.print xva_r:reff

plus minusXva_r

I(xva_1:plus) I(xva_1:minus)


2-18© 2007

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Output Control Example (1/2)

Verilog Module

// Verilog-A module

module va_fnc(plus, minus);

electrical plus, minus;

electrical int1, int2;

parameter real r1=0, r2=0;

branch (int1, int2) br1;

// creates an internal branch br1 between

// internal nodes int1 and int2;

child_module c1 (plus, int1);

child_module c2 (minus, int2);

…

Endmodule

Verilog-A device in netlist

x1 1 2 va_fnc r1=1 r2=2


2-19© 2007

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Output Control Example (2/2)

To print the current on Verilog-A device port name plus for the instance x1:

.print I(x1.plus)

To print the Verilog-A module internal node named int1 for the instance x1:

.print V(x1.int1)

In this module there is an internal branch name br1 declared then, the branch current can be probed as:

.print I(x1.br1)

If the module va_fnc is hierarchical and has a child instance called c1 with an internal node c_int1 then the node c_int1 can be output as:

.print V(x1.c1.c_int1)

Wildcarding can be use to output internal nodes, int1 and int2 for the child c1 in the instance x1:

.print v(x1.c1.int*)


2-20© 2007

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Overriding Subcircuits with Verilog-A Modules

If both a subcircuit and a Verilog-A module have the same case-insensitive name, by default, HSPICE uses the subcircuitdefinition

Vamodel option lets Verilog-A definition take preference

Supports cell-base definition only

Can be specified as a netlist option or a command line option

Netlist option syntax:

.option vamodel [=name]

Examples: .option vamodel=vco vamodel=chrgpump

– Instances of vco and chrgpump will use Verilog-A definition

.option vamodel

– All cell instantiations will use Verilog-A definition whenever it is available

Command line option: –vamodel

hspice input.sp –hdl va_models –vamodel chrgpump –vamodel vco


2-21© 2007

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Disabling .option VAMODEL with .option SPMODEL

.option spmodel switches back to HSPICE definition

Supports cell-based definitions only

Useful for .ALTER blocks

Netlist Syntax

.option spmodel [=name]

Examples:

Specific module

.option spmodel=vco

Assuming switched to a Verilog-A module in an earlier .alter block

Instantiations of vco will use subckt definition again

Global

.option spmodel

All cell instantiations will use subckt definitions

There is no equivalent command line option for spmodel


2-22© 2007

222-

Addition Information – vamodel and spmodel

Command line option -vamodel has preference over any netlist vamodel or spmodel options

Example:hspice va_opt.sp –hdl va_models –vamodel my_cap

Every run uses the Verilog-A definition for cell my_cap

Specific vamodel and spmodel options have preference over global options

Examples:* va_opt.spi

* all will use Verilog-A definition whenever available

.option vamodel

.alter 1

* all will use subckt definition whenever available

.option spmodel

.alter 2

.option vamodel=my_cap $$ my_cap will use Verilog-A

.option spmodel $$ my_cap will still use Verilog-A

…


2-23© 2007

232-

Stand-Alone Compiler

Verilog-A files can be compiled manually using the hsp-vacomp command

Input a Verilog-A file, compiler produces a Compiled Model Library (CML) file

A .cml file is a platform and version specific shared library

.cml files can be directly loaded

Compiler Example:

% hsp-vacomp resistor.va

Produces resistor.cml in the same directory

Load Example:

.hdl resistor.cml $$ load resistor.cml


2-24© 2007

242-

Verilog-A Examples

Examples of typical Verilog-A modules with HSPICE netlists are located at:

$installdir/demo/hspice/veriloga/


2-25© 2007

252-

Lab 2: Verilog-A Modules


1. Use Verilog-A modules in a circuit

2. Simulate the circuit

3. View the simulation results

Netlist

Setup

Simulation

CosmosScope

45 minutes


2-26© 2007

This page was intentionally left blank.

Simulating Variability - Design for YieldHSPICE Advanced Topics

3-1© 2007

13-

Agenda

Introduction1

Verilog-A Modules2

DAY

1111



3


3-2© 2007

23-

Unit Objectives


Understand and modify a Variation Block

Use DCMatch analysis

Use Monte Carlo analysis


3-3© 2007

33-

Source: IBS Report

Wafer Yield in Nanometer Technologies

20

30

40

50

60

70

80

90

100

350 250 180 130 90

Technology nodes (nm)

Pro

du

ct

yie

ld (

%)

Lithography & new materials

Parametric Variability

Defect density

65nm

45nm

20

30

40

50

60

70

80

90

100

350 250 180 130 90

Technology nodes (nm)

Pro

du

ct

yie

ld (

%)

Lithography & new materials

Parametric Variability

Defect density

65nm

45nm


3-4© 2007

43-

Variation Components Across Wafer

Global Variation Linear Variation Radial Variation

Wafer Level Variation


3-5© 2007

53-

Variation Components From Reticle

Across Reticle

Variation

Combined Across Wafer Variation


3-6© 2007

63-

Variation Components Due To Discreteness of Atoms and Photons

Oxide layer thickness

Poly line edge roughness

Discrete number of dopants in channel

Affect each device differently

Local Variations

Total parametric variation combines wafer, reticle, and local variations


3-7© 2007

73-

Variation Components Due To Proximity: (not random)

Deterministic

systematic variations,

not random

Can be modeled (WPE)

Not considered here under variability

orientation

density

metal coverage

well proximity


3-8© 2007

83-

minimum size device drain current variation > 40% (3-σ)

Table data: Nassif CICC 2001

0.9 300 +/-403 +/-0.4870 +/-332006

1.2 350 +/-403.5 +/-0.42100 +/-402005

1.5 400 +/-404 +/-0.39130 +/-452002

1.8 450 +/-454.5 +/-0.36180 +/-601999

2.5500 +/-505 +/-0.4250 +/-801997

vddVth (mV)tox (nm) leff (nm)Year

History of Parameter Values and Variations (3-σ)

Quantifying Variability in Nanometer Technologies


3-9© 2007

93-

Contents

Variability on Silicon

Devices

Interconnect

Variation Block

Monte Carlo Analysis

Data Mining

Mismatch Analyses

DCMatch Analysis

ACMatch Analysis

Mismatch versus Monte Carlo


3-10© 2007

103-

Cu Interconnect Stack Structure

Source: ITRS

up to 16 layersof interconnect

Passivation

Wire

Via

Silicon Bulk with

Active Devices

Dielectric


3-11© 2007

113-

Random Variation in Interconnect

Interconnect Process Variables:

Metal : - thickness

- line width and spacing

- resistivity

Dielectric: - thickness

- dielectric constant

Vias: - resistance

metaln-1

metaln

metaln+1

h1

h2w

tn

s

tn+1

tn-1

over 150 parameters have random variation in 65nm process


3-12© 2007

123-

Star-RCXTStar-RCXTStar-RCXT

Multiple

corner

files

Process Characterization

nxtgrd

PrimeTime HspiceHspiceHspiceHSPICE

Layout

nxtgrdnxtgrd

nxtgrd

Star-RCXT

PrimeTimePrimeTimePrimeTime

netlist

Interconnect Variation Modeling: Current Approach

Corner files with fixed min or max value for each layer

Full extraction for each corner

Results are worst case points, pessimistic


3-13© 2007

133-

Process Characterization

nxtgrd with variation

PrimeTime HSPICE

Star-RCXT Statistical Extraction

Extracted Netlist with Parasitics and

Variation Information

Layout

Monte

Carlo

Interconnect Variation Modeling: Statistical Extraction Flow

Single technology file with statistics for all layers

Single extraction

Netlist includes variation information

Resulting distribution shows effects of device and interconnect variation


3-14© 2007

143-

Contents


Devices

Interconnect

Variation Block


Data Mining

Mismatch Analyses

DCMatch Analysis

ACMatch Analysis



3-15© 2007

153-

Variation Model in HSPICE

Global variation

Statistical equivalent of corner files

Corner files represent extreme points of a distribution

Global variation describes continuous distribution shape

Local variation

Random variation between adjacent devices with identical layout

Critical for high precision analog

Increasingly important for digital

Spatial variation:

To model effects of gradients

Not important for small blocks

These variation types are independent of each other and easy to extract from test structures


3-16© 2007

163-

Variation Block Overview

Complements nominal model definitions

Variation types: Global, Local and Spatial

Variation definitions for devices and interconnect

Emphasis on variations in materials and manufacturing

Created by foundry; possibly encrypted

Definitions used for Monte Carlo and Mismatch Analyses

Designers can choose options and variation on elements


3-17© 2007

173-

Variation Block Structure

.variation

optionsdefine parameters common to all sub-blocks

.global_variationdefine random variablesdefine variations of model parameters

.end_global_variation

.local_variationdefine random variablesdefine variations of model parameters.element_variation

define variations of element parameters.end_element_variation

.end_local_variation

.spatial_variationdefine random variablesdefine variations of model parameters

.end_spatial_variation

.end_variation


3-18© 2007

183-

Options and Common Parameters

Options

Regarding use of Variation Block ignore_local_variation

ignore_global_variation

ignore_spatial_variation

ignore_interconnect_variation

ignore_variation_block

For all dependent analyses output_sigma_value

vary_only | do_not_vary

For Monte Carlo analysis

Common parameters:

To define parameters valid only in Variation Block (separate name space)


3-19© 2007

193-

Independent Random Variables

Normal distribution:

A=N() (mean=0, sigma=1)

( also used in implicit definitions)

Uniform distribution:

B=U() (from -0.5 to 0.5)

Cumulative distribution function:

C=CDF(x1,y1,.....xn,yn)

Specification Histogram of 1000 CDF samples


3-20© 2007

203-

Dependent Random Variables

To create arbitrary distributions from basic distributions

Example 1:

var = U()

Y = '0.5 * (D+E) + (E-D) * var '

creates a uniform distribution from D to E

Example 2:

a = N()

b = N()

c = 'a+2*sgn(b)'

Histogram:


3-21© 2007

213-

Syntax for Specifying Variations

Basic construct for describing variation:

Parameter=‘Expression for Sigma’

abbreviated notation for

variation_in_Parameter=‘Expression for Sigma’

Constructs for expressions:

Constants, parameters or functions

Absolute variation or relative ( space % )

Perturb() to reference random variable

get_E() to model dependence on device geometry (w, l, m)or location (xcoor,ycoor)

Implicit definition:

If expression has no reference to random variable ( no Perturb ), then Normal Distribution assumed with zero mean and 1-sigma equal to expression


3-22© 2007

223-

Variations on Model and Element Parameters

Syntax for defining variations on model parameters:

modelType modelName modelPar=‘Expression for Sigma’

Syntax for defining variations on element parameters:

elementType elementPar=‘Expression for Sigma’

Examples:nmos nch vth0='1.2e-9/sqrt(get_E(L)*get_E(W)*get_E(M))'

I DC=12 %


3-23© 2007

233-

Simple Variation Block Example

.variation

.global_variation

nmos nch vth0=0.07 u0=10 %

pmos pch vth0=0.08 u0=8 %

.end_global_variation

.local_variation

nmos nch

+ vth0='1.2e-9/sqrt(get_E(W)*get_E(L)*get_E(M))'

+ u0 ='2.3e-6/sqrt(get_E(W)*get_E(L)*get_E(M))' %

pmos pch

+ vth0='3.4e-9/sqrt(get_E(W)*get_E(L)*get_E(M))'

+ u0 ='4.5e-6/sqrt(get_E(W)*get_E(L)*get_E(M))' %

.element_variation

R r=10 %

.end_element_variation

.end_local_variation

.end_variation


3-24© 2007

243-

Principal Components Based Global Variation Modeling

.Global_Variation

parameter A1=N() A2=N() A3=N()

nmos nch

+ tox =Perturb('-7.2E-12*A1-7.1E-12*A2-8.7E-12*A3')

+ vth0=Perturb('-3.6E-03*A1+8.9E-03*A2-1.5E-03*A3')

+ cjn =Perturb('-3.2E-06*A1+6.7E-06*A2-4.3E-06*A3')

+ u0 =Perturb(' 5.6E-04*A1-9.7E-04*A2+7.6E-04*A3')

+ ....

pmos pch

+ tox =Perturb('-7.5E-12*A1-6.9E-12*A2-8.8E-12*A3')

+ vth0=Perturb('-7.4E-03*A1+3.3E-03*A2-7.2E-03*A3')

+ cjn =Perturb('-5.0E-06*A1+8.9E-06*A2-3.2E-06*A3')

+ u0 =Perturb(' 7.6E-04*A1-4.3E-04*A2+4.8E-04*A3')

+ ....

.End_Global_Variation

Correlation between parameters and devices


3-25© 2007

253-

Local Variations in Nanometer Technologies

.Local_Variation

nmos nch

+ tox ='3.1e-07/sqrt(Get_E(L)*Get_E(W)*Get_E(M))' %

+ wint='6.2e-12/sqrt(Get_E(L))'

+ lint='2.0e-12/sqrt(Get_E(W)*Get_E(M))'

+ ....

Parameter choices and device geometry dependence according to Drennan/McAndrew [4], different from Pelgrom model [2]


3-26© 2007

263-

Spatial Variation Example

.variation

parameter Pi = 3.14159

.spatial_variation

Parameter a = N( ) b = U( )

Parameter Slope = ’20 * a’

Parameter Angle = '2 * Pi * b'

nmos nch vth0 =

+ Perturb(‘Slope*sqrt(get_E(x)*get_E(x)+get_E(y)*Get_E(y)) \\

*cos(Angle-atan(get_E(y)/get_E(x))-(get_E(x)<0?Pi:0))')

.end_spatial_variation

.end_variation

Plane with slope sigma of 20mV/mm, arbitrary rotation on chip surface


3-27© 2007

273-

Designer’s Variation Block

Local variation on elements ( generic R, C, I, V ):.variation.local_variation

.element_variationR r=10 %

.end_element_variation.end_local_variation

.end_variation

Options:.variation

option ignore_local_variation=yes.end_variation


3-28© 2007

283-

Variation Block Summary

Extension of device model

Consolidates definitions for global, local and spatial variations, on devices and interconnect

Clear distinction between different types of variations

Emphasis on variations in material and manufacturing

Flexible syntax allows for proprietary models of variability

Content created by foundry

Designers can specify options and variations on elements


3-29© 2007

293-

Contents


Devices

Interconnect

Variation Block


Data Mining

Mismatch Analyses

DCMatch Analysis

ACMatch Analysis



3-30© 2007

303-

Monte Carlo Analysis in HSPICE

Prior art:

Distributions defined on global parameters (GAUSS, UNIFORM)

Vary-anything approach with implicit rules

Trouble with unexpected behavior

Local variations require lots of memory

Distributions defined on model parameters (LOT/DEV)

Not adopted by the foundries

Lacks geometry dependence

State of art:

Distributions defined in Variation Block

New feature: output file with perturbations for data mining


3-31© 2007

313-

Monte Carlo Commands

Command syntax:.DC sweepVar start stop step sweep MCcommand

.AC type step start stop sweep MCcommand

.TRAN step stop sweep MCcommand

Syntax for MCcommand:Monte = val

Monte = val firstrun=num

Monte = list num

Monte = list (<num1:num2> <num3> <num4:num5>)


3-32© 2007

323-

Options for Monte Carlo Analysis

Options defined in Variation Block:

Variation Block options:Option

ignore_global|local|spatial|interconnect_variation= yes

Option ignore_variation_block = yes

Variability Analysis options:

Option output_sigma_value = value

Option Vary_only | Do_not_vary = subcktList

Monte Carlo options:Option Normal_Limit = value

Option Sampling_method = factorial | ofat | lhs


3-33© 2007

333-

Factorial Sampling

Option sampling_method = factorial

All parameter combinations at nominal + or – Normal_limit

Generates 2^n+1 samples

12 independent variables maximum ( 4097 samples )

Simple way of specifying corners, for worst case analysis

With 5 principal components, 33 relevant corners

1 32 1

22 33

45

45

6 7

8


3-34© 2007

343-

One-Factor-At-a-Time Sampling

Option sampling_method = ofat

One parameter at a time set to nominal + or – Normal_limit

Produces 2*n+1 samples

For sensitivity studies

1 32 1 32

5

4

1 32

5

46

7


3-35© 2007

353-

Latin Hypercube Sampling

Compared to simple random sampling:

Spreads sample points more evenly

3-10X fewer samples for same precision in answers

LHS 10 samples in 2D


3-36© 2007

363-

Monte Carlo Analysis Flow

Start

index 1:

Simulate with no variation applied

index n :

Simulate with variations applied

Global variation: add same random value

to particular parameter for all devices

Local variation: add different random value

to specified parameters for each device

End

Calculate statistics

done more


3-37© 2007

373-

Monte Carlo Result Distributions

32 128 512 2048

samples

5

4

seed 3

2

1


3-38© 2007

383-

Monte Carlo Convergence

↑

error(%)

number of Monte Carlo samples →

20

10

6

4

2

10 30 100 300 1000

1/√n

trend

lineProbability is

2/3 for smaller error

1/3 for larger error


3-39© 2007

393-

Contents


Devices

Interconnect

Variation Block


Data Mining

Mismatch Analyses

DCMatch Analysis

ACMatch Analysis



3-40© 2007

403-

Interpreting Results of Monte Carlo

bad

good

pre

miu

m

good

bad

bad

good

pre

miu

m

good

bad

bad

goo

d

pre

miu

m

goo

d

bad

looks like we need to do some adjustments ...

wide margin at expense of area, power, cost ?

what’s the percentage of good circuits ?

Qualitative view of effects of variations:does this distribution look “normal” ?


3-41© 2007

413-

Application note on HSPICE.com: “Pairs Plots from HSPICE Monte Carlo”

Data Mining: Pairs Plot


3-42© 2007

423-

Data Mining: Pareto Plot

ranked relative offset contributions

for 7-transistor CMOS opamp

mn1 mn2

mp4mp3


3-43© 2007

433-

Monte Carlo Analysis Summary

Uses variation definitions from Variation Block

New sampling methods for faster results

Variety of options to study different types of variation

Output file with parameters for data mining, to identify critical devices and yield limiting process parameters

Results consistent with mismatch analyses


3-44© 2007

443-

Contents


Devices

Interconnect

Variation Block


Data Mining

Mismatch Analyses

DCMatch Analysis

ACMatch Analysis



3-45© 2007

453-

Mismatch Analysis

DCMatch:

To calculate effects of variations on a circuit’s DC operating point

ACMatch:

To calculate effects of variations on a circuit’s AC response

Use variation definitions from Variation Block

Results match those of small signal Monte Carlo

At least one order of magnitude faster than Monte Carlo


3-46© 2007

463-

Mismatch

“Characteristics of identically designed devices vary by small amounts.”

2)(

2VthVgsIds −×=

β

rightleft

rightleft VthVth

ββ ≠

≠

rightleft IdsIds ≠


3-47© 2007

473-

Effects of Mismatch on DC Amplifier

Local variations cause mismatch on identically designed devices

Mismatch in device pairs causes random offset

Equivalent of built-in random voltage source in series with input

inputoutput

Classic 7-transistor CMOS opamp


3-48© 2007

483-

HSPICE DCMatch Analysis Overview

Available in HSPICE since release 2005.09

Uses contents of Variation Block

Reports effects of variations on a circuit’s DC solution

Main output: Table

Sigma of total output variations

Sigma of all variation types

Contributions of parameters and devices

Measure and Probe results available


3-49© 2007

493-

DCMatch Analysis Command

.DCMatch outputVariable <options>

OutputVariable: voltage, difference voltage or current

Options:

Threshold: controls device printout

File: contains tables for DC sweep

Interval: printing subset of tables

Example:

.DCMatch V(9) V(4,2) I(Vmeas)


3-50© 2007

503-

DCMatch Table Result Example

Output sigma due to global and local variations = 619.62uV

DCMATCH GLOBAL VARIATIONOutput sigma due to global variations = 289.66uV---------------------------------------------------------Contribution Contribution Cumulative Independent Sigma(V) Variance (%) Variance (%) Variable 227.94u 61.92 61.92 [email protected] 23.19 85.11 [email protected] 14.40 99.51 [email protected] 485.62m 100.00 snps20n@vth0

DCMATCH LOCAL VARIATIONOutput sigma due to local variations = 547.74uV----------------------------------------------------------Contribution Contribution Cumulative Matched DeviceSigma(V) Variance (%) Variance (%) pair Name 297.91u 29.46 29.46 1 mn1296.38u 29.16 58.61 1 mn2252.37u 21.14 79.75 2 mp3246.91u 20.23 99.99 2 mp4


3-51© 2007

513-

Amplifier with Rail-to-Rail Input Range

input

output

bias

Source: JSSC August 2003combined input stages


3-52© 2007

523-

DCMatch Simulation Result

Input offset sigma due to device mismatch as a function of input common mode voltage:

20

15

10

5

0 0.5 1.0 1.5 2.0 2.5

Input Voltage →

↑Input

offset

sigma

(mV)


3-53© 2007

533-

Benefits of DCMatch Analysis

Reports variation in operating point from local variation definitions in Variation Block and device sizes in netlist

Purpose:

Avoid yield loss due to variations

Design for minimum area

Unique benefits :

Pointer to major contributors of variation

Significantly faster than Monte Carlo

Circuit candidates for DCMatch analysis:

Bandgap references

Operational amplifiers

DACs

Charge pumps

Bias circuits

( ... and which analog circuit does not need bias?)


3-54© 2007

543-

HSPICE ACMatch Analysis Overview

New for HSPICE release 2007.03

Uses contents of Variation Block

Reports effects of variations on AC response

Variations in DC parameters affect DC operating point

Variations in DC operating point change low frequency response

Variations in DC operating point change values of voltage dependent capacitors

Variations in AC parameters change capacitor values

Combination of changes cause variation in AC response

Runs for each sweep point of associated AC analysis

Main output: Table

Output sigma for total variations and all variation types

Individual contributions of parameters and devices forglobal or local variations

Measure and Probe support in 2007.03-SP1


3-55© 2007

553-

ACMatch Analysis Command

.ACMatch outputVariable <options>

OutputVariable:

Voltage, difference voltage or current

Mag, phase, real, imag ( Vm, Vp, Vr, Vi )

options:

Threshold: controls device printout

File: contains tables for DC sweep

Interval: printing subset of tables

Example:

.ACMatch VM(9)

.AC dec 1 1k 10Meg


3-56© 2007

563-

Fully Differential Amplifier

differential

output

differential

input

cmfb

Effect of variations on power supply rejection or feedthrough?

inject

AC signal


3-57© 2007

573-

Power Supply Feedthrough

-28dB

sigma(real)

sigma(imag)

no Variation


3-58© 2007

583-

Benefits of ACMatch Analysis

Reports effect of variations in DC and AC parameters on AC transfer characteristics.

For studying effect of process variation on signal integrity in sensitive circuits, including interconnect variation after layout

Unique benefits of ACMatch analysis:

Pointer to major contributors of variation

Significantly faster than Monte Carlo

Circuit candidates for ACMatch analysis:

Fully differential circuits

Continuous-time integrated filters (MOSFET-C and gm-C)

Crystal oscillators


3-59© 2007

593-

Contents


Devices

Interconnect

Variation Block


Data Mining

Mismatch Analyses

DCMatch Analysis

ACMatch Analysis



3-60© 2007

603-

Mismatch Versus Monte Carlo Analysis

5000 Monte Carlo Samples

Mismatch analyses use calculus of

probability instead of sampling


3-61© 2007

613-

DCMatch and ACMatch Versus Monte Carlo

No

Combined

“pretty good”

Slow

AC, DC, Tran

Any

Variation Block and old style

Monte Carlo

NormalPreferred distributions

Variation Block only

Variation definition

YesDevice/parameter contributions report

ExcellentAccuracy

SeparateVariation contributions (global, local etc)

FastRelative run time

DC, ACAnalysis types

DCMatch/ACMatchFeature


3-62© 2007

623-

HSPICE Documentation on Variability

In HSPICE Simulation and Analysis User Guide:

Chapter 13: Simulating Variability

Chapter 14: Variation Block

Chapter 15: Monte Carlo Analysis

Chapter 16: Mismatch Analyses

Appendix A: Statistical Analysis (deprecated style)

SNUG tutorial: “DCmatch Analysis in HSPICE”

SNUG: Synopsys Users Group - San Jose 2006http://www.snug-universal.org/cgi-bin/search/search.cgi?San+Jose+2006


3-63© 2007

633-

References

1. K.R. Lakshmikumar, R.A. Hadaway, and M.A. Copeland: Characterization and modeling of mismatch in MOS transistors forprecision analog design. IEEE J. Solid-State Circuits, December 1986.

(First paper relating mismatch to device area)

2. M. Pelgrom, A. Duinmaijer, and A. Welbers: Matching properties of MOS transistors. IEEE J. Solid-State Circuits, May 1989.

(Added distance dependence to mismatch modeling)

3. P.R. Kinget: Device mismatch and tradeoffs in the design of analog circuits. IEEE J. Solid-State Circuits, June 2005.

(Importance of mismatch in design; extensive references)

4. P.G. Drennan and C.C. McAndrew: Understanding MOSFET mismatch for analog design. IEEE J. Solid-State Circuits, March 2003.

(Modeling mismatch in nanometer technologies)

5. K. Singhal and V. Visvanathan: Statistical device models from worst case files and electrical test data. IEEE Trans. Semiconductor Manufacturing, November 1999.

(Global variation modeling by principal components)


3-64© 2007

643-

Presentation for Modeling Engineers

Emphasis on:

Process aspects: different types of variations

Variation Block content

Interconnect variability

Approximately 2 hours with Q&A

Can be arranged through WEBEX


3-65© 2007

653-

Lab 3: Simulating Variability – Design for Yield

Lab Test Circuit

Simulations:

Monte Carlo and DCmatch analyses

Global and local variations on sheet resistance

Results:

Divider ratio

Total resistance

Post-process:

CosmosScope histogram

Matlab Demo: Pairs Plot

(See application note: “Pairs Plots from HSPICE Monte Carlo” at HSPICE.com)

90 minutes

S-Parameters and Linear AnalysisHSPICE Advanced Topics

4-1© 2007

14-

Agenda



IBIS6

DAY

2222



4-2© 2007

24-

Unit Objectives


Use linear analysis to extract network parameters

Use S-elements


4-3© 2007

34-

S-Parameter Basics

S (or scattering) parameters is another way to describe a linear multi-terminal network

The independent variables are the injection wave (a) and the reflection wave (b)

(a) and (b) are column vectors while (S) is a square matrix consists of reflection coefficients sij:

(b) = (S)(a)

ai is the normalized injection wave of port i

bi is the normalized reflection wave of port i

sij = bi/aj when matched impedances are connected to the ports other than port j

sii = bi/ai when matched impedances are connected to the ports other than port i


4-4© 2007

44-

Two-Port Scattering Parameters

S11 = input reflection coefficient

S21 = forward transmission coefficient (gain)

S12 = reverse transmission coefficient (isolation)

S22 = output reflection coefficient

S-parameter matrix:

Black

box s11 s22

s21

s12

=

2221

1211

ss

ss

S


4-5© 2007

54-

Linear Multi-Port Parameter Analysis

A linear N-port network is completely characterized at each frequency by a complex NxN signal-transfer matrix and a complex NxN noise correlation matrix

The .LIN analysis will automatically extract these

matrices for a multi-port network and make available a broad set of derived measurements (makes .NET

obsolete)

This analysis will internally compute

Full S-parameter matrix

Noise parameters (reduced to 2-port)

Requires identification of the port terminals

Use new “P” port element

b=SaP1 P2


4-6© 2007

64-

Linear Characterization

HSPICE capable of extracting:

[S], [Y], [Z], [H] parameters, VSWR

Noise parameters (with correlation)

Maximum, available, and associated gains

Stability factors

Impedance matching coefficients

Output file formats

Sc0, TouchStone, CITIFILE


4-7© 2007

74-

Port (P) Element

Identifies the ports used in .LIN analysis

Behaves as either a noiseless resistance or a voltage source in series with the port impedance for all analyses types

Each port number must be a unique number

No shared ports

Port numbers must be sequential

Each port has an associated system impedance, Z0

If not specified, Z0=50Ω

The system impedance can be overridden for a specific analysis type using the keywords rdc, rac, or rtran


4-8© 2007

84-

Port Element Syntax

Pxxx p n port=number

+ <dc mag> <ac <mag <phase>>>

+ <one tran waveform>

+ <zo=val> <rdc=val> <rac=val>

+ <rtran=val>

Examples:

P1 in 0 port=1 ac=1

p2 out 0 port=2


4-9© 2007

94-

.LIN Analysis Syntax

.LIN <sparcalc = [1|0] <modelname = …>

+ <filename = …> <format=[selem|citi|touchstone]>

+ <noisecalc = [0|1]> <gdcalc = [0|1]>>

Examples:

.LIN sparcalc=1 modelname=custom

+ filename=cad1 format=touchstone

+ noisecalc=1 gdcalc=1

.LIN sparcalc=1 modelname=bpf

+ format=selem


4-10© 2007

104-

.LIN Keywords

Sparcalc

Calculate S-parameters (default=1)

Modelname

Model name in the .model statement listed in the .sc# file

Filename

Output filename (default is the netlist name)

Format

S element (.sc#) file, citi file format, touchstone format

Noisecalc

If 1, extract 2-port noise parameters (default=0)

Gdcalc

If 1, extract group delay analysis (default=0)


4-11© 2007

114-

HSPICE Linear Characterization

Setup as .AC swept frequency analysis

Add port elements

Add .LIN

command

Several new .LIN

measurements then available

LNAP1 P2

*HSPICE Linear LNA Analysis

*…

P1 in gnd port=1 z0=50

xLNA in out LNA

P2 out gnd port=2 z0=50

.AC LIN 101 100MEG 10G

.LIN noisecalc=1

.PROBE AC S11 S12 S21 S22

.PROBE AC NFMIN RN GAMMA_OPT

Dumps *.sc0 data file with

Scattering and noise parameters


4-12© 2007

124-

.LIN Parameter Definitions (1/4)

Network Parameters

S - scattering parameters

Y - admittance parameters

Z - impedance parameters

H – hybrid parameters

1 and 2 port only, derived from S-parameters

If more than 2 ports, ports numbered 3 and above are terminated in their port characteristic impedance


4-13© 2007

134-


Optimum Matching for Noise Parameters

ZOPT - source impedance which achieves minimum noise

YOPT - source admittance which achieves minimum noise

Noise Figure

NF - noise figure

NFMIN - noise figure minimum (source at ZOPT)

Group delay

T, TD - group delay from port=1 to port=2


4-14© 2007

144-


Noise correlation

RHON - Correlation coefficient between the input noise voltage and the input noise current

Equivalent noise resistance and conductance

RN - noise equivalent resistance

GN - noise equivalent conductance

Noise correlation impedance and admittance

ZCOR - Noise correlation impedance

YCOR - Noise correlation admittance


4-15© 2007

154-


Stability Parameters

K_STABILITY_FACTOR - Rollett stability factor

Gain Parameters

G_AS - associate gain - maximum gain at the minimum noise figure

G_MAX - maximum available/operating power gain

Matching for optimum gain parameters

GAMMA_S_OPT - source reflection coefficient which achieves maximum available power gain

GAMMA_L_OPT - load reflection coefficient which achieves maximum operating power gain


4-16© 2007

164-

Introduction to Noise Analysis (1/3)

Random disturbance signal in circuit

Device noise is noise from circuit elements (random/stochastic)

Flicker Noise

Thermal Noise

Shot Noise

Interference noise is noise from circuit environment

Ground bounce

Crosstalk

Substrate noise


4-17© 2007

174-


Device noise models are native to HSPICE devices

.LIN and .AC analysis are used to perform the noise

analysis

Noise is modeled in frequency domain (FD)

Noise amplitude is random in time domain (TD)

Noise power is finite if signal is bandwidth limited

Power Spectral Density (PSD) in FD

HSPICE and SPICE random device noise models are not evaluated with .TRAN analysis


4-18© 2007

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Two types of PSD profiles for standard noise sources

Bandwidth limited where power concentrated in a frequency range

Flicker noise

Flat power distribution across all frequencies (white noise)

Thermal noise

Shot noise


4-19© 2007

194-

Noise Representation (1/2)

Total power of a noise signal is the integral of the PSD function with respect to frequency

Vrms of the noise signal represent RMS of average power carried by a noise source in a 1-Hz bandwidth

around f with 1ΩΩΩΩ normalized load

Reference noise signal to input sinusoidal signal

Noise limits the smallest input signal the circuit can handle

Allow a fair comparison of different circuit topology


4-20© 2007

204-

Noise Representation (2/2)

HSPICE noise calculation based on AC nodal voltages

HSPICE calculates the noise generated in each device and its contribution to the noise output

Total output noise voltage is the RMS sum of the individual noise sources


4-21© 2007

214-

Noise Types (1/3)

Thermal Noise

Random movements of electrons in a conductor

Independent of DC current (resistor only)

Proportional to temperature

Gaussian amplitude distribution, Independent of frequency, white spectrum


4-22© 2007

224-

Noise Types (2/3)

Shot Noise

Random passage of electrons and holes across a potential barrier (P-N junction)

Dependent of DC current

Proportional to DC bias current

Gaussian amplitude distribution, independent of frequency, white spectrum


4-23© 2007

234-

Noise Types (3/3)

Flicker Noise (1/f Noise)

Fluctuations in the average current travel time in a conductor

Dependent of DC current

Native to all active devices

Manufacturing process related

Non-Gaussian amplitude distribution, Dependent of frequency, pink spectrum


4-24© 2007

244-

Noise Calculation Example

Setup as .ACswept frequency analysis

Add port elements

Add .LINcommand with noisecalc=1

Several new .LINmeasurements then available

* A Common Source NMOS amplifier

.options list post

.model n_tran nmos level=49

version=3.22 AF=.826 KF=4e-29

vdd vdd 0 DC=5

p1 in 0 port=1 ac=0.1 dc=2.1 z0=50

p2 out vdd port=2 z0=20k

rs in g1 50

m1 out g1 0 0 n_tran l=1.5u w=40u

.ac dec 10 10Meg 10G

.lin noisecalc=1

.print ac v(out) onoise

.end

Dumps *.sc0 data file with

Scattering and noise parameters


4-25© 2007

254-

S-Element

Two types of S-element are supported:

S-parameter

Y-parameter

Y-parameter is the traditional admittance matrix for a multi-terminal network:

(I)=(Y)(U)

(I) is a column vector representing the current of each port

(U) is a column vector representing the voltage of each port

(Y) is the admittance matrix of the multi-terminal network


4-26© 2007

264-

S-Element Syntax

Sxxx nd1 nd2 ... ndN nd_ref

+ <MNAME = S_model_name> <FQMODEL=sp_model_name>

+ <TYPE=[S|Y]> <INTDATTYP =[RI|MA|DBA]>

+ <Zo=[value|vector_value]>

+ <FBASE=base_frequency> <FMAX=maximum_frequency>

+ <PRECFAC=val>

+ <DELAYHANDLE=[1|0|ON|OFF]> <DELAYFREQ=val>

+ <INTERPOLATION=STEP|LINEAR|SPLINE>

+ <HIGHPASS=[3|2|1|0]> <LOWPASS=[2|1|0]>

+ <DTEMP=val>

+ <NOISE=[1|0]>


4-27© 2007

274-

S-Element Rules

The only required field is the nodes and must be defined before any optional parameters

If MNAME is not specified, FQMODEL must be set

The optional arguments may come in any order

All the optional parameters except MNAME may be set in both the S-element statement and the S model statement

Parameters in the element statement have higher priority


4-28© 2007

284-

S-Element Keywords (1/4)

nd1 nd2 … ndN: N signal nodes

nd_ref: reference node

MNAME: S model name

FQMODEL: SP model name

TYPE: parameter type

S: scattering parameter, default

Y: Y parameter

Zo: characteristic impedance value of the reference line

Default is 50 ohms

TSTONEFILE: name of the Touchstone file containing frequency-dependent data

Touchstone file must follow the file extension rule: filename.s#p, where # represents the dimension of the network

CITIFILE: Name of the citifile containing frequency dependent data


4-29© 2007

294-


FBASE: Base frequency used for transient analysis

Default value of FBASE is reciprocal value of the transient period (1/TSTOP)

S-parameters are converted in to time domain for transient analysis using IFFT (Inverse Fast Fourier Transform)

FBASE is the sampling frequency

Lower values of FBASE will give more accurate results but, will increase simulation time

Samples taken at f=0, FBASE,2*FBASE, 3*FBASE …, N*FBASE

– where N*FBASE < FMAX

Interpolation and extrapolation are used to obtain the sampled frequency points

If the S-parameter file contains a sufficient number of points, there will be no error introduced in the IFFT

If FBASE is set smaller than the reciprocal value of the transient period, the transient analysis will perform circular convolution, with the reciprocal value FBASE as the base period


4-30© 2007

304-


FMAX: Maximum frequency used in transient analysis

Maximum frequency point for Inverse Fourier Transformation

The default value of FMAX is reciprocal of the rise time of the voltage source used in the transient analysis

During the transient analysis, extrapolation is performed if sufficient frequency range is not specified in the S-parameter file

INTDATTYP: Data type for the linear interpolation of the complex data

RI – real, imaginary

MA – magnitude, angle

DBA – magnitude in dB, angle

PRACFAC: Precondition factor

Precondition is used to avoid infinite admittance matrix

Default = 0.75 (good for most cases)


4-31© 2007

314-


DELAYHANDLE: Delay handler

Activates the measurement of group delay for transmission-line type parameters

Group delay is the rate of change of phase with frequency, dθ/df

DELAYHANDLE = ON (or 1) to turn on delay handle

Default = OFF(or 0)

DELAYFREQ: Delay frequency

Sets the frequency point at which finite difference computation of group is carried out when DELAYHANDLE=1

Default = FMAX (good for most cases)

If the S-parameter file contains noisy data around the maximum frequency range, numerical errors may occur, then set DELAYFREQ to a value lower than FMAX

If DELAYHANDLE is set OFF but, DELAYFREQ is nonzero, the S-element will be simulated in delay mode

INTERPOLATION: The interpolation method

STEP: piecewise step

LINEAR: piecewise linear

SPLINE: b-spline curve fit


4-32© 2007

324-


HIGHPASS: Method to extrapolate higher frequency points

0: cut off

1: use highest frequency point

2: perform linear extrapolation using the highest 2 points

3: apply the window function to gradually approach the cut-off level (default)

LOWPASS: Method to extrapolate lower frequency points

0: cut off

1: use the magnitude of the lowest point

2: perform linear extrapolation using the magnitude of the lowest two points

DTEMP - Temperature difference between the element and the circuit in degrees Celsius Default=0

NOISE – Activate or de-activate thermal noise

Noise=1 – The element will generate thermal noise (default)

Noise=0 – The element will be considered noiseless


4-33© 2007

334-

S-Parameter Model Syntax

.MODEL Smodel_name S <N=dimension>

+ [FQMODEL=sp_model_name|TSTONEFILE=filename|

+ CITIFILE=filename]

+ <TYPE=[S|Y]> <Zo=[value|vector_value]>

+ <FBASE=base_frequency>

+ <FMAX=maximum_frequency> <PRECFAC=val>

+ <DELAYHANDLE=[1|0|ON|OFF]> <DELAYFREQ=val>

Smodel_name, S, and, FQMODEL are required

Only one model type, FQMODEL, TSTONEFILE or, CITIFILE should be specified

If more than one method is specified, the first one will be used and a warning message will be issued


4-34© 2007

344-

SP Model Syntax

.model modelname sp [N=val FSTART=val FSTOP=val

+ NI=val SPACING=val MATRIX=val VALTYPE=val

+ INFINITY=matrixval DC=matrixval

+ INTERPOLATION=val EXTRAPOLATION=val]

+ [DATA=(npts …)] [DATAFILE=filename]

SP models are generated when the default format is used for linear analysis

The *.sc0 file will contain .model lines for both SP

model and S model


4-35© 2007

354-

SP Model Keywords (1/3)

N: Matrix dimension (# of terminals), default=1

FSTART: starting frequency, default=0

FSTOP: final frequency (use for LOG or LIN spacing)

NI: number of frequency points per interval (only for DEC and OCT spacing)

Npts: number of data points

SPACING: Data sample spacing format:

LIN: uniform spacing

OCT: octave variation

DEC: decade variation

LOG: logarithmic spacing

POI: nonuniform spacing


4-36© 2007

364-

SP Model Syntax (2/3)

MATRIX: Matrix (data point) format:

SYMMETRIC: symmetric matrix, default

HERMITIAN: similar to symmetric but off-diagonal terms are complex-conjugate of each other

NONSYMMETRIC: A full matrix is specified

VALTYPE: data type of matrix elements:

REAL: real entry

CARTESIAN: complex number in real/imaginary format, default

POLAR: complex number in polar format (angles in radians)

INFINITY: Data point at infinity, not counted in number of points

DC: Data point at frequency=0, not counted in number of points:

Required to specify INFINITY for L&C

Required if there is no data point at frequency=0


4-37© 2007

374-

SP Model Syntax (3/3)

INTERPOLATION: interpolation scheme:

STEP: piecewise step (default)

LINEAR: piecewise linear

SPLINE: use B-spline

EXTRAPOLATION: extrapolation scheme:

NONE: no extrapolation is allowed

STEP: the last boundary point is used (default)

LINEAR: linear extrapolation using last two points

DATA: specifies data points:

LINEAR, OCT, DEC case: data=npts d1 d2 …

POI case: data=npts f1 d1 f2 d2 …


4-38© 2007

384-

SP Model Example

Example of a SP Model File:

.MODEL fmod sp N=3 FSTOP=30MegHz

+ DATA= 2

+ 1.0 0.0

+ 0.0 0.0 1.0 0.0

+ 0.0 0.0 0.0 0.0 1.0 0.0

+ 0.97409 -0.223096

+ 0.00895303 0.0360171 0.964485 -0.25887

+ -0.000651487 0.000242442 0.00895303

+ 0.0360171 0.97409 -0.223096

Values are expressed as real, imaginary


4-39© 2007

394-

Using S-Parameters Example

* run S-element in time domain

.option post

.tran 1n 80n

Vin in 0 DC=1v AC=1v pulse(0 1 0 5n 5n 10n 40n)

***** original circuit (for comparison) *****

L1 inOrg outOrg 5n

C1 outOrg 0 100p

Rin in inOrg 50

Rout outOrg 0 50

***** S-parameter representation *****

S1 s1in s1out 0 mname=Smodel

.MODEL Smodel S TSTONEFILE=lc.s2p TYPE=S FMAX=5e10

Rin1 in s1in 50

Rout1 s1out 0 50

.end


4-40© 2007

404-

Mixed Mode S-Parameters

Coupled transmission line schematic

Line A

Line B

V1

V3 V4

V2

i1

i3

i2

i4

port 1 port 2


4-41© 2007

414-

Mixed Mode Port Element

Required to extract mixed mode S-Parameters

.LIN internally sets the necessary drive mode

(common/differential)

For analyses other than the .LIN analysis, acts as a

differential driver

Positive nodes with half of their specified voltage

Negative nodes with a negated half of the specified voltage


4-42© 2007

424-

Extracting Mixed-Mode S-Parameters (1/3)

New keyword in the .LIN command

.LIN …

+ [ mixedmode2port = dd|dc|ds|cd|cc|cs|sd|sc|ss ]


4-43© 2007

434-


To print or probe parameters

S|Y|Z<xy>nm<(t)>

xy defines the port type D – differential

C – common

S – single-ended

If xy is not specified, the value of mixedmode2port will be used

nm is the port number

(t) is the type dB, m, p, r, i

Print/Probe Format Examples.print sdd11(db) sdd21(db) sdd22(db)

.print zds11(m) zds22(m)

.print yss11(m) yss22(m)


4-44© 2007

444-


Default and available values for mixedmode2port keyword depends on port configuration

For both port 1 and port 2 single ended

Available keyword: ss

Default: ss

For both port 1 and port 2 balanced

Available keywords: dd,cd,dc,cc

Default: dd

For port 1 balanced and port 2 single

Available keywords: ds,cs

Default: ds

For port 1 single and port 2 balanced

Available keywords: sd,sc

Default: sd


4-45© 2007

454-

Mixed Mode S-Parameter Example

*Mixed Mode S-Parameter

Example:

*Network

X1 in1 in2 out1 out2 0 diffnet

*Define Ports

P1 in1 in2 0 ac=1 Zo=50 port=1

P2 out1 out2 0 Zo=50 port=2

*Define .AC and .LIN

.ac lin 1000 1e7 1e10

.lin format=touchstone mixedmode2port=dd

:

.end


4-46© 2007

464-

Mixed-Mode S-Parameter Example Results (1/2)

! S(1,1) = SDD(1,1)

! S(1,2) = SDD(1,2)

! S(1,3) = SDC(1,1)

! S(1,4) = SDC(1,2)

! S(2,1) = SDD(2,1)

! S(2,2) = SDD(2,2)

! S(2,3) = SDC(2,1)

! S(2,4) = SDC(2,2)

! S(3,1) = SCD(1,1)

! S(3,2) = SCD(1,2)

! S(3,3) = SCC(1,1)

! S(3,4) = SCC(1,2)

! S(4,1) = SCD(2,1)

! S(4,2) = SCD(2,2)

! S(4,3) = SCC(2,1)

! S(4,4) = SCC(2,2)

In the S-parameter file, the following parameters are calculated at each frequency


4-47© 2007

474-

Mixed-Mode S-Parameter Example Results (2/2)

If you add the following statement to the netlist

.print sdd11(db) sdd21(db) sdd22(db)

Results

freq sdd11 sdd21 sdd22

db db db

1.0000e+07 -3.121e+01 -2.542e-01 -3.121e+01

2.0000e+07 -2.969e+01 -3.022e-01 -2.969e+01

3.0000e+07 -2.825e+01 -3.420e-01 -2.825e+01

4.0000e+07 -2.691e+01 -3.784e-01 -2.691e+01

5.0000e+07 -2.572e+01 -4.131e-01 -2.572e+01


4-48© 2007

484-

Using Mixed Mode S-Parameters (1/2)

S-element syntax

Sxxx p1+ <p1-> p2+ <p2-> ref mname=Smodel

Rules

Pn+ and pn- are the positive and negative terminals of the port n, respectively

If the port is mixed mode (balanced) then, both positive and negative terminal names are required

If the port is single ended then, only one terminal name is required

The port numbers must be in increasing order corresponding to the S-matrices notation


4-49© 2007

494-

Using Mixed Mode S-Parameters (2/2)

S-model syntax

.model Smodel S … [mixedmode=<0|1>]

+ [datatype=XiYjZk]

Keywords

Mixedmode – Sets type of S-parameter representation to use

1 – Mixed mode S-parameters

0 – (default) Standard S-parameters

Datatype – A string that defines the order of indices of the incident/reflected vectors (a and b)

Default datatype is a 2 balanced port network, D1D2C1C2

The string must be an array of letter and number pairs, “Xn”– ‘X’ = ‘D’ or ‘d’ indicates differential term

– ‘X’ = ‘C’ or ‘c’ indicates common term

– ‘X’ = ‘S’, ’s’, ‘G’ or ‘g’ indicates single (grounded) term

‘n’ = port number


4-50© 2007

504-

Lab 4: Using .LIN and S-Parameters


1. Use the .LIN

command to extract S-parameters.

2. Simulate a circuit containing an S-element.

3. Use the .LIN

command to extract noise parameters

Extract S-parameters

Use S-element

45 minutes

Transmission Lines and Field SolverHSPICE Advanced Topics

5-1© 2007

15-

Agenda

DAY

22224


IBIS6


S-Parameters and Linear Analysis


5-2© 2007

25-

Unit Objectives


Use W-element transmission lines

Use the field solver


5-3© 2007

35-

Introduction to Transmission Lines

What is a transmission line?

Who benefits from using transmission line analysis?

Overview:

Key circuits for digital systems analysis

The components:

Ideal transmission lines

Lossy transmission lines

Field Solver

S-Parameter


5-4© 2007

45-

Transmission Lines (1/4)

What is a transmission line?

A transmission line is a device intended to deliver an output signal at a distance from the point of signal input.

Any conductive pathway can show transmission line effects at high enough frequencies and/or long enough lengths.

Examples:

Microstrips

Coaxial cables

Ribbon cables

IC package interconnect

PC board traces


5-5© 2007

55-


Who benefits from using transmission line analysis?

System designers

IC designers:

High-speed digital

High-frequency analog

Interconnect

PC board designers

Anyone concerned about crosstalk and signal integrity


5-6© 2007

65-


Some key circuits for digital systems analysis:

Pin package models (for low pin count products)

14-64 pin DIP, PLCC, TSOP

RAM, ROM, EPROM, TTL, Glue-logic

Driver and receiver models

PGA package models (for high pin count applications)

100-600 pin gate arrays, microprocessors

PCB trace models (single and coupled lines)

Variable length model for standard trace widths

Top layer (microstrip)

Mid-layer (stripline)

Cable models - coax, twisted pair, ribbon, power

Miscellaneous models - chip decoupling capacitors, tantalum capacitor, resistors


5-7© 2007

75-


Some of the unwelcome effects caused by transmission line effects are:

Pulse rounding / distortion

Propagation delays

Crosstalk

Ringing

Ground bounce

Attenuation


5-8© 2007

85-

Transmission Lines in HSPICE

HSPICE supports 3 transmission line elements:

T: lossless, single signal only

U: lossy, allows up to 5 signal lines

W: lossy, more robust and accurate than U, no limit on number of signal lines

W-element is the recommended transmission line

U-element is supported solely for backward compatibility


5-9© 2007

95-

Ideal Transmission Lines: T-Element (1/2)

The ideal LOSSLESS transmission line:

Txxx in inref out outref ZO=val TD=val L=val

+ <IC=V1,I1,V2,I2>

or

Txxx in inref out outref ZO=val F=val

+ <NL=val> <IC=V1,I1,V2,I2>

Efficient at simulating long delay times

Defined by impedance and delay

Input difference delayed:

Differential mode only


5-10© 2007

105-

Ideal Transmission Lines: T-Element (2/2)

Cannot be coupled

Common mode is NOT modeled

Td(min)=Td*L*SCALE:

Caution: Can cause extremely long analysis times

Vint= V(out-refout)

t-TD+ (iout x Zo)

t-TD

+

-

in

inref

Voutt= V(in-refin)

t-TD+ (iin x Zo)

t-TD

+

-

out

outref


5-11© 2007

115-

W-Element Transmission Line

W-element based on recursive convolution:

Faster and more accurate compared to other approaches

Inputs frequency-dependent RLGC matrices

No limit on the number of coupled conductors

Frequency-dependent loss is accurately modeled

Accuracy does not depend on the transient speed, line length, amount of loss, coupling, number of lumps, or frequency dependence

1

Singlelumpedresistor

RLCGSegment

Sp

ice

c

on

vo

luti

on

m

od

el

‘U’ele

men

t

Welement

Rela

tive r

un

tim

e

.69 .92

687

23,513


5-12© 2007

125-

Comparison of U vs. W-Elements

-0.05

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0 10 20 30 40 50

U element (300 segments)

W element

Time (ns)

Tra

nsi

ent

Wav

efo

rms

(V)

spurious ringing (U element)


5-14© 2007

145-

W-Element RLGC Matrices

Five possible RLGC matrix formats:

RLGC Models

RLGCmodel – internally specified in a .model statement

RLGCFile – externally specified in a file

– Format is not as flexible as RLGCmodel format

» Scale suffixes (i.e. 1n = 1e-9) not supported

» File is order dependent

» Cannot include parameters

Fsmodel

Uses built-in field solver

Umodel

Supported for backward compatibility

TABLEMODEL

Frequency dependent table model


5-15© 2007

155-

RLGC File

W-element RLGC parameters:

N Number of Signal conductors(same as that in the element card)

Lo dc inductance matrix per unit length

Co dc capacitance per unit length

Ro (optional) dc resistance matrix per unit length

Go (optional) dc shunt conductance matrix per unit length

Rs (optional) Skin-effect resistance matrix per unit length

R(f) = Ro + √√√√fRs

Gd (optional) Dielectric-loss conductance matrix per unit length

G(f) = Go + fGd


5-16© 2007

165-

W-Element Accepts U-Model

The W-Element is extended to fully accept all U-model modes including:

RLGC input for up to five coupled conductors

Geometric input (planar or coax)

Measured parameter input

Skin effect

MONTE CARLO simulation

The above features provide backward compatibility with the U-element


5-17© 2007

175-

W-Element Syntax

Wxxx i1 i2 ... iN iR o1 o2 ... oN oR N=val L=val

+ <RLGCMODEL=name or RLGCFILE=name or

+ UMODEL=name or FSMODEL=name

+ or TABLEMODEL=name> [ INCLUDERSIMAG=YES|NO

+ FGD=val ] [ DELAYOPT=0|1|2|3 ]


5-18© 2007

185-

W-Element Keywords

Keywords

N - number of signal wires, excluding reference conductor

L - length of transmission line

Default unit is meters

INCLUDERSIMAG - Include imaginary term of skin effect

FGD - Cutoff frequency for dielectric loss

DELAYOPT - pre-process function added to increase W-element transient accuracy

DELAYOPT=0 deactivate (default)

DELAYOPT=1 activate

DELAYOPT=2 automatic determination

DELAYOPT=3 10GHz W-Element


5-19© 2007

195-

Benefits of DELAYOPT

Better accuracy

Captures harmonics for High Frequency

For much longer traces

Easier to use

No dependency on ‘risetime’ setting


5-20© 2007

205-

Optimal Number Of W-Element Segments

Single segment is optimum for most cases

Minimum number that ensures

Each segment has more than –40dB gain for critical harmonics

|Vout|/|Vin|>=0.01 (-40dB)

Too many segments can accumulate numerical error!


5-21© 2007

215-

AC vs. TRAN Comparison At 1GHzG

ain

|Vo

ut|

/ |V

in|

Length [inch]

AC Results

DELAYOPT=0

DELAYOPT=3

DELAYOPT=1

Lossy coupled PCB traces Golden Values

AC Results

DELAYOPT=3

Best match


5-22© 2007

225-

AC vs. TRAN Comparison At 5GHz G

ain

|Vo

ut|

/ |V

in|

AC Results

DELAYOPT=0

DELAYOPT=3

DELAYOPT=1


AC Results

DELAYOPT=3

Best match

Length [inch]


5-23© 2007

235-

AC vs. TRAN Comparison At 20GHzG

ain

|Vo

ut|

/ |V

in|

Length [inch]

AC Results

DELAYOPT=0

DELAYOPT=3

DELAYOPT=1


AC Results

DELAYOPT=3

Best match


5-24© 2007

245-

Using S-Parameters in Transmission Lines

Advantage of using S-parameter input for transmission lines:

Measured data is used directly in simulation

Efficiently validate field solver models

Exact representation of frequency dependent behavior

Compensate the lack of 3-D field solver in HSPICE


5-25© 2007

255-

Using S-Parameters in W-Element Keywords

Additional keywords required for both the W and S-elements

W-element keywords

SMODEL – specify S-model

NODEMAP – match W-element nodes to S-parameter ports

X - input terminal

– I – input

– N – near

Y - output terminal

– O – output

– F – far

Default NODEMAP

I1I2I3...InO1O2O3...On

S-element keyword

XLINELENGTH – required to indicate the line length of the extracted S-parameters


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Using S-Parameters in W-Element Syntax

W-element syntaxWxxx i1 i2 ... iN iR o1 o2 ... oN oR

+ N = val L = val

+ …

+ <SMODEL=Smodel_name > < NODEMAP=Xi...Yj... >

New S-model syntax.model Smodel S <N=dimension>

+ ...

+ <XLINELENGTH=value>

Example:W1 in gnd out gnd smodel=smodel

+ N=1 l=0.3 NODEMAP=i1o1

.MODEL smodel S TSTONEFILE=wline.s2p

+ xlinelength=0.3


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Using S-Parameters In W-element Guidelines

The keyword XLINELENGTH is required

Once the S-parameter file is extracted, XLINELENGTH value does not change, even when the W-element is scaled

Warning message will be generated if W-element has two different reference nodes for the input and output

S-element has only one reference node

W-element with S-parameter for input simulation is about 2X slower than RLGC table for input


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W-Element Thermal Noise Modeling

Calculates thermal noise values from

S-parameters

RLGC files for passive circuits

Thermal noise is equivalent to noise extracted using .LIN


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Thermal Noise Model Keywords

Additional keywords required to model thermal noise

DTEMP - Temperature difference between the element and the circuit in degrees Celsius

Default=0

NOISE – Activate or de-activate thermal noise

Noise=1 – The element will generate thermal noise (default)

Noise=0 – The element will be considered noiseless


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W-Element with Thermal Model Syntax

Wxxx i1 i2 ... iN iR o1 o2 ... oN oR N=val L=val

+ <RLGCMODEL=name or RLGCFILE=name or UMODEL=name

+ FSMODEL=name or TABLEMODEL=name>

+ [ DELAYOPT=0|1|2|3 ]

+ …

+ <DTEMP=val> $$ Specify element temperature

+ <NOISE=[1|0]> $$ thermal noise flag


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Field Solver

The field solver is a 2D field solver

Two methods used:

Boundary-Element Method

Filament Method

Used to extract frequency-dependent (skin-effect) resistance and inductance


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Filament Method

Divides the conductor into thin filaments

From the coupling of these filaments, the distributed magnetic coupling of the inside and outside conductor is derived

The filament method is used when the option COMPUTERS=yes is set in the .FSOPTIONS statement


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Modeling Geometry Basics

The number of layers is arbitrary

Conductor cross section can be of an arbitrary shape, including an infinitely-thin strip

The number of conductors is unlimited

The dielectric regions are planar or circular for polar field solver

The conductors must not overlap

Magnetic materials are not supported

The media must be homogeneous:

The solver uses the arithmetic average values of conductivities and loss tangents when the media is not homogeneous


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What Input does the Field Solver Require?

.MATERIAL:

Define the material properties for dielectrics and metals

.LAYERSTACK:

How materials are stacked and what the thickness of each layer is

.SHAPE:

Define the conductor shape

.FSOPTIONS:

Field solver options


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.MATERIAL Definition

.MATERIAL mname METAL|DIELECTRIC <ER=val>

+ <UR=val> <CONDUCTIVITY=val> <LOSSTANGENT=val>

Define a material as a dielectric or a metal

ER – dielectric constant:

Default er=1

UR – relative permeability:

Default ur=1

Ignored since magnetic materials are not supported

CONDUCTIVITY – Static field conductivity of a conductor or lossy dielectric:

Default is perfect conductor, conductivity=-1

LOSSTANGENT - Alternating field loss tangent of dielectric (tan δδδδ )


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Layerstack Rules

Layers are listed from bottom to top

Metal layers (ground) are located:

Only at the bottom or

Only at the top or

Both top and bottom

Layers are stacked in the Y direction:

The bottom of the layerstack is Y=0

Background material must be a dielectric:

AIR is the default

All conductors must be located above y=0


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.LAYERSTACK

.LAYERSTACK sname <BACKGROUND=mname>

+ <LAYER=(mname,thickness) ...>

Sname – layerstack name

Mname – material name

BACKGROUND = background dielectric

Thickness – layer thickness


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.SHAPE

.SHAPE sname Shape_Descriptor

Shape_Descriptor can be one of the following:

Rectangle

RECTANGLE WIDTH=val HEIGHT=val

Circle

CIRCLE RADIUS=val

Polygon

POLYGON VERTEX=(x1 y1 x2 y2 ...)

Strip

STRIP WIDTH=val


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.FSOPTIONS

.FSOPTIONS name <ACCURACY=HIGH|MEDIUM|LOW>

+ <GRIDFACTOR=1|val> <PRINTDATA=NO|YES>

+ <COMPUTEGO=YES|NO> <COMPUTEGD=NO|YES>

+ <COMPUTERO=YES|NO> <COMPUTERS=NO|YES>

PRINTDATA - print the output matrices

COMPUTEGO - computes the static conductance matrix

COMPUTEGD - computes the dielectric loss matrix

COMPUTERO - computes the DC resistance matrix

COMPUTERS - computes the skin-effect resistance matrix:

Invokes the filament method solver


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Field Solver .Model (1/2)

.MODEL mname W MODELTYPE=FieldSolver

+ LAYERSTACK=name <FSOPTIONS=name>

+ <RLGCFILE=name> <COORD=0|DESCART|1|POLAR>

+ CONDUCTOR=(SHAPE=name<MATERIAL=name>

+ <ORIGIN=(x,y)><TYPE=SIGNAL|REFERENCE|FLOATING>)…

LAYERSTACK - associated .LAYERSTACK name

FSOPTIONS - associated .FSOPTIONS name

RLGCFILE – output the RLGC matrices to the specified file

COORD – defines coordinate system

Default is 0 or DESCART

Polar or 1 enables polar field solver


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Field Solver .Model (2/2)

SHAPE - Conductor shape

ORIGIN - x y coordinates of the conductor

MATERIAL- Conductor material name

TYPE - Conductor types:

SIGNAL - a signal node

REFERENCE - the reference node

FLOATING - floating conductor


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Field Solver .Model Rules (1/2)

List of conductors must appear last

Signal conductors must be in the same order as the terminal list defined in the W-element

RLGC file is only printed if PRINTFILE=yes is set

in the .FSOPTIONS statement

If conductor material is not defined, the ideal conductor, PEC is used

If FSOPTIONS=name is not specified, default

options are used


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Field Solver .Model Rules (2/2)

Metal layers in the layerstack are treated as the reference node

Floating conductors are electrically disconnected

Reference conductors are electrically connected and correspond to the reference node in the W-element

Floating and reference conductors can appear in any order


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Partial Netlist for Field Solver Example

* Three traces in dielectric

W Element W1 in1 in2 in3 gnd out1 out2 out3 gnd FSmodel=cond3_sys N=3 l=0.5

* Start field solver definition

* Materials

.MATERIAL diel_1 DIELECTRIC ER=4.3

.MATERIAL diel_2 DIELECTRIC ER=3.2

*Shapes

.SHAPE rect_1 RECTANGLE WIDTH=0.35mm, HEIGHT=0.07mm

* Layerstack

.LAYERSTACK stack_1

+ LAYER=(PEC,1um),LAYER=(diel_1,0.2mm), LAYER=(diel_2,0.1mm)

* Option settings

.FSOPTIONS opt1 PRINTDATA=YES

* Model definition

.MODEL cond3_sys W MODELTYPE=FieldSolver, LAYERSTACK=stack_1, FSOPTIONS=opt1,

+ RLGCFILE=ex2.rlgc CONDUCTOR=(SHAPE=rect_1, ORIGIN=(0,0.201mm)),

+ CONDUCTOR=(SHAPE=rect_1, ORIGIN=(0.5mm,0.301mm)),

+ CONDUCTOR=(SHAPE=rect_1, ORIGIN=(1mm,0.301mm))


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Modeling Coaxial Lines

The field solver can be used to model coaxial lines

Keyword COORD=polar (or COORD=1) sets field solver to polar mode

The position of the conductor is defined in polar coordinates (radius, degrees)

Only one dielectric layer is permitted in the layerstack definition


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Coaxial Line Example

* Material List

.MATERIAL diel_1 DIELECTRIC ER=4

.MATERIAL copper METAL CONDUCTIVITY=57.6meg

* Shape List

.SHAPE circle_1 CIRCLE RADIUS=0.5m

* Layer Stack

.LAYERSTACK coaxial LAYER=(diel_1 11m) $ only one dielectric

* Field solver option

.FSOPTIONS myOpt printdata=yes computers=yes

+ computegd=yes computego=yes

* Field solver Model

.MODEL coax W MODELTYPE=FIELDSOLVER FSOPTIONS=myOpt

+ COORD=polar LAYERSTACK=coaxial, RLGCFILE=coax.rlgc

+ CONDUCTOR = (SHAPE=circle_1, MATERIAL=copper, ORIGIN=(0, 0))

* Circuit

W1 in1 0 out1 0 FSMODEL=coax N=1, L=1


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Shielded Twin Lead Example

* Material List

.MATERIAL diel_1 DIELECTRIC ER=4

.MATERIAL copper METAL CONDUCTIVITY=57.6meg

* Shape List

.SHAPE circle_1 CIRCLE RADIUS=0.5m

* Layer Stack

.LAYERSTACK coaxial LAYER=(diel_1 11m)) $ only one dielectric

* Field solver options

.FSOPTIONS myOpt printdata=yes computers=yes

+ computegd=yes computego=yes

* Field solver Model

.MODEL twin W MODELTYPE=FIELDSOLVER FSOPTIONS=myOpt COORD=polar

+ LAYERSTACK=coaxial, RLGCFILE=twin.rlgc

+ CONDUCTOR = (SHAPE=circle_1, MATERIAL=copper, ORIGIN=(4.5m, 0))

+ CONDUCTOR = (SHAPE=circle_1, MATERIAL=copper, ORIGIN=(4.5m, 180))

W1 in1 in2 0 out1 out2 0 FSMODEL=twin, N=2, L=1


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Lab 5: Transmission Lines and Field Solver


1. Simulate a circuit that contains a W-element.

2. Use the field solver to extract transmission line parameters.

Field Solver

Extraction

Transmission line

parameters

45 minutes

W-element


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What is IBIS?

IBIS = I/O Buffer Information Specification

IBIS is a standard for describing the analog behavior of the buffers of digital devices using plain ASCII text formatted data

IBIS files are not really models; they contain the data that will be used by the simulation tools behavioral models and algorithms

IBIS started in the early 90’s to promote tool independent I/O models for system level signal integrity work

http://www.eigroup.org/ibis/


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IBIS Model Characteristics

Fast simulation:

V / I / t relationships for only external nodes of the entire buffer

No circuit detail involved:

Not useful for circuit designers

Ideal for system level interconnect design

Hides process and IP

Package modeling

Electrical Board Description

Multi-stage buffer:

[Driver Schedule]


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IBIS Buffers

A basic IBIS model consists of:

Four I-V curves

Pullup & POWER clamp

Pulldown & GND clamp

Two ramps

dV/dt_rise

dV/dt_fall

Die capacitance

C_comp

Packaging

RLC values

For each buffer on a chip


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IBIS Model I-V Curves (1/2)

[Pulldown] referenced to [Pulldown Reference]:

Contains the difference of drive and receive (3-state) model I-V curves for driver driving low

Origin of the curve is usually 0V for normal CMOS buffers

[Pullup] referenced to [Pullup Reference]:

Contains the difference of drive and receive (3-state) model I-V curves for driver driving high

The origin of the curve is usually the supply voltage (Vcc or Vdd)


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IBIS Model I-V Curves (2/2)

[GND Clamp] referenced to [GND Clamp Reference]:

Contains the receive (3-state) model I-V curves

The origin of the curve is usually 0v (GND) for normal CMOS buffers

[Power Clamp] referenced to [Power Clamp Reference]:

Contains the receive (3-state) model I-V curves

The origin of the curve is usually at the supply voltage (Vcc orVdd)


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IBIS I-V Curve Rules of Thumb

Generally, I-V curves will be from –Vdd to 2*Vdd:

The theoretical max overshoot due to full reflection is 2X the signal swing

Current is positive when flows into the device

GND Clamp range is –Vdd to Vdd

Power Clamp range is Vdd to 2*Vdd


6-11© 2007

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Ramp and V-t Curve Measurements

The [Ramp] and [Rising Waveform], [Falling Waveform] keywords describe the transient characteristics of the buffer:

Information on how fast the pullup and pulldown transistors turn on and off with respect to time

Die capacitance (C_comp) is included

Package effects are not included


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Schematic of an I/O Circuit

Example of a simple link simulation using I/O buffer

IBIS Buffer model used to replace transistors

W-element used to model transmission line


6-13© 2007

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IBIS Buffer Basic Syntax

BufferName node1 node2 …nodeN

+ file=‘/fullpath/file.ibs’

+ model=‘modelName’

Number of nodes depends on types of buffer

Node sequence is predefined for each supported buffer type


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Supported Buffer Types and Syntax (1/2)

Input bufferB_INPUT nd_pc nd_gc nd_in nd_out_of_in

Output bufferB_OUTPUT nd_pu nd_pd nd_out nd_in [nd_pc nd_gc]

TrBi-state buffer_3STATE nd_pu nd_pd nd_out nd_in nd_en [nd_pc nd_gc]

Input/Output bufferB_IO nd_pu nd_pd nd_out nd_in nd_en V_out_of_in [nd_pc nd_gc]

Input ECL BufferB_INPUT_ECL nd_pc nd_gc nd_in nd_out_of_in

Output ECL BufferB_OUTPUT_ECL nd_pu nd_out nd_in [nd_pc nd_gc]

Tristate ECL BufferB_3STATE_ECL nd_pu nd_out nd_in nd_en [nd_pc nd_gc]


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Supported Buffer Types and Syntax (2/2)

Input-Output ECL Buffer B_IO_ECL nd_pu nd_out nd_in nd_en nd_out_of_in [nd_pc nd_gc]

Terminator Buffer B_TERMINATOR nd_pc nd_gc nd_out

Series Buffer B_SERIES nd_in nd_out

Series Switch Buffer B_SER_SW nd_in nd_out

Open Drain, Open Sink, Open Source Buffers Same as output buffer

Open drain and open sink buffers do not include pull-up circuitry but, always specify nd_pu

Open source buffers do not include pull-down circuitry but, always specify nd_pd

I/O Open Drain, I/O Open Sink, I/O Open Source Buffers Same as input-output buffer

I/O open drain and I/O open sink buffers do not include pull-up circuitry but, always specify nd_pu

I/O open source buffers do not include pull-down circuitry but, always specify nd_pd


6-16© 2007

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BUFFER Keyword

buffer = buffer_number | buffer_type

Buffer numbers INPUT = 1

OUTPUT = 2

INPUT_OUTPUT = 3

THREE_STATE = 4

OPEN_DRAIN = 5

IO_OPEN_DRAIN = 6

OPEN_SINK = 7

IO_OPEN_SINK = 8

OPEN_SOURCE = 9

IO_OPEN_SOURCE = 10

INPUT_ECL = 11

OUTPUT_ECL = 12

IO_ECL = 13

THREE_STATE_ECL = 14

SERIES = 15

SERIES_SWITCH = 16

TERMINATOR = 17


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BUFFER Keyword Example

Examples:

b2 nd_pu nd_pd nd_out nd_in nd_pc nd_gc

+ file = '.ibis/at16245a.ibs‘

+ model = 'AT16245_OUT‘

+ buffer = 2

b2 nd_pu nd_pd nd_out nd_in nd_pc nd_gc

+ file = '.ibis/at16245a.ibs‘

+ model = 'AT16245_OUT‘

+ buffer = output


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TYP Keyword

typ=typ|min|max|fast|slow

typ=0|-1|1|2|-2

If the value of typ is either typ, min, or max, it signifies a column in the IBIS file from which the data is extracted:

The default is typ=typ

If min or max data are not available, typ data is used

If the value of typ is fast or slow, combinations of the min and max data will be used

Typ can also be set to a number

-2Slow

2Fast

1Max

-1Min

0Typ


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Power On | Off

Power = On (default):

HSPICE connects buffer to power sources specified in IBIS file

Do not connect the external nodes (nd_pu, nd_pd, nd_pc, nd_gc) to voltage sources in the netlist

Do not use SAME external node name in different buffer

Power = Off:

Must connect the external nodes to voltage sources or through parasitic RLC elements to simulate power and ground bounce


6-20© 2007

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INTERPOL and NOWARN Keywords

INTERPOL:

Interpol=1|2

The I-V and V(t) curves need to be interpolated

The recommended default interpolation method is linear interpolation

interpol = 1

Interpol=2 uses quadratic bi-spline interpolation

NOWARN:

Suppresses warning messages from the IBIS parser

Do not use as the first keyword after the nodes list


6-21© 2007

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XV_PU and XV_PD Keywords

Enable state variable information of pullup and pulldown nodes:

xv_pu = state_pu

xv_pd = state_pd

State variable information can be printed:

.print v(state_pu) v(state_pd)


6-22© 2007

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RAMP_FWF and RAMP_RWF Keywords

Used to select which ramp or waveform data to use from the available data

Ramp_fwf controls falling waveforms or ramp:

ramp_fwf= 2|1|0

Ramp_rwf controls rising waveforms or ramp:

ramp_rwf= 2|1|0)

Default is ramp_fwf=2 and ramp_rwf=2:

The first two waveforms found in the model will be used

0 denotes use the ramp data specified in the model

1 denotes use one waveform:

If more than one waveform is available, the first waveform found in the model is used


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FWF_TUNE and RWF_TUNE Keywords

Control the algorithm for processing ramp and waveforms:

Default value is 0.1

Value range is from 0 to 1

Used only if ramp_fwf and ramp_rwf are 0 or 1:

fwf_tune = fwf_tune_value

rwf_tune = rwf_tune_value


6-24© 2007

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C_Comp

C_comp normally is connected between the output pin (input pin for input buffers)

C_comp can be split between the pullup, pulldown, power and ground clamps using the keywords:

c_com_pu=<value> c_com_pd=<value>

c_com_pc=<value> c_com_gc=<value>

If C_comp is split between the pullup, pulldown, power and ground clamps and the total exceeds the C_comp value specified in the IBIS model, HSPICE will continue the simulation and not give a warning


6-25© 2007

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IBIS Buffer Scaling Keywords

All I-V and V-t curves can be scaled:

Default for all scaling factors is 1

Values must be greater than 0

I-V curves scale buffer strength

V-t curves scale buffer delay, rise and/or fall time

Pullup and pulldown scaling factors:pu_scal=<value> pd_scal=<value>

Power and ground clamp scaling factors:pc_scal=<value> gc_scal=<value>

Rising and falling waveform scaling factors:rwf_scal=<value> fwf_scal=<value>

Supply voltage variation scaling factors:spu_scal=<value> spd_scal=<value>


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HSP_VER Keyword

The default is the current version of the HSPICE simulator

Use to set to previous version of the IBIS buffer

Syntax

hsp_ver = hspice_version


6-27© 2007

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Using the .IBIS Command (1/2)

A buffer is added to the netlist for every pin

Follows the signal_name and model_name defined

in the [Pin] list of the IBIS file

Buffers not created for POWER, GND or NC pins

The .IBIS command creates new buffers in the

netlist

Buffer_name = ‘cname’_‘pin_name’’

Cname is defined in the .ibis card in the netlist

Pin_name is defined by the [Pin] keyword in the .ibs file


6-28© 2007

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.IBIS Command Syntax (2/2)

Buffer pin names

Die side output node, if package model used:

'cname'_'pin_name'_o

Output node or input node for input buffers:

'cname'_'pin_name'

Enable node for buffers with enable pins:

'cname'_'pin_name'_en

Input node or outofin node for input buffers:

'cname'_'pin_name'_i

Outofin node for buffers other than input buffers:

'cname'_'pin_name'_outofin


6-29© 2007

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.IBIS cname

+ file=‘file_name’

+ component=‘component_name’

+ package=[3|0|1|2|]

+ pkgfile=‘pkg_file_name’

+ <optional keywords>

Keywords

Cname - Instance name of the .IBIS command in the netlist

File_name - IBIS model file name

Component - define using the [Component] keyword in the IBIS model file

Note: The component name and file name are case-sensitive


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Package – (optional, default is 3) defines package parasitics to be added to each pin

0 - does not use package parasitics

1 - use [Package] definition from the IBIS model file

2 - use [Pin] definition from the IBIS model file

3 – use the [Package Model] if it is defined in the IBIS model file

If [Package Model] is not defined, the [Pin] model will be used

If [Pin] is not defined, the [Package] model will be used

Package Model can be defined in either the IBIS file or the PKG file

Pkgfile – defines file containing package model file

Required if package model is not defined in the IBIS model file

Optional Keywords – any valid B-element optional keyword


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.IBIS Command Examples

Examples:.ibis memory

+ file = ’dram.ibs’

+ component = ’SIMM’

+ package = 2

.ibis p_test

+ file = ‘comp.ibs’

+ component = ‘cpu_133mhz_ff’

+ package = 3

+ pkgfile = ‘test.pkg‘

+ typ=typ nowarn


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Using the .PKG Command (1/2)

Syntax

.PKG pkgname

+ file = ’pkgfilename’

+ model = ’pkgmodelname’

Where

Pkgname – package card name

Pkgfilename – name of the .pkg or .ibs file that contains package models

Pkgmodelname – package model defined by [Define Package Model] in the .pkg file or [Package Model] in the .ibs file


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Using the .PKG Command (2/2)

Example:

.pkg fp1

+ file=‘ddr2tst.pkg

+ model=‘flatpack1’

The .PKG command automatically creates a series of either lumped RLCs or distributed RLCs

Package pin names

Nodes on the die side:

’pkgname’_’pinname’_dia

Nodes on the pin side:

’pkgname’_’pinname


6-34© 2007

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Using the .EBD Command

Describes a PCB or substrate that can contain components or other boards through a set of user visible pins

The Electrical Board Description (EBD) file describes the electrical connectivity

The .EBD command is used in conjunction with the .IBIScommand because the EBD file contains the reference designator of the component

HSPICE automatically creates lumped RLCs or W-elements to express the paths

Examples of use:

SIMM, DIMM Modules

MCMs

Processor Modules

Packages


6-35© 2007

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.EBD Command Syntax

.EBD ebdname

+ file = ’ebd_filename’

+ model = ’ebd_modelname’

+ component = ’ibisname:reference_designator’

+ <component = ’ibisname:reference_designator’> …

Keywords

Ebdname – ebd card name

Ebd_filename – name the .ebd file that contains the board description

Ebd_modelname – ebd model defined by [Begin Board Description] in the .ebd file

Ibisname - Name of the associated .IBIS command to identify IBIS buffer component

Reference_designator - Reference designator from the node subparameter of the [Path Description] in the ebd file

Note: The filename and modelname are case sensitive


6-36© 2007

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.EBD Example

.ebd mb1

+ file = ’memsimm.ebd’

+ model = ’16X8 SIMM’

+ component = ’mem:u21’

.ibis mem

+ file = ’mem16x8.ibs’

+ component = ’SIMM’

+ package=3

+ pkgfile=‘fpsim.pkg’

Pin names

Pins associated with the board will be named

ebdname_pin_name

Where Pin_name is the pin name given in the [Pin Description] of the ebd

file


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EBD Limitations

No coupling between paths

No correct modeling of differential signaling

Transmission line parameters have to be derived with respect to well defined reference planes

Insufficient connector modeling


6-39© 2007

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Using the .ICM Command

ICM = IBIS Interconnect Modeling Specification

“Interconnect” can be connector, cable, PCB traces or even an IC package

Defines structure as path between “sections”

Defines the electrical data for each section

Connector

Stub

ConnectorT-line

Described by

[Begin ICM Model]

…

(path description)

…

[End ICM Model]

Described by

[Begin ICM Section]

…

(RLGC or S-params)

…

[End ICM Section]

Connector

Stub

T-line


6-40© 2007

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ICM Structure (1/2)

Header Information

[Begin Header] and [End Header] keywords

Spec. Version

Filename and Revision

Date

Source, Notes, Disclaimer and Copyright

ICM Family

Description of model “family” or group

List of models in the “family”


6-41© 2007

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ICM Structure (2/2)

ICM Model Description

Type (SLM, S-parameter, MLM_*, etc.)

Signal-to-ground ratio & (optionally) reference Z

Tree Path Description

Links groups of signals through cascaded “sections” of model data

Describe one-to-one connections between sections and ports or endpoints of the interconnect

Allows “forks” with same number of conductors

Nodal Path Description

Links sections of model data through input & output nodes per section

Connections need not be one-to-one

– Allows internal “dangling nodes”

Nodal and Tree Path Descriptions are mutually exclusive


6-42© 2007

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Additional ICM Constructs

ICM Pin Map

Maps connector pins to Tree Path Descriptions

ICM Node Map

Maps connector pins to Nodal Path Descriptions

ICM Section

Data block for model sections

Data is in RLGC matrix or S-parameter format

Matrices include self-inductance, capacitance, conductance, loss, etc.

Similar format to IBIS package models

Each section is referenced by at least one Tree or Nodal Path Description


6-43© 2007

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ICM Swath

Allows minimal, economical description to be used for larger connectors or interconnects

Smaller electrical parameter matrices can be repeatedly mapped over a larger structure

Includes the [ICM Swath Description] and [ICM Swath Pin Numbers] keywords


6-44© 2007

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.ICM Syntax

.icm icm_name

+ file=‘filename.icm'

+ model=‘xxx‘

+ <swath = 1/2/3>

Keywords

File – specify particular ICM file to include

Model – specify which model in the file

Swath – indicate which method is used to expand swath matrix

1. Centering the swath around the pins of interest

2. Expand and Centering - Expanding the swath matrix into a larger swath matrix, centering both swaths about the paths of interest

3. Expand to full sized interconnect


6-46© 2007

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Multi-Lingual Model Support (1/2)

Supports SPICE or Verilog-A buffer model

Syntax:

B_SPICE node1 node2 node3 …

+ file='ibis_filename' model='model_name'

+ [nd_in=node_input]

+ [nd_en=node_enable]

+ [nd_outofin=node_out_of_in]

+ [typ=typ|min|max] [power=on|off]

+ [nowarn]

+ [para_begin para1=value1 para2=value2 …para_end]


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Multi-Lingual Model Support (2/2)

Buffer element nodes must map port names declared in [Ports] of [External Model]

The file of subcircuit listed in [Corner] of [External Model] must be manually included in netlist if the subcircuit is used by external model

Keywords para_begin and para_end are used to assign values to parameters which are declared in [External Model] with Verilog-A language


6-48© 2007

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Example

bspice Dri Out Vcc 0 Ven Rcv

+ file= 'extmdlva.ibs'

+ model= 'vatest'

+ nd_in=PlsV

+ nd_en=Vcc

+ nd_outofin=Oti

+ typ = typ

+ power=off

.ibs file(extmdlva.ibs) example

;

[External Model]

Language Verilog-A(MS)

;


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Component Calls for [External Circuit]

Support component calls for SPICE or Verilog-A formatted [External Circuit]

[External Circuit] is used to describe either buffer (similar to [External Model]) or interconnection inside component

The naming rule to probe a die node declared in Port_map of [Circuit Call] in a interconnection description:

‘cname’_’die_node_name’


6-50© 2007

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Name Limit Extension

The limit on IBIS filenames has been extended to 44 characters from the existing 24 characters

The model and signal name limit has been extended to 40 characters from the existing 20 characters


6-51© 2007

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Lab 6: IBIS Buffers

During this lab, you will use IBIS buffers and a transmission line to do a simple signal integrity analysis.

IBIS buffers

Transmission line

Signal Integrity analysis

45 minutes


2CS-

Synopsys Support Resources

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required)

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SolvNet Registration is Easy

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5CS-

Support Center: AE-based Support

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Access to internal support resources

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7CS-

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