huazhong normal university (ccnu) dong wang. introduction to the scalable readout system mrpc...
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Huazhong Normal University (CCNU)
Dong Wang
Introduction to the Scalable Readout System
MRPC Readout Specification Application of the SRS to CMB-MRPC Summary
Scalable Readout System
from: https://espace.cern.ch/rd51-wg5/default.aspx
---Introduction to the Scalable Readout System
Links instead of buses: more reliable, longer distance, more bandwidth
Scalable: small system= few links 1SRU, large system= N links
Merge 3 streams :single DTC link (Data, Trigger, Control )copper or fiber
Chip frontend exchangeable: keep the common readout system
Cheap & standard: frontend card chassis (Eurocard format), cables(CAT6 cable)
, fibers(850 nm MM fiber), network(10 Gigabit Ethernet)
DAQ system: robust, user-friendly and supported: Alice / DATE
Radiation protected on FEC and SRU FPGA chips
from: https://espace.cern.ch/rd51-wg5/default.aspx
---Introduction to the Scalable Readout System
from: https://espace.cern.ch/rd51-wg5/default.aspx
---Introduction to the Scalable Readout System
Overall time resolution σT = 80 ps. Occupancy < 5 % for Au-Au central
collisions at E=25 GeV/A. Space resolution ≤ 5 mm x 5 mm. Efficiency > 95 %. Pile-up < 5%. Rate capability > 20 kHz/cm2. Multi-hit capability (low cross-talk). Compact and low consuming electronics
(~65.000 electronic channels).
The TOF wall of the CBM experiment at FAIR 15-03-2007 D. Gonzalez-Diaz (GSI-Darmstadt)
---MRPC Readout Specification
One SRU can handle 2304 channels 1 SRU = 36 FEE = 36*8 TDC = 36 * 8*8
channel = 2304 channel ~65000 CBM/TOF channels = ~30 SRU
needed One SRU-DROC link can support 6Gb/s
data rate maximum One FEC-SRU link can support 200Mb/s
data rate via cat6 connection
---MRPC Readout Specification
from: https://espace.cern.ch/rd51-wg5/default.aspx
Architecture of the readout Chain
VIRTEX5 LXT
32 x RJ45 . . .
128 x SN65LVDS100
DCS mezzanine
54 LVTTL bus signals ( 32 data 16 addr. 3 cntr. 1 Rst )8 TTC signals (4 Broadcast, 2 strobes, 2x clock ) 5 other (2 x ADC, 1 ext. Inp, 2 RxTx )
128 x differential LVDS (256 I/O)
Con13 CON14
TTCrx
67 I/O signals
4 I/O signals
NIM input 2x
LVDS coax 4x bidir
4 diff LVDS ( 8 I/O)
88E 1111RJ45M
4 x SN65LVD
S10070 pin connectors70 pin connector
RJ45 DCS ethernet cableEthernet-DCS
Gigabit Ethernet
Optical SFP
1000 BASE- T ( 1 GB copper)
10 GBASE-S (10 GB* optical)
32 x Serial quad LVDS links (CAT6)
RJ45
40 MHz
25 MHz ICS844021 I-01
35 I/O signals
125 MHz
2 Rocket I/O
clock s
TPS74401
MIC29301 MIC29301
+1V
+3.3V+2.5V
- 5V
+3.3V, +4.2V, -12V
LDO area
Power
XCF32P-VOG48
FLASH
JTAGMolex 87831-1420
Clock outputs
AD7417
T+V monitoring
LT1175
. . .
TTC fiber (LHC)
PHYSICAL
9
---Application of the SRS to CMB-MRPC
from: https://espace.cern.ch/rd51-wg5/default.aspx
First version of SRU board layout finalized.
First success with porting of DATE software to Gigabit Ethernet .
---Application of the SRS to CMB-MRPC
from: https://espace.cern.ch/rd51-wg5/default.aspx
from: https://espace.cern.ch/rd51-wg5/default.aspx
---Application of the SRS to CMB-MRPC
A cards : custom chip adapter, ADC’s etcB cards: options, Extensions (LEDs, HV bias etc.)C-cards: larger, more complex extensions
A, B card: ~100x89 mm2
C-card: ~ 128x233 mm2
C-cards A,B-cards
Note: A,B and C cards can be mixed in single Eurocrate
---Application of the SRS to CMB-MRPC
A-card•4 HPTDC chips
FEC card
To be defined:• Connectors on A card to FEA• Power for FEA card• might also use larger C-card
---Application of the SRS to CMB-MRPC
The analog electronic Part can be designed based on GSI/CBM group collaborate, ALICE/TOF NINO/HPTDC tecnology, or collaborate with other groups.
CCNU is RD51 member Adapter card design and firmware of FEC will be
designed by CCNU FEC card and DATE Readout will supported by
RD51 Connectivity to FEA to be studied Existing ALICE readout system: DATE being
ported to GBE First version of SRU has finished design at CERN Upgrade version of SRU is under development at
CCNU