hv system for hyperk and e61 - agenda (indico) · hv system for hyperk and e61 a. evangelisti, a....
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HV system for HyperK and E61
A. Evangelisti, A. Boiano, G. De Rosa (INFN-Na)
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Constrains in HyperK and E61
• Severe power budgeting: 3-4W for the full mPMT
• Stable high voltage for all the dynodes.
• Voltage range (0 – 1500V)
A Cockcroft-Walton (CW) voltage multiplier circuit to
generate multiple voltages to drive the PMT dynodes
starting from the 5 voltage supply, as in Km3Net
(P. Timmer, E. Heine, H. Peek, JINST 5 (2010) C12049)
2 Andrea Evangelisti, INFN - Naples
HV Board block diagram
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Switch flayback
MCU ARM-32
14 stage moltiplication
Cockcroft-Walton
I/V meas
MCU:
ARM-32 STM32L011F4U
Ultra-low-power ARM Cortex-M0+
HV Range 0 - 1500 V
V full scale = 1500 V (resolution 0.4V)
I full scale = 16.5 μA (resolution 4 nA) O
n-O
ff
TTL RS232
12 bit DAC
Low pass filter
PMT
SPI
I/V control L
ow
pas
s fi
lter
Reference
voltage
Andrea Evangelisti, INFN - Naples
HV Board Caracteristics
Possible to change voltage ratio with a
simple mounting variant.
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HV Board prototypes
5
The first circuit shown those problems:
• High ripple on HV
• High noise on signal output
• Very fast transient on switch
Problem solved in second prototype
Two HV board prototypes have been realized
Andrea Evangelisti, INFN - Naples
HV Board Test
6 Andrea Evangelisti, INFN - Naples
HV circuit switching noise test
HV board V1 switching
noise @ 1500 V:
4mV( 6pC)
HV board V2 switching
noise @ 1500 V:
500μV(1pC)
HV Board Test
7 Andrea Evangelisti, INFN - Naples
HV circuit switching noise test
HV board V2 switching
noise @ 1500 V:
500μV(1pC)
Voltage ratio 3:1:1
Voltage ratio 3:2:1
HV Board improvment
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• Low pass filter for each dynode with particular attention to the last three stage.
• Separated ground between power supply and signal.
• Multilayer board studied to minimize the ground coupling.
• Particular attention to the placement of the component on the PCB to minimize
the length of the route that is a noise source.
• Low pass filter on the output of the Switch flayback transformer to smooth the
fast component of the switch.
• Dedicated circuit on the output of the switch mosfet to increase the rise time of
the pulse (from 50 ns to 140 ns)
Andrea Evangelisti, INFN - Naples
HV Board Test
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Rump up and
Rump down
observed with
Voltage&Current
monitor
Run observed
with
Voltage&Current
monitor
HV variation < 200mV
Current Voltage
Current Voltage
HV Board Caracteristics
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HV circuit power consumption
Maximum power dissipated for
single HV channel @1500V:
12.5 mW
In a mPMT with 26 channel:
26 12.5 mW = 325 mW
Andrea Evangelisti, INFN - Naples
HV Board Caracteristics
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Switch flayback: Power consumption 3.5 mW
V measurement:
Resistive load (1500 V) 2.2 mW
Operational amp 5 mW V meas I meas
Switch flayback
I measurement:
Operational amp 5 mW
POWER DISSIPATION(Worst case)
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8
10
12
14
16
0 200 400 600 800 1000 1200 1400 1600
Observed 3:2:1
Expected
Observed 3:1:1
Andrea Evangelisti, INFN - Naples
HV Board Test
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PMT & HV circuit signal test
Andrea Evangelisti, INFN - Naples
PMT + HV board
• 1200V
• 1300V
• 1400V
• 1500V
Voltage ratio 3:2:1
Conclusion
Two signal to set and two signal to control the HV
board
Second prototype for Voltage Multiplier Circuit
developed debugged and tested at INFN-Na.
Two possible voltage ratio(3:2:1 and 3:1:1)
HV circuit tested on a R12199-02 PMT and
compatible with the R14374 PMT.
13 Andrea Evangelisti, INFN - Naples