hw / sw implementation · 10/25/2013 · version 1.2 or any later version published by the free...
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![Page 1: HW / SW Implementation · 10/25/2013 · Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover](https://reader034.vdocuments.net/reader034/viewer/2022052003/6016043c0fa098036e5bd7f8/html5/thumbnails/1.jpg)
Young Won Lim10/25/14
HW / SW Implementation
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Young Won Lim10/25/14
Copyright (c) 2013 Young W. Lim.
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".
Please send corrections (or suggestions) to [email protected].
This document was produced by using OpenOffice and Octave.
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FSM Example (2A) 3 Young Won Lim10/25/14
HW Implementation
RTL design
Gate netlist
GDS
i0
i1s
sb
a0
a1
zU0
U1
U2
U3
D Q
clk
always @(posedge clk) if (load) q = d;
Logic Synthesis
Physical Synthesismask
ASIC (Application Specific Integrated Circuit)
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FSM Example (2A) 4 Young Won Lim10/25/14
NAND Gate
A Transistor Level A Layout
A Wafer processed
A Gate Level
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FSM Example (2A) 5 Young Won Lim10/25/14
SW Implementation
C++ / Java Code
Assembly Code
ELF
int i, s=0;for(i=0; i<10; ++i) s+= i;
Compile
Link with libraries
addi $s1, $0, 0add $s0, $0, $0addi $t0, $0, 10...
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FSM Example (2A) 6 Young Won Lim10/25/14
OS Kernel
● Process Management
● Interrupts
● Modes
● Memory Management
● Virtual Memory
● Multitasking
● Disk access
● File System
● Device Drivers
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FSM Example (2A) 7 Young Won Lim10/25/14
Interrupt
SWI
SWI handler
any inst
INT handler
CPU
INT
Software Interrupt Hardware Interrupt
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FSM Example (2A) 8 Young Won Lim10/25/14
Multi-tasking
A
● Time Slice● Time Sharing● Round Robin Scheduling● Context Switching
B
C
A
B
C
timer tick interrupt
Task A Thread
Task B Thread
Task C Thread
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FSM Example (2A) 9 Young Won Lim10/25/14
GPIO
D Q
D Q
● write to port address
● read from port address
● write to port direction register
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FSM Example (2A) 10 Young Won Lim10/25/14
HW (ASIC) & SW Implementations
RTL design
Gate netlist
GDS
Logic Synthesis
Physical Synthesis
C++ / Java Code
Assembly Code
ELF
Compile
Link with libraries
Parallelism is ensured by spatial allotment in a chip
Parallelism is ensured by temporal processing on a processor
HW (ASIC) SW
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FSM Example (2A) 11 Young Won Lim10/25/14
FPGA Architecture
A Logic Block
A Configurable Interconnection
FPGA (Field Programmable Gate Array)
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FSM Example (2A) 12 Young Won Lim10/25/14
1
0
1
0
0
0
0
1
Implementing Boolean Functions
0 1 1
0 1 0
0 0 1
0 0 0
1 1 1
1 1 0
1 0 1
1 0 0
inputs output
x y z
3
2
0
1
7
6
4
5
index
F
1
0
1
0
0
0
0
1
Size : 23 x 1
address3bits
Data 1 bit
LUT (Look up table)
A Logic Block
Memory
A Truth Table
Combinational Logic
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FSM Example (2A) 13 Young Won Lim10/25/14
Configuring Logic Blocks
A Logic Block
select
LUT SRAM cells
An 2-bit SRAM cell
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FSM Example (2A) 14 Young Won Lim10/25/14
Configuring Interconnections
An 1-bit SRAM cell
An 1-bit SRAM cell
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FSM Example (2A) 15 Young Won Lim10/25/14
HW (FPGA) Implementations
RTL design
Gate netlist *
“Programming File”
Logic Synthesis
Physical Synthesis
FPGA configuration information
HW (FPGA)
select
LUT SRAM cells
An 2-bit SRAM cell
An 1-bit SRAM cell An 1-bit SRAM cell
LUTs, FF, etc
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FSM Example (2A) 16 Young Won Lim10/25/14
HW (FPGA) & SW Implementations
RTL design
Gate netlist
“Programming File”
Logic Synthesis
Physical Synthesis
FPGA configuration information
HW (FPGA)
C++ / Java Code
Assembly Code
ELF
Compile
Link with libraries
SW
Machine Instructions of a processor
0100101...FPGA configuration information
10111011...
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Young Won Lim10/25/14
References
[1] http://en.wikipedia.org/[2] D.M. Harris, S. L. Harris, “Digital Design and Computer Architecture”