hybrid optical/digital processor for radar imaging keith frampton essex corporation 9150 guilford...

Hybrid Optical/Digital Processor for Radar Imaging

Keith Frampton

Essex Corporation

9150 Guilford Road

Columbia, MD 21046

301-953-7875

[email protected]

Pat Stover

Annapolis Micro Systems

190 Admiral Cochrane Dr. Suite 130

Annapolis, MD 21401

410-841-2514

[email protected]

23 September 2003

HEPC 2003 September 23, 20032

Problem Statement and Solution

• Problem:

– Projected BMD threat environment will have clutter and EMI

– LFM waveforms have limitations with these threats

– Desired advanced waveforms (chaotic, PRN*, …) are very processing intensive

• Solution:

– The advanced optical processor (AOP) generates range-Doppler images from advanced arbitrary waveforms

– AOP architecture incorporates:•Embedded optical signal processing•Embedded digital signal processing in FPGAs


Program Objectives

• Modernize the architecture, scaling to:– 1 GHz

– Real-time operation

– Full complex, single pass

– Store images in real-time to disk

• Compact rack stackable configuration

6U Card Cage

Power Supplies


AOP 2 Performance Characteristics

Pulse Width 10 sec to 50 msec

Pulse Repetition Interval (PRI)

Pulse Repetition Frequency (PRF)

100 usec minimum

10 kHz maximum

Center Frequency Tunable 5 GHz to 7 GHz (TBR)

Bandwidth (-3dB) 1 GHz

Stable Reference Frequency 10 MHz

Post-Compression Dynamic Range (peak to RMS noise)

66 dB

Spur Free Dynamic Range 85 dB for 128 coherently integrated pulses

Range Resolution 0.15 meters

SNR Loss vs. Range center 6 dB maximum @ +/- 76.7 meters relative to image center

Range Bins 1024 bins (+/- 512 about image center)

Range Extent 153 meters (+/-76.7 m about image center)

Range Sidelobes (Hamming weighting) -34 dB

Frequency Response 3 dB uncorrected; 1 dB corrected

RCS Repeatability +/- 0.1 dB

Phase Deviation from Linear in CPS +/- 5 degrees


Algorithm Functionality is Similar

OPT_97.CVS

op tica l do m a in d ig i ta l dom a in

A / DS u m

O ptica lF T

O ptica lF T

X

E qua l iza t ion ,w e igh t ing ,co m p en sa tion , &non- l inear ops .

X IF F T F F T

C o m p re s s e din ran ge

C o m p re s s e din D opp le r

R an ge -D op p le rM a p

R a d a rR e tu r n

R a d a rR e fe r e n ce

Optical/Digit al Implementa tion

Dig_96.CVS

A / D P r e s u m F F T

F F T

X

E qua l iza t ion

X IF F T F F T

C o m p re s s e din ran ge

C o m p re s s e din D opp le r

R an ge -D op p le rM a p

R a d a rR e tu r n

R a d a rR e fe r e n ce

Digital Implement ation


PROCFLW 2.CVS

Dop

ple

r,

R a d a r B a n d w id th(F re q u e n c y , f )

Tim

e,

t

( 1 -D F F T s )

A c o u s t o - O p t icU n i t

R e t u r n

R e f e r e n c e

D ig i ta l S ig n a lP r o c e s s in g U n it

( 2 D F F T )

C o m p l e xR a n g e

D o p p le rD a t a

p u l s ec o m p r e s s io n

R a n g e ,

(1 -D F F T s )

S = sp e c tru m o f ra d a r re tu rn s ig n a lR = s p e c t ru m o f ra d a r re fe re n ce s ig n a l

ST C S (f, t) PP(t,)

C A F()

Tim

e,

t

R a n g e ,

Process Flow

Cross power spectra vs. time

Correlator compresses pulse in range

FFT compresses pulses in Doppler

Frequency of each fringe is proportional to range.

Phase change over time is proportional to Doppler.


AOP2 Functional Configuration

RFFrontEnd

Optics Camera Electronics

Real-time Signal

ProcessingHardwareRadar

Reference Signal

Radar ReturnSignal

19” Rack-mountable 6U card cage

AOP-2 Control

PC

AOP2 Radar Receiver

Image Selection•Range•Range-Doppler•Range-Velocity*

* future capability


AOP 2 Top Level System Diagram

Controller

VME64

Ethernet

Signal Generator

RFFront-End Optics

RadarReturn

RadarCompressed

Images (future)

Processing &Control

External Triggers

Camera Data

Synchronize Trigger

Timing & Control

RF

Signals

AO Signals

Digital RadarReference

(Functional)

Frequency Reference

Radar Transmit Data

Fibre Disk

Fibre card

Fibre PMC

TektronixAWG710

Modular, Connectorized Components

Custom, Harris for Packaging

AMS, FPGA based

VMIC SBCWindows 2000C++, Labview,

Java


Radar Configuration with AOP2

Discrimination and Data Post

Processing

Radar Reference

Signal

Radar Transmit /

receive RF

Waveformgenerators

Std.Receiver

Range-compressed orRange-Doppler Images

Range-compressed

Image Radar ReturnSignal

Target Information

All part of AOP 2

Real-timeDisk

Future real-time interface

AOP 2ReceiverRadar Transmit

Signal


2 D F F T(D S P )

R a n g e -D o p p le r

M a p(C A F )

P h o tos e ns or A rra y(20 48 x 4 )

Fo u rie rT ran s fo rm

O pt ic s

La s e r

A co us to O p ticM o d u la to r (A O M )

Aegis1.CVS

R as te r D e tec to rO utp u t vs . T im e

C o m p le xd a ta

r(t) {A na lo g ra dar re fe renc e}s (t) {A na lo g rada r re tu rn s ig na l}

+-

+-

I

Q

Full Complex, Wideband Architecture

Analog (RF) Input (No A/D) Arbitrary waveforms

Digital output Real-time processing

Small size, weight and power Full complex images

Analog (RF) Input (No A/D) Arbitrary waveforms

Digital output Real-time processing

Small size, weight and power Full complex images

Do

pp

ler

Range

AOP2 Configuration

Range-Doppler Image


Optics Module Mated With Camera Module

Camera Card Connectors

Camera CardBragg Cell SMA Connectors

Optics Module

Optics Module Connector

Optics Processing Module

6U VME form factor


AOP2 Optics Module


System Calibrations and Corrections

• Calibrations and corrections are required at various points in the processing chain– Correct radar and processor response– Obtain optimum performance

RF Front End

Optical CPS

Return

Reference

RF Bragg data

(2, analog)

Camera data

CPS x phase

(2048, 4)

I/Q data

CPSI, CPSQ

(2048, 2)

Range compressed

images

RCII, RCIQ

(2048, 2)

Channel power Amplitude weighting Line phase correction

Deconvolutional filter

Range roll-Off

Range scale

Amplitude scale

Range Compression

FFT

I/Q Combine


AOP2 Hardware Configuration*

6U card cage- Controller card

- Optical module

- Post processing & Timing card

Power Meter

RF module

Power amplifiers

Programmable LOs for tunable RF front-end

Waveform generators

• Reference • Return

Real-time file system

UPS

* Including test equipment


AOP Production Conceptual Configuration

Size reduced from ½ rack in AOP2 demonstration to ½ single 6U chassis:

• AWGs reduced to single chip for PRN codes

• Synthesizers reduced to fixed LOs

• Amplifiers reduced to single card

• No output data storage, data sent to radar post processing in real time

OpticalReceiver RFFE Amps

Waveform generators

Amplifiers

RF front-end & LOs

Optical receiver

Camera & timing

Processing & control card

Controller


Post Processing & Control Subsystem (PCS)

VME64

6U Card

Cam

era

Dig

ital

Dat

a In

Cam

era

Co

ntr

ol

RF

& S

ign

al G

ener

ato

r

PE1

Virtex II

VME to PCI

Bridge

Wildstar II VME

Backplan

e I/O P2

88 88172172

172

PE1

Virtex II

Backplan

e I/O P0

Quad Fibre Channel 2 I/O

Bridge

Virtex II

168

FibreDis

k

Monitor

DiskSBC: Host

Processor

RadarCompressed

Images

2-3 6U Cards

PE1

Virtex II PE0

Virtex II

PE1

Virtex II PE2

Virtex II


PCS External Interfaces

RF

Controller

Optical Module

Camera

Processing &Control Subsystem

P_CLK

Vsync, Hsync

Signals that are connected with cables.

External Signals

Pixel data A(12)

Pixel data B(12)

Pixel data H(12)

5V-3VInterface

VME backplane signals

Pixel data C(12)

Pixel data D(12)

Pixel data E(12)Pixel data F(12)

Pixel data G(12)

Signals using VME user defined pins

C_trig

Pixel Tap A

Pixel Tap B

Pixel Tap H

Pixel Tap C

Pixel Tap D

Pixel Tap EPixel Tap F

Pixel Tap G

TEC_actual[5:0]

1AWG[1:0]

Range gate Trigger

Transmit Trigger

R Trig

T Trig

SW1, SW2[2:0] PD_current[7:0]

LD_current[7:0]

AWG

2AWG[1:0]

1AWG_ld, 2AWG_ld1AWG_trig, 2AWG_trigAWG_mrk

1Attn[5:0]

2Attn[5:0]

SW1, SW2[2:0]

1Attn[5:0]

2Attn[5:0]


WILDSTAR TM II for VME

Copyright Annapolis Micro Systems, Inc. 2002

PE 2VIRTEX TM II

XC2V 6000, 8000

Backplane I/OP0

Backplane I/OP2

DDR2SRAM

2, 4 MB

36 DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

36DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

36

36

36

ProgOsc

3

DDRSDRAM64 MB

32

88 88

PE 1VIRTEX TM II

XC2V 6000, 8000

I/O #1

DDR2SRAM

2, 4 MB

36 DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

36DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

36

36

36

ProgOsc

3

DDRSDRAM64 MB

32

168

PE 0VIRTEX TM II

XC2V 6000, 8000

I/O #0

DDR2SRAM

2, 4 MB

36 DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

36DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

36

36

ProgOsc

3

DDRSDRAM64 MB

32

168

172 172

36 36 3636

VME BUS

PCIController

32/64 Bits 33/66 MHz

32 32 32

32 32

172

PCI to VME Bridge

Flash

Flash Flash Flash

1616 16

MasterClock

Generator

PCLKMCLKICLK

16

DifferentialSingle Ended

Annapolis Micro Systems Wildstar II

FPGA based reconfigurable computing board


WILDSTARTM II for VME & Fibre Channel 2 I/O Card

WILDSTARTM II FPGA card Fibre Channel 2 I/O Card daughter card


Internal PCS Interfaces

PE2

• Collect Raw Data from detector

• Apply Correction

• Combine to get I & Q

• Update status for Controller

PE0

• Compute Range/Doppler Image

PE1

• Apply Correction to get CPS

• Compute Range Compressed Image

• Apply Correction to RCI

I & Q

CPS

CPS

RCI

Fibre Disk

RCI orRange/Doppler

CPS

Raw Camera Data


PE2 Data Processing

VME64

PA(11:0)

PB(11:0)

PC(11:0)

PD(11:0)

PE(11:0)

PF(11:0)

PG(11:0)

PH(11:0)

Pixel Data Memories

Camera CLK

Camera Controller

Controlsignals

I+(11:0)

I-(11:0)

Q+(11:0)

Q-(11:0)

H_syncV_sync

Trigger

Amplitude Weighting Memories

X

X

X

X-

-

I(15:0)

Q(15:0)

I+(15:0)

I-(15:0)

Q+(15:0)

Q-(15:0)

System Controller

Signal Generation & RF Front End Signals

Controller Optical Module PCS Signal Generation and RF Front End Internal

Complex Data

Raw Data


PE2 Allocated Memory Diagram


PE 2VIRTEXTM II

XC2V 6000, 8000

Backplane I/OP0

Backplane I/OP2

DDR2SRAM

2, 4 MB

36 DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

36DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

36

36

36

ProgOsc

3

DDRSDRAM64 MB

32

88 88

172 172

36

VME BUS

PCIController

PCI to VME Bridge

Flash

Flash

16

MasterClock

Generator

PCLKMCLKICLK

16


Direct connect to PE 1Direct connect to PE 0

Internal RAM: 16KB allocatediAmpWtTbl – 8192BqAmpWtTbl – 8192B

iRawPixelData – 2MB qRawPixelData – 2MB

iCalRawPixelData – 8KB qCalRawPixelData – 8KB


PE1 Functional Flow Diagram

PE2

Select Data

SourcedataSrcPE1

memClearPE1 Is memory full?Write Data to

Memory

Apply Line Phase Correction

linePhErrMeasupdatedLPCorr

PE0Apply

Deconvolutional Filter and FFT

Window

decvFiltWdwVect

yes

no

Is memory full? Write Data to Memory

no

yesFFT Processing

PE0

updatedDeconv

upLP(0)

upDF(0)

Interleave I,Q

iRngImgData(31:0)qRngImgData(31:0)

cpsData(31:0)

iCorrectedPreFFT

qCorrectedPreFFT

iPixelData

qPixelData

PE2

iData(15:0)qData(15:0)




PE 1VIRTEXTM II

XC2V 6000, 8000

I/O #1

DDR2SRAM

2, 4 MB

36 DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

36DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

36

36

36

ProgOsc

3

DDRSDRAM64 MB

32

168

172

36

VME BUS

PCIController

32/64 Bits 33/66 MHz

32

32

172

PCI to VME Bridge

Flash

Flash

16

MasterClock

Generator

PCLKMCLKICLK

16


Internal RAM: 24KB allocatedlinePhErrMeas – 8192BdecvFiltWdwVect – 8192BrangeRollOffVect – 8192BDirect connect to PE 0

Direct connect to PE 2

iPixelData – 1MB qPixelData – 1MB

iCorrectedPreFFT – 1MB qCorrectedPreFFT – 1MB

iRngImage – 2MB qRngImage – 2MB


PE0 Functional Diagram

PE1RangeData

PE2CPSData

memClearPE0Constant

Write toStatic

Memory0 & 1

CalculateMemory

Address byColumn

ReadStatic

Memory0 & 1

CalculateMemory

Address byRow

ReadLADMuxBlock Ram

MultiplyData ByDopplerWindow

DopplerFFT

CalculateMemory

Address byColumn

memClearPE0Constant

Terminate

0

1

DeinterleaveData

InterleaveData

rngRollOffVect

iRngImage qRngImage

doppFFTWdw

Terminate

Write toStatic

Memory2 & 3

RngDoppImage(I & Q)

dataSrcPE0Register

ReadLADMuxBlock Ram

MultiplyData By

Range Roll-OffVector

Write toStatic

Memory4 & 5

0

1

CalculateMemory

Address byRow

ReadStatic

Memory2 & 3

FirstData

in Pulse

1

0

Write toDynamicMemory

iRng

qRng

iRngImgData (31:0)qRngImgData (31:0)

icpsData (31:0)qcpsData (31:0)

iRngDoppData (31:0)qRngDoppData(31:0)

iImageData (31:0)qImageData (31:0)

pulseHeader (63:0)

MakeCycle

Cnt/CalHeader

PE1Cal

upLP (0)upDF (0)

Sift

procModeConstant

FibreDisk




PE 0VIRTEXTM II

XC2V 6000, 8000

I/O #0

DDR2SRAM

2, 4 MB

36 DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

36DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

DDR2SRAM

2, 4 MB

36

36

ProgOsc

3

DDRSDRAM64 MB

32

168

172

36 36

VME BUS

PCIController

32/64 Bits

32

32

PCI to VME Bridge

Flash

Flash

16

MasterClock

Generator

PCLKMCLKICLK

16


172 Direct connect to PE 1

Direct connect to PE 2

iRng0 – 2MB

iRngDoppImage – 2MB

qRng0 – 2MB

qRngDoppImage – 2MB

Internal RAM: 2KB allocatediDoppFFTWdw – 1024BqDoppFFTWdw – 1024B

RngDopp – 8MB

iRng1 – 2MB qRng1 – 2MB


Corefire Example


PCS Testing: CoreFire Debugger

CoreFireTM Application Debugger includes windows for

monitoring and manipulating data flow


Wildstar II FFT Example

FFT Example Scenario

• CoreFire project for PE1Data read from memory on Wildstar II board

FFT operation

Data written to memory on Wildstar II board

• Java programData read from file

Data written to memory on Wildstar II board

Data read from memory on Wildstar II board

Data written to file

• CoreFire DebuggerKicks off the Wildstar II board processing

Memory and register viewers show data

during the processing

• IView ToolCompare output data file with

expected results


Wildstar II FFT Example

Peak to RMS = 139 dB

FFT done in SW FFT done on Wildstar board

Scale and Subtract

(Magnitude)


Conclusions

• Essex has been able to implement an extremely complex, computationally intensive radar processing task in:– Embedded optical hardware and

– Embedded DSP/FPGA hardware

• This approach saves space, development time, software, development costs and maintenance costs.

• The AOP hardware allows the use of new arbitrary classes of waveforms for improved ballistic missile discrimination.


Wrap-up / Questions

hybrid optical/digital processor for radar imaging keith frampton essex corporation 9150 guilford...

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