hybrid pwm update method for time delay compensation in … · 2017. 2. 1. · a novel hybrid...
TRANSCRIPT
Hybrid PWM Update Method for Time Delay Compensation in Current Control Loop
Seungryul Moon
Dissertation submitted to the faculty of the Virginia Polytechnic Institute and State University
in partial fulfillment of the requirements for the degree of
Doctor of Philosophy In
Electrical Engineering
Jih-Sheng Lai, Chair Rolando P. Burgos
William T. Baumann Louis J. Guido
Steve Southward
February 1st, 2017 Blacksburg, Virginia
Keywords: delay compensation, hybrid PWM update, deadbeat control,
high-speed ac drives, immediate PWM update, delayed PWM update
Copyright 2017, Seungryul Moon
Hybrid PWM Update Method for Time Delay Compensation in Current Control Loop
Seungryul Moon
Abstract
ABSTRACT
A novel hybrid pulse-width modulation (PWM) update method is proposed to eliminate
the effect of the one-step control time delay Td-one without losing the full duty cycle range.
Without the Td-one to cause linear phase shifts that limit the control bandwidth and affect closed-
loop stability, a very high quality digital current control can be achieved, such as a high closed
current loop bandwidth, strong robustness against disturbances, ability to reach a very high
fundamental frequency compared to switching frequency, etc.
In a conventional digital control implementation, a sampling period (Tsamp) is allocated
for the execution of samplings and computations, and the update of PWM outputs is delayed
until the beginning of the following sampling period. This delayed PWM update method is the
cause of the Td-one. Instead of the delayed PWM update, if the PWM outputs are updated
immediately after algorithm computations, then the effect of the Td-one can be eliminated;
however, the computation time delay Td-comp from the current sampling instant through algorithm
computations to the PWM update instant causes a reduced duty cycle range. Each of these two
conventional PWM update methods has some shortcomings.
A hybrid PWM update method is proposed to circumvent the aforementioned
shortcomings and to incorporate only the advantages. The proposed method improves the
performance by updating the PWM outputs multiple times during a Tsamp, whereas the PWM
outputs are updated only one time during a Tsamp in the conventional methods. In spite of the
simplicity of the proposed method, the performance improvements in stability, robustness and
response characteristics are significant. On the other hand, the proposed method can be easily
applied to many PWM based digital controls because of its simplicity.
Additional to the hybrid PWM update method, a hybrid control method is proposed to
optimize the sequence of control operations. It maximizes the current loops’ robustness and
minimizes the delay from the sampling of outer control loops’ variables, such as voltage and
speed, to the duty cycle update instant. The minimum delay enables the maximization of the
outer control loops’ bandwidth. Additionally, a corrective neutral offset voltage injection method
is proposed to correct small PWM output deviations that may occur with the hybrid PWM update
method.
Utilizing a three-phase voltage source inverter with a permanent magnet synchronous
machine as the platform, a deadbeat current control and a high speed ac drive experiment have
been conducted to demonstrate the feasibility and validity. Notable results include a closed
current loop response of one Tsamp with the deadbeat control and a 500 Hz current fundamental
frequency with 1 kHz switching frequency in the high speed ac drive.
Hybrid PWM Update Method for Time Delay Compensation in Current Control Loop
Seungryul Moon
General Audience Abstract
GENERAL AUDIENCE ABSTRACT
A novel hybrid pulse-width modulation (PWM) update method is proposed to improve
the performance of power electronics applications. PWM is a modulation technique that is
typically used in power electronics to encode a control signal. A delayed PWM update method
and an immediate PWM update method are two conventional PWM update methods, and each of
these conventional methods has shortcomings.
The delayed PWM update method, as the name implies, delays the update of PWM
outputs until the beginning of next cycle. This delayed update ensures that PWM signals have the
full range; however, it causes an update delay in control loops, which degrades the control loops’
response speed. On the other hand, the immediate PWM update method, as the name implies, the
update of PWM outputs is executed as soon as the control signals are available to be updated.
This immediate update eliminates the update delay, but it loses the full range of PWM signals.
The hybrid PWM update method is proposed to combine the delayed and immediate
PWM update methods, in which the combination can eliminate the update delay without the loss
of the full signal range. The proposed method is quite simple; however, the performance
improvements in stability, robustness, and response characteristics are significant. On the other
hand, the proposed method can be easily applied to many PWM based digital controls because of
its simplicity.
The proposed method is implemented on a three-phase voltage source inverter with a
permanent magnet synchronous machine, and the feasibility and validity are demonstrated with a
deadbeat current control algorithm and a high speed ac drive experiment. In the experiments, a
very high quality digital current control is achieved, such as a high closed current loop
bandwidth, strong robustness against disturbances, ability to reach a very high fundamental
frequency compared to switching frequency, etc.
v
Dedication
To my parents
Young-chul Moon and Hyun-sook Kim
To my wife
Jaeyeon Choi
vi
Acknowledgements
First and foremost, I would like to express my most sincere gratitude to my advisor and
mentor Dr. Jih-Sheng Lai. Throughout my master’s and PhD degrees, he have advised me with
enthusiasm, insight, and wisdom. He is the most outstanding engineer that I know, and his
relentless pursue of engineering excellence has inspired me do the same. He has taught me many
lessons not only in power electronics engineering, but also many facets of life. Thank you.
I would like to thank Dr. Rolando Burgos, Dr. William Baumann, Dr. Louis Guido and
Dr. Steve Southward for serving as the members of my committee, and for their interest,
suggestion, and kind support for this work.
I would like to thank Dr. Zhen Yu, Mr. Ramesh Ramamoorthy, Mr. Sam Sabapathy and
Mr. Richard Poley at Texas Instruments for their valuable comments, feedbacks and advices
during our conference calls. Without their comments, this dissertation would not have been as
complete as it is.
It has been a great pleasure to work with the colleagues at the Future Energy Electronics
Center (FEEC). My thanks go to Mr. Yousef Alabdrabalnadi, Ms. Rachael Born, Dr. Honnyong
Cha, Dr. Baifeng Chen, Mr. Bo-yuan Chen, Dr. Chien-Liang Chen, Mr. Rui Chen, Dr.
Younghoon Cho, Dr. Jungmuk Choe, Dr. Zakariya Dalala, Mr. Jason Dominic, Ms. Le Du, Mr.
Eric Faraci, Dr. Bin Gu, Mr. Chris Hutchens, Mr. Nathan Kees, Mr. Gary Kerr, Mr. Alexander
Kim, Mr. Jongwan Kim, Dr. Jong-Woo Kim, Ms. Hyun-Soo Koh, Dr. Ahmed Koran, Mr.
Thomas LaBella, Dr. Yen-Shin Lai, Mr. Wei-Han Lai, Mr. Moonhyun Lee, Dr. Qingqung Ma,
Mr. Tom Mao, Mr. Hidekazu Miwa, Ms. Erin Puckett, Dr. Pengwei Sun, Ms. Yu Wei, Ms.
vii
Jinghui Yan, Mr. Chih-Shen Yeh, Dr. Ben York, Ms. Hongmei Wan, Dr. Zaka Ullah Zahid, Dr.
Lanhua Zhang, Ms. Xiaonan Zhao, Dr. Cong Zheng and Mr. Bo Zhou.
With my heartfelt respect, I thank my parents, Mr. Young-chul Moon and Ms. Hyun-sook
Kim. Their everlasting love, support, encouragment, and patient kept me strong throughout my
PhD years. I thank my sister, Ms. Seunghee Moon and her family, who have showed their
support and love. I thank my uncle and aunt, Mr. Gerard Thompson and Ms. Ok-Hui Thompson,
for their support and love. They are just as important as my parent in making who I am today. I
thank all of my extended family. Too many to name them all, but my deepest appreciation
belong to all of my family. Finally, I would like to specially thank my wife, Ms. Jaeyeon Choi.
Her acts of kindness, love, and compassion have rubbed off on me, and I am a better person
because of her.
The PhD years have been long and hard at times, but it was mostly great and meaningful
because of all people around me. Thanks to all friends and colleagues that have given me your
support and encouragement in my dissertation work. If I have forgotten to mention you; know
that your time, effort and perspective have been much appreciated. Thank you, all!
January 16, 2017 in Blacksburg
Seungryul Moon
viii
Table of Contents
Abstract ................................................................................................................................. ii
General Audience Abstract ......................................................................................................... iv
Dedication ................................................................................................................................ vi
Acknowledgements ..................................................................................................................... vii
Table of Contents ......................................................................................................................... ix
List of Figures ............................................................................................................................. xiv
List of Tables ............................................................................................................................ xviii
List of Abbreviations ................................................................................................................. xix
Nomenclature ...............................................................................................................................xx
Chapter 1 Introduction................................................................................................................1
1.1 Motivation .....................................................................................................................1
1.2 Overview of the current controls in power electronics .................................................4
1.2.1 Dc-dc converters ......................................................................................................4
1.2.2 Ac motor drives........................................................................................................5
1.2.3 Utility grid tied inverter system ...............................................................................5
1.2.4 Uninterruptable power supplies ...............................................................................6
1.2.5 Power factor correction ............................................................................................7
1.3 Design objective: High closed current loop bandwidth ................................................8
ix
Chapter 2 Existing Techniques and Literature Review ...........................................................9
2.1 Current sampling methods ...........................................................................................10
2.2 Conventional PWM update methods ...........................................................................13
2.2.1 Immediate PWM update method ...........................................................................13
2.2.2 Delayed PWM update method ...............................................................................18
2.2.3 Variety of the delayed and immediate PWM update methods and digital delays .19
2.3 Delays in the current loop ...........................................................................................22
2.4 Literature reviews ........................................................................................................24
2.4.1 Definition of bandwidth .........................................................................................24
2.4.2 Handling of time delays .........................................................................................24
2.4.3 Implementation platform .......................................................................................25
2.4.4 Control design methods .........................................................................................26
2.4.5 Previous novel PWM update methods ...................................................................27
2.4.6 Multi-sampling and current sampling at other than carrier peaks .........................31
Chapter 3 Hybrid PWM Update Method ................................................................................32
3.1 Plant modeling and control design with immediate PWM update method .................34
3.1.1 Plant modeling .......................................................................................................34
3.1.2 Controller design ....................................................................................................35
3.1.3 Controller gain deign method ................................................................................36
3.1.4 Control computation sequence ...............................................................................37
3.1.5 Modulation index limitation ..................................................................................38
3.1.6 Application example: one-cycle deadbeat control method ....................................39
x
3.2 Plant modeling and control design with delayed PWM update method .....................40
3.2.1 Plant modeling and conventional control design ...................................................40
3.2.2 Predictive control design........................................................................................42
3.2.3 Control computation sequence ...............................................................................44
3.2.4 Application example: two-cycle deadbeat control .................................................45
3.3 Stability and robustness analysis of the conventional and predictive controls ...........46
3.3.1 Current controller open-loop crossover frequency (ωcc) selection ........................46
3.3.2 Theoretical stability range with respect to the parameter uncertainty ...................50
3.3.3 Robustness against inverter non-linear characteristics ..........................................55
3.4 Hybrid PWM update method ......................................................................................58
3.4.1 Proposed hybrid PWM update method ..................................................................58
3.4.2 Non-ideal control computation sequence ...............................................................60
3.4.3 Improved ideal control computation sequence ......................................................62
3.5 PWM output behaviors of hybrid PWM update method .............................................64
3.5.1 Ideal case of when both mi(udy* ) and mi(uim* ) are optimal .......................................67
3.5.2 Non-ideal case of when mi(udy* ) is sub-optimal ......................................................69
3.5.3 Faulty case of when mi(uim* ) is sub-optimal ...........................................................70
3.5.4 Non-ideal case of when both mi(udy* ) and mi(uim* ) are sub-optimal ........................71
3.5.5 Mitigation of PWM deviation during second half of Tsamp ....................................72
3.5.6 Application to double-sampling method ................................................................73
3.6 Stability and robustness analysis of hybrid PWM update method ..............................75
3.6.1 Robustness evaluation based on PWM output inspections ....................................75
3.6.2 Block diagram of hybrid control ............................................................................76
xi
3.6.3 Modeling of the hybrid control ..............................................................................77
3.6.4 Application example: hybrid deadbeat control ......................................................78
3.6.5 Stability boundary of the hybrid deadbeat control .................................................78
3.7 Corrective duty cycle manipulation for PWM output deviation compensation of the
hybrid PWM update method .......................................................................................82
3.7.1 Arbitration of corrective method ...........................................................................83
3.7.2 Corrective method 1 ...............................................................................................85
3.7.3 Corrective method 2 ...............................................................................................88
3.7.4 Advantages and disadvantages ..............................................................................94
Chapter 4 Applications of the Hybrid PWM Update Method ...............................................95
4.1 Test setup .....................................................................................................................95
4.2 Deadbeat control of three-phase ac drives...................................................................97
4.2.1 Literature review on deadbeat controls ..................................................................97
4.2.2 Experimental results...............................................................................................99
4.3 High speed control of three-phase ac drives .............................................................115
4.3.1 Literature review on high speed ac drives ...........................................................115
4.3.2 Gain design and stability analysis ........................................................................117
4.3.3 Experimental results of high speed ac drives .......................................................120
Chapter 5 Conclusion and Future Direction .........................................................................124
5.1 Conclusion .................................................................................................................124
5.2 Contribution ...............................................................................................................128
5.3 Future direction .........................................................................................................129
xii
Appendix A Plant modeling ....................................................................................................130
Appendix B Scalar representation of the current loop ........................................................132
Appendix C Increase of the modulation index limitation by neutral offset voltage
manipulation .......................................................................................................133
References ..............................................................................................................................136
xiii
List of Figures
Fig. 1.1. Simplified control block diagrams of dc-dc converter systems ...................................... 4
Fig. 1.2. Simplified control block diagram of a three-phase ac motor drive system ..................... 5
Fig. 1.3. Simplified control block diagram of a utility grid-tied inverter system .......................... 5
Fig. 1.4. Simplified control block diagram of a uninterruptable power supply system ................. 6
Fig. 1.5. Simplified control block diagram of a power factor correction system .......................... 7
Fig. 2.1. Current sampling method with a uniformly sampled PWM using a triangular carrier . 10
Fig. 2.2. Varieties of sampling methods ...................................................................................... 12
Fig. 2.3. Simplified timing diagram of immediate PWM update method ................................... 13
Fig. 2.4. Duty cycle range of immediate PWM update method .................................................. 14
Fig. 2.5. Comparator behaviors during immediate PWM update method ................................... 16
Fig. 2.6. Simplified timing diagram of delayed PWM update method ........................................ 18
Fig. 2.7. Varieties of delayed and immediate PWM update methods .......................................... 19
Fig. 2.8. Different delays in a current loop .................................................................................. 22
Fig. 2.9. “Two-polarity PWM method” of [14] ........................................................................... 27
Fig. 2.10. “Dual sampling mode” of [15] .................................................................................... 28
Fig. 2.11. “Area compensation scheme” of [32] .......................................................................... 29
Fig. 2.12. “Asymmetric PWM method” of [14] .......................................................................... 30
Fig. 3.1. Three-phase voltage source inverter and a generic three-phase RLE load model ......... 32
Fig. 3.2. Overall cascade control scheme with a surface PMSM ................................................ 32
Fig. 3.3. Current control loop without considering Td-one ............................................................ 35
Fig. 3.4. Timing sequence without considering Td-one .................................................................. 37
xiv
Fig. 3.5. Timing diagram of one-cycle deadbeat control ............................................................. 39
Fig. 3.6. Conventional current control loop with considering Td-one ............................................ 41
Fig. 3.7. Predictive current control loop with considering Td-one ................................................. 42
Fig. 3.8. Timing sequence with considering Td-one ....................................................................... 44
Fig. 3.9. Timing diagram of two-cycle deadbeat control ............................................................. 45
Fig. 3.10. Open-loop Bode plots of TI(z), TI_d-one(z), and TI_pred(z) .............................................. 47
Fig. 3.11. Closed-loop Bode plots of GI(z), GI_d-one(z) and GI_pred(z) .......................................... 48
Fig. 3.12. Eigenvalue migration patterns of GI(z) when L^ is varied ............................................ 52
Fig. 3.13. Eigenvalue migration patterns of GI_d-one(z) when L^ is varied ..................................... 52
Fig. 3.14. Eigenvalue migration patterns of GI_pred(z) when L^ is varied ...................................... 53
Fig. 3.15. Current control loops ................................................................................................... 56
Fig. 3.16. Conventional PWM update methods ........................................................................... 58
Fig. 3.17. Hybrid PWM update method ....................................................................................... 59
Fig. 3.18. Non-ideal control sequence of the hybrid PWM update method ................................ 60
Fig. 3.19. Ideal control sequence of the hybrid PWM update method ........................................ 62
Fig. 3.20. Three-phase VSI and a generic three-phase RLE load model ..................................... 64
Fig. 3.21. Block diagram of operations from synchronous reference frame u* to PWM outputs 65
Fig. 3.22. PWM outputs of the ideal case that both mi(udy* ) and mi(uim* ) are optimal ................... 67
Fig. 3.23. Non-ideal case that mi(udy* ) is sub-optimal .................................................................. 69
Fig. 3.24. Faulty case that mi(uim* ) is sub-optimal ........................................................................ 70
Fig. 3.25. Non-ideal case that both mi(udy* ) and mi(uim* ) are sub-optimal ..................................... 71
Fig. 3.26. Additional PWM update to remove the PWM deviation during the second half of Tsamp
........................................................................................................................................... 72
xv
Fig. 3.27. Example application of hybrid PWM update with double-sampling method ............. 73
Fig. 3.28. Hybrid current control loop with a hybrid feedback ................................................... 76
Fig. 3.29. Eigenvalue migration pattern of GI_hy(z) when the L^ is varied with ωcc = 2πfsamp/6 ... 79
Fig. 3.30. Block diagram of the proposed corrective duty cycle manipulation ........................... 82
Fig. 3.31. First example of the corrective method 1 .................................................................... 85
Fig. 3.32. Second example of the corrective method 1 ................................................................ 86
Fig. 3.33. Third example of the corrective method 1 ................................................................... 87
Fig. 3.34. First example of corrective method 2 .......................................................................... 89
Fig. 3.35. Second example of corrective method 2 ...................................................................... 91
Fig. 3.36. Third example of corrective method 2 ........................................................................ 92
Fig. 4.1. Experimental Test Setup ................................................................................................ 96
Fig. 4.2. Stability boundary of the two-cycle deadbeat control ................................................... 99
Fig. 4.3. Stability boundary of the hybrid deadbeat control when Redge = 3/3 ........................... 101
Fig. 4.4. Stability boundary of the hybrid deadbeat control when Redge = 2/3 ........................... 101
Fig. 4.5. Steady-state responses ................................................................................................. 103
Fig. 4.6. Detailed steady-state responses of the hybrid PWM update method .......................... 105
Fig. 4.7. Hybrid PWM update method during over modulation ................................................ 106
Fig. 4.8. Simulated step responses ............................................................................................. 106
Fig. 4.9. Small-signal transient responses of conventional control with delayed PWM update 107
Fig. 4.10. Small-signal transient responses of predictive control with delayed PWM update
under small reference change .......................................................................................... 108
Fig. 4.11. Small-signal transient responses of hybrid control with hybrid PWM update under
small reference change .................................................................................................... 109
xvi
Fig. 4.12. Detailed small-signal transient responses of the hybrid deadbeat control ................. 110
Fig. 4.13. Large-signal transient responses ................................................................................ 112
Fig. 4.14. Maximum speed test .................................................................................................. 114
Fig. 4.15. Complex-vector eigenvalue migration patterns without Td-one when ωe increases ..... 118
Fig. 4.16. Steady-state operation with a very small Fratio .......................................................... 120
Fig. 4.17. Transient responses of the proposed method to step current changes at Fratio=5.0 ... 121
Fig. 4.18. Transient responses of PI controller to step current changes .................................... 123
Fig. Appendix B.1. Scalar representation of the proposed current control loop in Fig. 3.3 ...... 132
Fig. Appendix C.1 SPWM with usn* =0 and mi=0.6 .................................................................... 133
Fig. Appendix C.2 SPWM with usn* = –2Td-samp/Tsw and mi=0.8 ................................................. 134
Fig. Appendix C.3 120(OFF)DPWM with and mi=1.15*0.8..................................................... 135
xvii
List of Tables
Table 2.1. Total digital delays (Td-total) with respect to switching period (Tsw) ........................... 21
Table 3.1. Gain and phase margins and closed current loop bandwidth ...................................... 49
Table 3.2. Stability boundary of GI(z), GI_d-one(z) and GI_pred(z) .................................................. 53
Table 3.3. Theoretical stability boundaries of GI_hy(z) with respect to Redge ................................ 80
Table 3.4. Corrective action according to the number of references that violate dmax or dmin
threshold ............................................................................................................................ 84
Table 4.1. Specification of the experimental test setup ............................................................... 96
Table 4.2. Gain and phase margins and closed current loop bandwidth .................................... 117
Table 5.1. Comparison of the conventional and hybrid PWM update methods with deadbeat
control ............................................................................................................................. 126
xviii
List of Abbreviations
ac Alternating Current
ADC Analog-Digital Conversion
dc Direct Current
DSP Digital Signal Processor
FPGA Field-Programmable Gate Arrays
GaN Gallium Nitride
IGBT Insulated-Gate Bipolar Transistor
MIMO Multi-Input Multi-Output
MOSFET Metal–Oxide–Semiconductor Field-Effect Transistor
PFC Power Factor Correction
PI Proportional-Integral
PMSM Permanent Magnet Synchronous Machine
PWM Pulse-Width Modulation
SiC Silicon Carbide
UPS Uninterruptable Power Supply
VSI Voltage Source Inverter
ZOH Zeroth-Order-Hold
xix
Nomenclature
dabc* duty cycle vector in stationary reference frame
fsw switching frequency
fsamp sampling frequency
Tsw switching period
Tsamp sampling period
u inverter voltage with back-emf (complex-vector)
un mid-voltage of the vdc
us floating neutral point of the three-phase load
uxs phase voltages (the voltage difference between the ux and the us)
uxn pole voltages (the voltage difference between the ux and the un)
usn neutral offset voltage (voltage difference between the us and un)
vdc dc supply voltage
v controller output voltage without back-emf (complex-vector)
ωcc open-loop crossover frequency
x single variable (italic)
x complex-vector variable (bold-italic)
Superscript
* reference variables
Subscript
a, b, c phase-a, phase-b and phase-c variables in stationary reference frame
d, q phase-d and phase-q variables in synchronous reference frame
xx
Chapter 1
Introduction
1.1 Motivation
Power electronics are present everywhere as most modern electronics include some form
of power electronic components, and its tasks are different in different applications. It can be an
“enabling” technology. Electronic applications require power supplies, such as single-phase
power factor correction (PFC) circuits and simple analog dc-dc converters, and power electronics
are used to enable the operations of other electronics and applications. It can be an “interface”
technology. As more and more renewable energy sources become available, such as hydro
power, biomass, wind, thermoelectricity, photovoltaic, fuel cells, etc., power electronics are used
to recondition and interface raw powers to loads, such as utility grids, micro grids, and batteries.
It can be a “core” technology. As more systems become electrified, such as electric vehicles and
vessels, power electronics are the core techniques that are responsible for driving the system
performance higher.
Performance improvements in these power electronic applications have been the focus of
numerous researchers in past decades, and it still continues to receive attentions from academics
and industries. Although many types of research continue to focus on analog implementations of
1
power electronics, digital systems are often chosen over analog systems because of its many
advantages. Digital systems can do complicated controls, can be adaptive, are easy to modify, are
easily capable of multi-input-multi-output (MIMO) operations, are robust against aging and
noises, can easily interface other systems, etc. Digital controls are especially essential in
advanced applications, such as three-phase systems, due to its complicated algorithms.
Furthermore, the performance improvements of current loops have received extensive
attentions, because these typically are the innermost control loops that have a direct correlation
to the performances of outer control loops, such as voltage, speed, position, etc. Several
strategies have been proposed for the control of current loops in the past. Hysteresis control,
stator-reference-frame proportional-integral (PI) control, and synchronous-reference-frame PI
control are the basic and well-known methods [1]. Predictive control [2, 3], deadbeat control [3-
5], minimum time control [6], two-degree-of-freedom [7, 8], state feedback [5], internal model
control [9], etc., are more advanced schemes that improve the performance in some aspects, such
as faster responses, robust disturbance rejection, low current harmonic content, easier control
design, etc. However, achieved performances in previous literature are far below the theoretical
limits due to digital delays1, which consist of a one-step control delay Td-one and a digital PWM
delay Td-PWM. For example, delay elements reduce the maximum achievable bandwidth with
given stability margins.
The main motivation of the dissertation is to achieve a very high quality digital current
control through the reduction of the digital delays. A novel hybrid pulse-width modulation
1 The details of the digital delays are discussed in Chapter 2.
2
(PWM) update method is proposed to eliminate the effects of the one-step control delay Td-one
without losing the full duty cycle range. The proposed method is a simple concept that the PWM
outputs are updated two times during a sampling period Tsamp, whereas the PWM outputs are
updated only one time during a Tsamp in conventional PWM update methods. In spite of the
simplicity, the performance improvements in stability, robustness, and response characteristics
are significant. On the other hand, the proposed the proposed method can be easily applied to
many PWM based digital controls due to its simplicity. Additionally, a hybrid control method is
proposed to optimize the sequence of control operations. The proposed sequence is required to
take full advantages of the hybrid PWM update method. It maximizes the current loops’
robustness and minimizes the delay from the sampling instant of outer control loops’ variables to
the duty cycle update instant. It enables the maximization of the outer control loops’ bandwidth.
The combination of the hybrid PWM update method and the hybrid control algorithm
sequence can achieve many aspects of a very high quality current control, which includes
i) fast dynamic responses of the current loops during a transient,
ii) lower current ripples in the steady-state,
iii) a highly stable PWM inverter operation,
iv) robustness against the disturbances,
v) minimum delay for the outer control loops, and
vi) maximum supply voltage utilization.
3
1.2 Overview of the current controls in power electronics
Current control loops in various applications are illustrated. These applications can
significantly benefit from a high quality current control loop.
1.2.1 Dc-dc converters
vVoltage
Controller
*v Power Stage(Plant) Load
i vCurrent
Controller
*iVoltageController
*v Power Stage(Plant) Load
(a)
(b)Voltage feedback
Voltage feedbackCurrent feedback
Fig. 1.1. Simplified control block diagrams of dc-dc converter systems
(a) single-loop voltage mode control (b) dual-loop current mode control
Fig. 1.1 illustrates simplified control block diagrams of a dc-dc converter system. Fig.
1.1(a) is a voltage mode control, which employs the output voltage v as the only feedback signal
in the process of generating PWM outputs. Fig. 1.1(b) is a current mode control, which both the
output voltage v and inductor current i are utilized for the closed-loop control. The inductor
current i provides additional information for extra benefits in the PWM output generation, and
thus, modern PWM dc-dc converters extensively adapt the current mode control rather than the
voltage mode control [10].
4
1.2.2 Ac motor drives
iˆeω
*au*bu*cu
*uCurrentController
*iSpeedController
*eω
2 3⇒
Motor
abcu
3
2 3⇐ˆeω θ⇐
θ
Fig. 1.2. Simplified control block diagram of a three-phase ac motor drive system
Fig. 1.2 illustrates a simplified control block diagram of a three-phase ac motor drive
system. The cascade control is utilized, which the outer speed control generates the reference i*
of the inner current/torque control. The current control loop is the innermost loop, in which its
performances directly affect the performances of outer control loops, such as speed and position.
The current variables in the stationary reference frame are often transformed to the equivalent
variables in the synchronous reference frame.
1.2.3 Utility grid tied inverter system
dc-dcconverter
maximumpower point
trackingaci*
aci
dc-acinverter
currentcontroller
,dc dcv i
dcv
voltagecontroller
Fig. 1.3. Simplified control block diagram of a utility grid-tied inverter system
Fig. 1.3 illustrates a simplified control block diagram of a utility grid-tied inverter
system. A photovoltaic panel with a maximum power point tracking dc-dc converter is illustrated
as an example of a power source. The raw powers from different renewable energy sources are
converted, conditioned, and injected to the power grid, and the current controller is the interface
between the power source and the grid.
5
1.2.4 Uninterruptable power supplies
ac-dcconverter
dc-acinverter
batterymodule
critialloads
currentcontroller
voltagecontroller
*ov
,o ov i
oiov
*oi
Fig. 1.4. Simplified control block diagram of a uninterruptable power supply system
Fig. 1.4 illustrates a simplified control block diagram of an uninterruptible power supply
(UPS) application, which ensures continuous power supply to critical loads even during the
interruption of a main power source. Although the output voltage is the final control variable, the
current controller is a critical operational component that improves the dynamics and stability of
the entire system. The current controller also provides the system protection from over-current
faults.
6
1.2.5 Power factor correction
ac-dcconverter dc load
currentcontroller
voltagecontroller
aci
*dcv
dcv*aci
Fig. 1.5. Simplified control block diagram of a power factor correction system
Fig. 1.5 illustrates a simplified block diagram of a power factor correction (PFC) control
system. The voltage loop controls the dc-link voltage vdc and provides the reference to the inner
current controller. The current loop controls the grid current iac to match the phase of the grid
voltage. The goal is to achieve a unity power factor, and the current loop performance is
primarily responsible for the quality of power factor correction.
7
1.3 Design objective: High closed current loop bandwidth
Among many different desired and achievable performance characteristics, a high closed
current loop bandwidth is selected as the working example to demonstrate the performance
improvement with the proposed method2.
The first and foremost factor that limits the bandwidth of a digital current loop is the
sampling frequency fsamp. A slight reinterpretation of the Nyquist–Shannon sampling theorem
yields that the maximum bandwidth cannot exceed the half of fsamp. In comparison, although the
continuous “processing” of analog controls has no inherent bandwidth limits, the bi-state
characteristic of the PWM limits the maximum achievable bandwidth below the switching
frequency fsw.
The second limiting factor is the time delays in a control loop. The actual bandwidth is
much less than the Nyquist frequency because various delays reduce the phase margin of a
control loop; thus, delays limit the maximum achievable control bandwidth with given stability
margins [11]. Only when delays are minimized, a practical maximum closed current loop
bandwidth can match the theoretical value. The proposed hybrid PWM update method minimizes
the delays in a current control loop. Additionally, the proposed hybrid control minimizes the
delays in outer control loops.
2 The proposed method can be utilized to improve other performance characteristics, such as higher stability margins during high speed operations. These options are explored in Chapter 4.
8
Chapter 2
Existing Techniques and Literature Review
Fundamental topics are discussed, and some basic terms are defined to lay the foundation
for the proposed hybrid PWM update method. First, a current sampling method for a fixed-
frequency modulation system is reviewed. Second, two conventional PWM update methods are
examined to illustrate its behaviors, such as delays and duty cycle range characteristics. Third,
literature is reviewed on related topics, such as the definition on bandwidth, how delays are
handled in a control design, previous novel PWM update methods, etc.
9
2.1 Current sampling methods
carrier &reference
sampling points
PWM
current
Fig. 2.1. Current sampling method with a uniformly sampled PWM using a triangular carrier
In a fixed-frequency modulation system, state variables, such as currents, voltages, speed,
etc., are sampled at uniformly spaced time intervals. This method is referred as the uniformly
sampled PWM3 [12, 13]. Only the uniformly sampled PWM is concerned in the dissertation.
Fig. 2.1 illustrates a current sampling method with the uniformly sampled PWM using a
triangular carrier. Although different carrier types, such as trailing edge, leading edge, triangular,
etc., can be used with the uniformly sampled PWM, the triangular carrier is most attractive for a
couple of reasons. First, the triangle carrier makes the measurement of an average current very
simple. The currents are commonly sampled in the middle of either the turn-on or the turn-off
times, at where switching noise induced harmonics are suppressed; thus, the current average
values are measured without antialiasing filters [5]. The middles of the turn-on and turn-off times
coincide with the bottom and top of triangle carrier peaks, respectively. Therefore, if currents are
sampled at the peaks of the triangle carrier, then the average currents are measured at uniformly
spaced time intervals without any extra configuration, modification, or antialiasing filters. With
3 The uniformly sampled PWM is also referred as the regularly sampled PWM in some literature.
10
the other carrier types, the middles of turn-on and turn-off times vary with duty cycle values, and
thus, the measurement of the average currents is not trivial.
Second, the average of the digital PWM time delay Td-PWM stays constant regardless of
duty cycle values [5, 13]. With the triangular carrier, the transfer function of the digital PWM
can be modeled in the s-domain as
( ) ( ) ( )1 1
2 2
2 2
12
cos2
samp samp
samp samp
T Ts D s D
PWM
T Ts ssamp
G s e e
Te D eω
− − − +
− −
= +
= ≅
, (2.1)
where D is an average duty ratio, and ω is. GPWM(s) can be approximated with a zero-order-hold
(ZOH) transfer function. Therefore, the discretization of a plant model with the digital PWM
from the s-domain to z-domain can be easily done using the ZOH sample and hold (S-H) model.
The ZOH transfer function is given as
( ) 1 sampsTeH ss
−−= . (2.2)
A more detailed explanation is given in [5]. For these conveniences and advantages, the
uniformly sampled PWM with the triangular carrier is assumed throughout the text.
11
Current sampling
Carrier
(a)
(b)
(c)
swT
sampT
sampT
sampT
Fig. 2.2. Varieties of sampling methods
(a) single-sampling at the top peak of a carrier (b) single-sampling at the bottom peak of a carrier
(c) double-sampling
Fig. 2.2 illustrates three varieties of the uniformly sampled PWM with the triangular
carrier. Fig. 2.2(a) and (b) illustrates the single-sampling per switching period (Tsw) method (i.e.
the fsamp is equal to the fsw). When the current sampling is performed only at the top peak of the
carrier, as shown in Fig. 2.2(a), it is referred as single-sampling at top. Similarly, when the
current sampling is performed only at the bottom peak of the carrier, as shown in Fig. 2.2(b), it is
referred as the single-sampling at bottom4. When the currents are sampled at the both carrier
peaks, as shown in Fig. 2.2(c), it is simply referred as the double-sampling5 (i.e. the fsamp is twice
as high as the fsw). It should be noted that the current samplings occur only at the peaks of the
carrier, and the current samplings at other points are not considered.
4 The single-sampling at top is also referred as symmetric-on-time sampling, and the single-sampling at bottom is also referred as symmetric-off-time sampling in some literature.
5 The double-sampling is also referred as asymmetric sampling in some literature.
12
2.2 Conventional PWM update methods
An ideal controller would instantaneously sample, compute, and update its PWM outputs;
however, in practice, current samplings and algorithm computations consume some time. With
considering the fact that these sampling and computation time must occupy a part of a Tsamp, two
conventional PWM update methods are examined: an immediate PWM update method and a
delayed PWM update method.
2.2.1 Immediate PWM update method
-d compT
samplings
Carriersw sampT T=
computations1: conversion2: speed control3: current control
duty cycle range ofimmediatePWM update
*[ ]ku *[ 1]k +u
immediate PWM update
[ ]-thk [ 1]-thk +
[ ]ki [ 1]k +i
1 2 3
0.5d total sampT T− =- 0.5d PWM sampT T=
1 2 3
Fig. 2.3. Simplified timing diagram of immediate PWM update method
Fig. 2.3 illustrates a simplified timing diagram of the immediate PWM update method.
Small hashed boxes in the figure indicate the computation time of different operations that utilize
a portion of a Tsamp. The sum of all computation time is referred as Td-comp, which spans from the
current sampling instant to the PWM loading instant. The Td-comp may include conversions of
sampled variables, speed estimation, speed control, current control, etc. When the immediate
PWM update method is utilized, the PWM outputs are immediately updated at the end of the
Td-comp.
13
2.2.1.1 Duty cycle range
-d compT
carrier
-d compT
-d compT
sampling & update-d compT
duty cycle range
sw sampT T=
carriersampling & update
-d compTduty cycle range
sw sampT T=
carriersampling & update
-d compTduty cycle range
2sw sampT T= ⋅
Fig. 2.4. Duty cycle range of immediate PWM update method
(a) single-sampling at top (b) single-sampling at bottom (c) double-sampling
Fig. 2.4 illustrates the duty cycle range of the immediate PWM update method. The
major disadvantage of the immediate PWM update method is that the duty cycle must be limited
to avoid possible PWM output errors [14-16]. When the single-sampling at top is utilized as
shown in Fig. 2.4(a), the duty cycle d must be limited below the maximum duty cycle threshold
dmax as
-21 d comp
maxsw
Td d
T≤ = − . (2.3)
In a similar manner, when the single-sampling at bottom is utilized as shown in Fig. 2.4(b), the
duty cycle d must be limited above the minimum duty cycle threshold dmin as
-2 d compmin
sw
Td d
T≥ = . (2.4)
14
When the double-sampling is utilized as shown in Fig. 2.4(c), the duty cycle d must be limited by
both the dmax and dmin thresholds, which the reduction of the duty cycle range is twofold when
compared to the single-sampling methods.
The dmax and dmin thresholds can be translated in terms of a pole voltage uxn. The range of
the duty cycle d is from 0 to 1, and the range of the pole voltage uxn is from –vdc/2 to +vdc/2.
Thus, the relationship between d and uxn is defined as
0.5xn
dc
udv
= + . (2.5)
Accordingly, the maximum pole voltage umax can be defined with dmax as
( )0.5xn max max dcu u d v≤ = − , (2.6)
and uxn must be limited below umax. Similarly, the minimum pole voltage umin can be defined with
dmin as
( )0.5xn min min dcu u d v≥ = − , (2.7)
and uxn must be limited above umin. These dmax, dmin, umax and umin are used interchangeably based
on situations.
It should be noted that the Td-comp may not be the same in every interrupt routine. In
practical implementations, the variation of the Td-comp should be measured, and dmax, dmin, umax
and umin should be computed to include the largest Td-comp.
Ideally, the best solution to the duty cycle limitation is to minimize the Td-comp to a
negligible level, but it may not be possible. An alternative solution is to increase the amplitude of
the dc supply voltage vdc. With a given pole voltage reference, the reference moves away from
the peaks of a carrier with an increasing vdc, thus it provides more time to complete the
computation. However, this solution may not be preferred or feasible with given design criteria.
15
For example, an increased voltage would require higher component ratings, and the amplitude of
vdc cannot be increased if vdc is generated from a fixed voltage ac utility grid via passive
rectifiers.
2.2.1.2 Digital comparator behavior
(a)
(b)
(c)
triangle carrier
PWM
comparator*ZOHu
asZOH
carrv
sampling & update
as
*ZOHu
sampling period
-d compT -d compT
multiple polarity changes
sampling & update
as
sampling period
-d compT -d compT
missing PWM output PWM output deviation
carrv
carrv
*ZOHu
maxv
maxv
prohibited area
2dcv
2dcv
−
Fig. 2.5. Comparator behaviors during immediate PWM update method
(a) comparator circuit (b) analog comparator output (c) digital comparator output
Fig. 2.5 illustrates the comparator behaviors during the immediate PWM update method.
In Fig. 2.5(a), the ZOH voltage reference uZOH* is applied to the positive (i.e. non-inverting) input
of a comparator, and a triangle carrier vcarr is applied to the negative (i.e. inverting) input. These
two signals are modulated into a PWM output via a comparator.
16
Fig. 2.5(b) illustrates the analog comparator’s behavior. Its output behavior is purely
based the voltage difference between the positive and negative inputs, and whenever the polarity
of the input differential changes, the PWM output changes accordingly. An undesirable PWM
output is produced when the uZOH* is placed in the prohibited area. The prohibited area, which is
marked with hashes in the figures, refers to a reference area where if a pole voltage reference of
the immediate PWM update is placed, then its PWM output violates the vmax or vmin thresholds.
The prohibited area is also applicable to relation between a duty cycle reference and the dmax or
dmin thresholds. For example, if the uZOH* enters the prohibited area in the middle of a Tsamp as
shown in the first Tsamp of Fig. 2.5(b), then the PWM output has a PWM output deviation.
Similarly, if the uZOH* exits the prohibited area in the middle of a Tsamp as shown in the second
Tsamp of Fig. 2.5(b), then the polarity of the PWM output changes multiple times in a Tsamp. Both
cases are acceptable but should be avoided. As long as the uZOH* does not violates the vmax and
vmin thresholds, the PWM output behavior is normal.
Fig. 2.5(c) illustrates the digital comparator’s behavior. Modern DSPs (e.g.
TMS320C2XXX of Texas Instruments) typically have embedded PWM comparators, and its
digital comparators may behave differently than analog comparators due to implementation
differences. It is assumed that a PWM output logic is decided based on the crossing event
between a voltage reference and the carrier [17]. For example, if the uZOH* enters the prohibited
area in the middle of a Tsamp as shown in the first Tsamp of Fig. 2.5(c), then the crossing event
between the uZOH* and vcarr does not occur due to the discontinuity of the uZOH* when the
immediate PWM update is executed, and thus, the PWM output stays low for the entire Tsamp. It
is a significant error, and it must be avoided. Similarly, if the uZOH* exits the prohibited area in the
17
middle of a Tsamp as shown in the second Tsamp of Fig. 2.5(c), then the PWM output deviates from
the desired value. This is acceptable but should be avoided.
2.2.2 Delayed PWM update method
samplings
Carriersw sampT T=
computations1: conversion2: speed control3: current control
duty cycle range ofdelayedPWM update
*[ ]ku *[ 1]k +u
delayed PWM update
[ ]-thk [ 1]-thk +
[ ]ki [ 1]k +i
1 2 3
-d oneT
1.5d total sampT T− =- 0.5d PWM sampT T=- 1.0d one sampT T=
1 2 3
Fig. 2.6. Simplified timing diagram of delayed PWM update method
Fig. 2.6 illustrates a simplified timing diagram of the delayed PWM update method.
Since the computation delay Td-comp cannot be reduced to zero, the update of a PWM output is
delayed until the beginning of the following Tsamp to avoid any loss of duty cycles or possible
PWM output malfunctions. This method allocates an entire Tsamp for the sampling and
computations. The delay due to the delayed PWM update is equivalent to a sampling period (i.e.
z-1), and this delay is referred as the one-step control delay Td-one. The Td-one is also referred as
“the sampling measurement and computation delay” in [11] and as “the execution time delay” in
[18].
18
2.2.3 Variety of the delayed and immediate PWM update methods and digital
delays
(a)2dcv
2dcv
−
swT
(b)
-d PWMT
(c)
PWMT- 1.5d total swT T=
(d)
- 0.75d total swT T=
Sampling delayed PWM update
- 1.5d total swT T=
- 1.0d total swT T=
- 1.0d total swT T=
- 0.5d total swT T=
1k −k
k1k +
1k −k
k1k +
kk 1k +1k +
-d oneT
-d oneT
kk1k − 1k +
kk
1k +1k +
1k −k
1k +2k +1k +
k
-d totalT
kk
1k +1k +
kk
1k +1k +
2k +2k +
3k +3k +
- 0.5d total swT T=
- 0.25d total swT T=
(e)
(f )
(g)
(h)
(i)
immediate PWM update
Fig. 2.7. Varieties of delayed and immediate PWM update methods
The total digital delay Td-total is the sum of the one-step control delay Td-one and the digital
PWM delay Td-PWM. These two are well-known delay defects in digital controls [11, 13, 18]. The
origin of the Td-one is discussed in 2.2.2. In addition to the Td-one, the Td-PWM must be considered as
19
a part of the total digital delay Td-total. The Td-PWM equals 0.5 times Tsamp, and it inherently arises
due to the sample-and-hold (S-H) characteristic of the uniformly sampled PWM method [13]6.
Fig. 2.7 illustrates varieties of the delayed and immediate PWM update methods. A
triangle carrier is shown in Fig. 2.7(a). The varieties of the delayed PWM update methods are
shown from Fig. 2.7(b) to (f). Fig. 2.7(b) and Fig. 2.7(c) are the single-sampling at top and
bottom, respectively. A full one Tsw is allocated for Td-one, and thus the Td-total is of these delayed
PWM update methods are
- - - 1.5d total d one d PWM swT T T T= + = ⋅ . (2.8)
Fig. 2.7(d) and Fig. 2.7(e) are another varieties of the single-sampling at top and bottom
peak, respectively. A half of a Tsw is allocated for Td-one, and thus the Td-total of these delayed
PWM update methods are
- - - 1.0d total d one d PWM swT T T T= + = ⋅ . (2.9)
Fig. 2.7(f) is the double-sampling. One full Tsamp is allocated for Td-one, which is
equivalent to a half of a Tsw. Additionally, since the Tsamp is halved compared to the Tsw, the
Td-PWM is also halved when compared to the Tsw, which equals 0.25 times Tsw. The Td-total is
- - - 0.75d total d one d PWM swT T T T= + = ⋅ . (2.10)
The varieties of the immediate PWM update methods is shown from Fig. 2.7(g) to Fig.
2.7(i). Fig. 2.7(g) and Fig. 2.7(h) are the single-sampling at top and bottom, respectively. With
6 If a multi-sampling method is utilized, the Td-PWM can be reduced, but it is not considered. Also, the delay amount of Td-PWM equals to 0.5 times Tsamp only when the triangular carrier is used. Refer to section 2.1.
20
the immediate PWM update method, the Td-one is eliminated at the cost of the reduced duty cycle
range. Therefore, the Td-one is equal to zero, and the Td-total consists of only the Td-PWM, which is
- - 0.5d total d PWM swT T T= = ⋅ . (2.11)
Fig. 2.7(i) is the double-sampling. When the double-sampling is used, the Td-PWM is
halved when compared to the single-sampling. Thus, the Td-total is
- - 0.25d total d PWM swT T T= = ⋅ . (2.12)
Table 2.1. Total digital delays (Td-total) with respect to switching period (Tsw)
Sample and update frequency Update method Td-one Td-PWM Td-total
Single-sampling Delayed 1.0 0.5 1.5 Delayed 0.5 0.5 1.0
Immediate 0.0 0.5 0.5
Double-sampling Delayed 0.5 0.25 0.75 Immediate 0.0 0.25 0.25
Table 2.1 summarizes the Td-total with respect to the Tsw. Two things can be observed.
First, the delays of the double-sampling method are smaller than the delays of the single-
sampling methods, which is an obvious result due to faster sampling rate. Second, the Td-total of
the immediate PWM update method is less than the Td-total of the delayed PWM update method,
since the effective delays due to the Td-one is zero with the immediate PWM update method. The
minimum Td-total with respect to Tsw is achieved when the double-sampling method is utilized
with the immediate PWM update method.
21
2.3 Delays in the current loop
i
digitalcurrent
controller
*i power stage(plant)
load
antialiasingfilter
sensordelay
filter delay
digital PWMdelay
one-step controldelay
Fig. 2.8. Different delays in a current loop
Fig. 2.8 illustrates different delays in a current loop. Typical delays in a current loop
include sensor delays, antialiasing filter delays, and digital delays. State variables, such as
currents, voltages, speed, etc., must be transduced by respective sensors. The delays due to a
current sensor can be largely neglected if the bandwidth of a sensor is much larger than the target
closed-loop bandwidth.
After the currents are transduced, the signals must be sampled and quantized7 for the
digital control. Although antialiasing filters are often required in other digital controls, the
antialiasing filters can be avoided when the uniformly sampled PWM is utilized with the triangle
carrier, as discussed in section 2.1. Thus, the delay due to the antialiasing filter can be eliminated.
Remaining delays are the digital delays, which consists of the one-step control delay
Td-one and the digital PWM delay Td-PWM. Since the uniformly sampled PWM is assumed in this
dissertation, the Td-PWM is accepted and is modeled as a part of the plant as an S-H characteristic.
7 The quantization errors are assumed to be negligible.
22
This is discussed in detail in Appendix A. In following chapters, the method for eliminating the
effect of the one-step control delay Td-one is discussed and proposed.
23
2.4 Literature reviews
2.4.1 Definition of bandwidth
A standard textbook definition of the bandwidth of a closed-loop frequency response is
the frequency at which the magnitude response curve is 3 dB down from its value at zero
frequency [19], and it is referred as ±3 dB qualification. However, some system may not fall
below 3 dB at any frequency. For such systems, the bandwidth is defined as the frequency range
over which the magnitude of the closed loop gain first decreased by no more than 3 dB, the
peaking is less than 3 dB, and the phase shift has not exceeded –90° [20], and this is referred as –
90° qualification.
2.4.2 Handling of time delays
The design objective is to maximize the bandwidth of a closed current loop, and it is well
understood in the control theory that time delays reduce the control loop phase margins; thus, the
delays limit the maximum achievable control bandwidth with given stability margins.
In past literature, the delays are handled in various ways. When the desired controller
bandwidth is lower than the effective frequency range of phase reduction due to the delays, the
delays have minimum effects and can be simply ignored in the controller designs. On the other
hand, the delays must be considered for higher bandwidth controllers. Simple controllers, such
PI, with a moderately high bandwidth can be quite reliably designed if time delays are properly
modeled and compensated. The delays are typically modeled as a low-pass filter with a time
constant that corresponds to the delays [5, 11, 21]. For high bandwidth controllers, such as
predictive and deadbeat types [2-5, 22], the delays must be considered more explicitly. For
example, in [4, 22-25], the delays due to algorithm computation and pulse-width modulation
24
(PWM) update method are accounted and compensated as a part of the control algorithms to
improve the bandwidth.
In [26] and [27], the digital delays are reduced by utilizing the immediate PWM update
method, rather than compensating the delays, and the reduction of the delays enabled the
bandwidth increase; however, inaccurate plant models are utilized and the deficiencies of the
immediate PWM update are not addressed.
2.4.3 Implementation platform
As it is evident in previous literature [26, 27], the idea of utilizing the immediate PWM
update method is not new, but the excessive algorithm computation time had made the
immediate PWM update method nearly impractical to utilize it in the past. Nowadays, the
advancement of digital processing power enables the immediate PWM update method a viable
option. Typically, a digital system is configured using one of two following processors: a
hardware-based parallel processor, such as field-programmable gate arrays (FPGA), and a
software-based sequential processor, such as a digital signal processor (DSP). The hardware-
based parallel processors have a finite, yet nearly negligible execution time, due to a very high
computing capability. For example, an FPGA is used for a motor control application in [26]. Its
ADC sample and conversion time is 550 ns, and the execution time of the entire algorithm is 200
ns. In comparison, the software-based sequential execution processors are slower and have a
considerable algorithm execution time. The algorithm execution time, which includes
trigonometric math for coordinate transformation, of older processors occupies a significant
portion of a sampling period [28]. Good news is that modern DSPs have dedicated trigonometric
math units and are much faster; therefore, the algorithm execution time can be reduced to a level
that the immediate PWM update method can be reasonably considered, even with the software-
25
based sequential processors [29]. However, regardless which processor type is utilized, the
Td-comp cannot be reduced to zero.
2.4.4 Control design methods
For a lower bandwidth controller, a controller can be designed in the continuous-time
domain using a continuous-time domain plant model, and then the controller can be discretized
for a discrete-time domain implementation, but this method cannot provide the best performance.
An acceptable approach for a moderately high bandwidth control is to design a controller in the
discrete-time domain with a discretized plant model via a Taylor series expansion [3]; however,
this method also cannot provide the best performance. To realize a high bandwidth control, a
proper plant model and an advanced controller are required. In [30], an accurate discrete-time
plant model and a pole-zero canceling controller are previously proposed, and these are modified
and extensively employed in the dissertation to achieve a high bandwidth control.
26
2.4.5 Previous novel PWM update methods
Several different novel PWM methods have sought to remove the one-step control delay
Td-one without the loss of duty cycle range. However, existing methods have disadvantages.
[ 3] sk T− ⋅
0.46d = 0.52d = 0.58d = 0.67d =Active-low PWM patternActive-high PWM pattern
Interrupt signal
PWM signal
[ 2] sk T− ⋅ [ 1] sk T− ⋅ [ ] sk T⋅ [ 1] sk T+ ⋅
Fig. 2.9. “Two-polarity PWM method” of [14]
A “two-polarity PWM method” is proposed in [14], and a modified copy of an excerpt
from the reference is illustrated in Fig. 2.9. Either an active-high PWM pattern or an active-low
PWM pattern is selected for the following Tsamp based on the duty cycle of the current Tsamp. For
example, the active-low PWM pattern is utilized in the following Tsamp when the duty cycle is
higher than 0.5. Similarly, the active-high PWM pattern is utilized when the duty cycle is lower
than 0.5 as illustrated in the excerpt. It can provide a minimum sampling and calculation time of
0.25∙Tsw before the first PWM edge change.
There are one minor and one major problems. The minor problem is that an extra PWM
edge change is required when the PWM pattern changes; however, two extra PWM edge changes
per fundamental cycle should not be a big burden to overall switching losses. The major problem
is that the proposed method cannot handle a large duty cycle jump. For example, if the previous
duty cycle is less than 0.5 and the following duty cycle is larger than 0.75, then the guarantee of
the availability on 0.25∙Tsw calculation time is lost, and the PWM output may malfunction as
shown in Fig. 2.5.
27
carrier &reference
sampling points0.9d = 0.7d = 0.4d = 0.2d =
Fig. 2.10. “Dual sampling mode” of [15]
A “dual sampling mode” is proposed in [15], and a modified copy of an excerpt from the
reference is illustrated in Fig. 2.10. This method has a similar concept as the “two-polarity PWM
method.” Instead of switching the PWM patterns, the sampling instant is changed based on the
duty cycle. The peak-valley sampling mode is utilized when the duty cycle is less than 0.5, and
the mid-value sampling is utilized when the duty cycle is greater than 0.5. It should be noted that
the unipolar sinusoidal PWM is used; thus, the peak-valley sampling mode is equivalent to the
single-sampling at top, and the mid-value sampling mode is equivalent to the single-sampling at
bottom as shown in Fig. 2.2. Since this method is similar to the “two-polarity PWM method,” it
also provides an available sampling and calculation time of 0.25∙Tsw. Its disadvantages are that it
cannot handle a large duty cycle change and that a special treatment may be required during the
sampling change instant due to change of the Tsamp width. A possibility of using this method for
three-phase application is raised in [31], but it is not applicable.
28
1S
sample update sample update
2S
Fig. 2.11. “Area compensation scheme” of [32]
An “area compensation scheme” is proposed for an LCL-type converter in [32], and an a
modified copy of an excerpt from the reference is illustrated in Fig. 2.11. This method is based
on an area equalization concept that the deviation of “area” between the sampling point and the
update point (i.e. S1 in the figure) is compensated by an equal and opposite “area” between the
update point and the next sampling point (i.e. S2 in the figure). This method has two major
problems. First, it requires advancing the sampling point ahead of the carrier peak. This is
acceptable for the sampling of the grid-side inductor of an LCL filter since switching induced
current harmonics are small, but this method is not acceptable for the sampling of the inverter-
side inductor of an LCL filter due to large harmonics. Second, the compensation cannot fully
compensate when a large PWM step change occurs for the same reason of the “two-polarity
PWM method.” If a large “area” error occurs in the S1 due to a large PWM step change, then
there may not be enough “area” to compensate in the S2.
29
[ 2] sk T− ⋅
Interrupt signal for 1stupdate of pulse width
PWM signal
[ 1] sk T− ⋅ [ ] sk T⋅ [ 1] sk T+ ⋅
Interrupt signal for 2ndupdate of pulse width
1S2S
0.5d = 0.7d =
Fig. 2.12. “Asymmetric PWM method” of [14]
An “asymmetric PWM method” is proposed in [14], and a modified copy of an excerpt
from the reference is illustrated in Fig. 2.12. This method is based on a similar concept as the
“area compensation scheme.” During a switching interval k, a sampling and calculation begin at
time kTs. During the first half of the PWM, the same duty cycle from the previous cycle is
utilized, and a new duty cycle is computed. A new PWM duty cycle is updated in the second
half, in which the duty cycle discrepancy during the first half is added during the second half.
This method can provide an available sampling and calculation time of 0.5∙Tsw. This method has
a major problem that a full duty cycle range cannot be achieved, as mentioned in the reference.
Thus, a “modified” method is proposed to set the first half the PWM cycle to either full or zero
duty cycle based on the previous duty cycle. This method also suffers the same problem of not
being able to correctly produce the computed PWM when there is a large duty cycle change
between sampling periods.
Above existing methods can provide some minimum computation time and the full duty
cycle range under an assumption that a PWM output does not change in large steps; however,
these cannot guarantee the full duty cycle range under all conditions.
Additionally, these methods, except the “area compensation scheme,” are only applicable
to single-sampling, and cannot be applied to double-sampling. The “area compensation scheme”
30
can be used in double-sampling, but the sampling instant must be ahead of the carrier peak, and
it is not suitable for the current sampling at the inverter side.
Another disadvantage of these methods is that these are only applicable to single-phase
applications and are ineffective for multi-phase applications. The “area compensation scheme”
can be applied to a multi-phase application, but the scheme must be applied to each phase.
In comparison, the proposed hybrid PWM update method can be applied to both the
single- and double-sampling methods, as well as single-phase and three-phase applications.
2.4.6 Multi-sampling and current sampling at other than carrier peaks
A multi-sampling method refers to a method that more than one sampling of the same
state variable is executed per Tsw. For example, the double-sampling method, which is discussed
in section 2.2.3, is a multi-sampling method. The multi-sampling method is attractive because
the digital PWM delay the Td-PWM can be significantly reduced [33]. However, if more than two
samplings are executed per Tsw, then some samplings must be executed other than the middle of
either the turn-on or the turn-off times. Similarly, when the current sampling point is shifted
ahead to provide time for computations, it again requires that the currents be sampled other than
the middle of either the turn-on or the turn-off times. Thus, the switching noise induced
harmonics cannot be suppressed as stated in section 2.1, and these harmonics must be either
filtered by analog antialiasing filters or digitally removed via algorithms [34]. The antialiasing
filters cause the phase delay, and thus any advantage gains are lost. The algorithm approach is
attractive since it does not impose any additional phase lags, but it requires additional
computations, and its accuracy cannot be better than the measurement itself.
31
Chapter 3
Hybrid PWM Update Method
cs
cs
2dcv
2dcv
au
bu
cu
nu
as
as
bs
bs
su
Three-phase SystemVoltage Source Inverter
LR E
Fig. 3.1. Three-phase voltage source inverter and a generic three-phase RLE load model
PMSMModulator
abcuas
bs
cs
iˆeω3
Triangle Carrier
2 3⇐ˆeω θ⇐
*au*bu*cu
*uCurrentController
*iSpeedController
*eω
2 3⇒θ
Fig. 3.2. Overall cascade control scheme with a surface PMSM
For the simplicity of discussion, a three-phase voltage source inverter (VSI) with a
generic three-phase RLE load model is selected as the working example, as shown in Fig. 3.1.
The load model consists of resistive R, inductive L, and back-emf E elements. Additionally, the
control structure of a surface permanent magnet synchronous machine (PMSM) in the
synchronous reference frame is utilized, and an overall cascade control scheme is shown in Fig.
32
3.2. An outer speed control loop utilizes a speed reference ωe* and a speed feedback ωe to
generate a current reference vector i*. The ωe is estimated from position θ measurements. An
inner current controller utilizes i* and a current feedback vector i to generate an inverter voltage
reference vector u*. The voltage reference u* is decomposed from a synchronous 2-variable
structure to a stationary 3-variable structure via a coordinate transformation operation. The
decomposed and individual inverter voltage references ua*, ub* and uc* are then modulated into
PWM outputs via comparisons with a triangle carrier. The PWM outputs sa, sb and sc are then
amplified and applied to the PMSM with the VSI.
33
3.1 Plant modeling and control design with immediate PWM update
method
3.1.1 Plant modeling
An exact discrete-time plant model Gp(z) in the synchronous reference frame is given as
( ) ( )( )
( )( ) ( )
/
/1 1
1 1
samp
e samp samp
e samp
p
R T L
j T R T L
j T
z zG z
z z z
eR ze e
eR ze e
ω
α
ω α
− ⋅
− ⋅
−
−
= =−
−=
−−
=−
i iv u E
, (3.1)
where α is a shorthand for (R·Tsamp/L), Tsamp is the sampling period, e is the exponential, and ωe is
the electrical synchronous frequency [30]. Symbols with the bold-italic face are complex vector
variables for multiphase notation including i as the current vector, u as the inverter voltage
vector, v as the current control voltage vector, and E as the back-emf voltage vector. The
complex-vector notation is defined as f = fd + j·fq [35], and the complex-vector notations are
extensively utilized to simplify the analysis from the conventional two-input, two-output scalar
structure to an equivalent single-input, single-output complex-vector structure. Additionally, the
plant model Gp(z) is more accurate than the models based on a Tayler’s expansion [3, 25].
Therefore, performance deteriorations due to model mismatches can be largely reduced,
especially during high speed operations. It should be noted that the plant model Gp(z) inherently
includes the S-H effect of the Td-PWM. The derivation of Gp(z) is detailed in Appendix A.
34
3.1.2 Controller design
Based on the plant model Gp(z), a current controller Gc(z) can be designed as
( ) ( )
( )( ) ( )( ) ( )
( )( )
* *
*
ˆ ˆ
ˆ
ˆ
ˆ1 1
e samp
c
j T
z z zG z
z z z
ze eKRe z
ω α
α
−
−
−= =
−
−=
− −
v u Ee i i
, (3.2)
where K is the controller gain and e is the error vector [16, 30]. The ‘*’ and ‘^’ indicate reference
and estimated values, respectively. The current controller Gc(z) produces the voltage reference
v*, and v* is summed with the estimated back-emf voltage vector E^ to generate the inverter
output reference u*.
The rationales of the controller Gc(z) are as follows. First, an integrated term, which is (z–
1) in the denominator, is added for a zero steady-state tracking error. Second, the frequency-
dependent poles of Gp(z) are canceled using the frequency-dependent zeros of Gc(z). Third, the
frequency-dependent variables in Gp(z) are canceled using its reciprocal variables in Gc(z). It is
important to note that the frequency-dependent values in the controller move with the frequency-
dependent values in the plant to directly cancel each other regardless of the operating frequency.
Lastly, the controller gain K determines the open-loop crossover frequency ωcc of the current
loop.
*i
( )ˆ ˆ1
ˆˆ
1
e sampj Te z eKRe
ω α
α
− −
−
−−
1z− E
Digital Controller
e*u*v
Ei
Discrete Plant Model
( )1
1
11e sampj T
z eR e z e
α
ω α
− −
− −
−
−vu
Fig. 3.3. Current control loop without considering Td-one
35
Fig. 3.3 illustrates the current control loop without considering the Td-one according to
Gp(z) and Gc(z). The lack of the Td-one indicates that the immediate PWM update method is
utilized. The scalar representation of the current loop in Fig. 3.3 is given in Appendix B.
3.1.3 Controller gain deign method
If the estimated parameters are known and equal to the actual parameters (i.e. L^ =L, R^ =R
and E^ =E), and if the inverter output reference u* is accurately modulated to the inverter output u
by the VSI, then a perfect pole-zero cancellation can occur between the plant Gp(z) and controller
Gc(z). The open-loop transfer function TI(z) is derived as
( ) ( )( ) ( ) ( )
1I c p
z KT z G z G zz z
= = =−
ie
, (3.3)
and the closed-loop system transfer functions GI(z) is derived as
( ) ( )( )
( )( )* 1 1
II
I
T zz KG zz T z z K
= = =+ − +
ii
. (3.4)
The controller gain K determines the open-loop crossover frequency ωcc, and K can be derived as
a function of ωcc as follows. First, the z of TI(z) is substituted with exp(j·ω·Tsamp), and TI(z) is
rewritten as
( )
( ) ( )
1
cos 1 sin
samp
samp
j TI j T
samp samp
KT ee
KT j T
ωω
ω ω
=−
=− +
. (3.5)
Second, the magnitude of TI(z) is derived as a function of frequency ω as
( ) ( )
( )( ) ( )2 2cos 1 sin
sampj TI
samp samp
M T e
K
T T
ωω
ω ω
=
=− +
. (3.6)
36
Third, the expression M(ω) is set equal to one, since the magnitude is one at ωcc by definition.
After some trivial trigonometric simplifications, the controller gain K is derived as a function of
ωcc as
( ) ( )2 2co scc cc sampK Tω ω= − . (3.7)
It should be noted that the only design variable is ωcc; thus, the system responses can be
determined by selecting an appropriate ωcc.
3.1.4 Control computation sequence
Speed control computationCurrent control computation
Duty cycle range
*[ ]ki *[ 1]k +i
*[ ]ku *[ 1]k +u Immediate PWM update
-d compT
*[ ]ku *[ 1]k +u
[ ]-thk [ 1]-thk +
Position samplingCurrent sampling
Sampling period[ ]kθ [ 1]kθ +[ ]ki [ 1]k +iˆ [ ]e kω ˆ [ 1]e kω + Speed estimation
Fig. 3.4. Timing sequence without considering Td-one
Fig. 3.4 illustrates an example timing sequence without considering the one-step control
delay Td-one. The immediate PWM update method is utilized to eliminate the effect of the Td-one.
As stated in section 2.2.1 and as shown in Fig. 3.4, the full duty cycle cannot be utilized due to
the computations delay Td-comp.
During the Td-comp, many operations are executed, and a typical control computation
sequence is as follows. At the beginning of the [k]-th Tsamp, the position θ[k] and currents i[k] are
sampled simultaneously, and the speed feedback ω^ e[k] is estimated using past θ measurements.
The variables in the figure indicate the results of different operations; for example, the θ beside
the hollow down arrow is the result of position sampling, and the ω^ e beside the horizontal hashed
37
box is the result of the speed estimation operation, etc. The speed control computation generates
the current reference vector i*[k] from the speed reference ωe*[k] and ω^ e[k] (see Fig. 3.2). The
computation of the current controller Gc(z) generates the control voltage reference vector v*[k]
from the i*[k] and i[k] as shown in (3.2). The v*[k] is summed with the E^ [k] to generate the
inverter voltage reference vector u*[k] (see Fig. 3.3), and u*[k] is loaded to PWM output via the
immediate PWM update method.
3.1.5 Modulation index limitation
In a three-phase system, rather than considering the duty cycle limitations of individual
phases with the dmax of (2.3) and dmin of (2.4), the limitation of modulation index mi is more
convenient to consider. The instantaneous mi of an inverter voltage reference can be defined as
( ) ( )2 2* **
*( )/ 2 / 2
d qi
dc dc
u um
v v
+= =
uu . (3.8)
When a conventional sinusoidal PWM (SPWM) is utilized, the maximum mi is defined as
-* 4( ) ( ) 1 d comp
i isw
Tm m max
T≤ = −u . (3.9)
When a space vector PWM (SVPWM) is utilized, mi(max) can be increased by approximately
15.5% (i.e. 2/sqrt(3) ≈ 1.155) as
-* 42( ) ( ) 13
d compi i
sw
Tm m max
T
≤ = −
u . (3.10)
If mi(u*) is less than the mi(max) thresholds given in (3.9) and (3.10), then it is considered as an
optimal mi level. Otherwise, if mi(u*) exceeds the mi(max) thresholds, then the dmax and dmin
thresholds are also violated, and it is considered sub-optimal mi level. Additionally, the mi(max)
38
thresholds can be increased for the single-sampling method, which is further explained in
Appendix C.
3.1.6 Application example: one-cycle deadbeat control method
-d compT
samplings
Carriersw sampT T=
computations1: conversion2: speed control3: current control
duty cycle range ofimmediatePWM update
*[ ]ku *[ 1]k +u
immediate PWM update
1z−
ideal response time of one sampT
[ ]-thk [ 1]-thk +*start : [ ]ki
[ ]ki [ 1]k +i
1 2 3
*end : [ 1] [ ]k k+ =i i
Fig. 3.5. Timing diagram of one-cycle deadbeat control
The deadbeat control is a particular application case of discrete-time feedback controls
that places poles directly at the origin. For deadbeat responses, the controller gain K of Gc(z) is
set equal to 1, which is accomplished by equating the open-loop crossover frequency ωcc to the
1/6th of the fsamp (i.e. ωcc = 2πfsamp/6) in the (3.7). When K = 1, the closed-loop transfer function
GI(z) becomes 1/z, and the current control loop of Fig. 3.3 becomes the one-cycle deadbeat
control, and Fig. 3.5 illustrates its timing diagram. It is referred as the one-cycle deadbeat
because the measured current at the [k+1]-th period (i.e. i[k+1]) ideally equals the current
reference i*[k] at the beginning of the [k]-th period.
39
3.2 Plant modeling and control design with delayed PWM update
method
3.2.1 Plant modeling and conventional control design
The delayed PWM update method can be utilized to avoid the reduced duty cycle range
of the immediate PWM update method, but the delayed PWM update method causes the one-step
control delay Td-one. The delay amount of the Td-one is equivalent to a sampling period, and thus
the Td-one is modeled with a delay operator as 1/z in the scalar domain. An equivalent delay
operator in the synchronous-reference frame using the complex-vector is modeled as
1/z/exp(jωeTsamp) to account for the coordinate rotation during the delay (a.k.a. Euler rotation)
[35]. Conventionally, the Td-one is included as a part of the plant as
( ) ( )_ -1
e sampp d one p j TG z G zze ω= . (3.11)
However, it is more accurate to consider the Td-one as a part of the controller, since the delay is
the result of the controller’s characteristic. Thus, Gp_d-one(z) is not used, and the original Gp(z) in
(3.1) is continuously utilized.
For the delayed PWM update method, the controller Gc(z) in (3.2) is modified as
( )( ) ( ) ( )( )
*ˆ e sampj T
c
zG z z z e
zω= +
uE
e, (3.12)
which includes the back-emf with a sampling period advancement term (i.e. zE^ ) and the Euler
rotation compensation term (i.e. exp(jωeTsamp)). When the delay operator is added to the control
loop to consider the Td-one, the controller Gc_d-one(z) is derived as
40
( ) ( )( )
( )( )
( ) ( )( )( ) ( )
* *-
_ -1
1ˆ
ˆ
e samp
e samp
e samp
d onec d one j T
j Tc j T
c
z zG z
z z ze
G z z z eze
G zz
z
ω
ωω
= =
= +
= +
u ue e
E
E
, (3.13)
where ud-one* is the actual inverter output voltage after the one-step control delay.
*i
( )ˆ ˆ1
ˆˆ
1
e sampj Te z eKRe
ω α
α
− −
−
−−
1z− ˆzE
Digital Controller
e*u*v
e sampj Te ω 1e sampj Tze ω
d oneT −
*-d oneu
Ei
Discrete Plant Model
( )1
1
11e sampj T
z eR e z e
α
ω α
− −
− −
−
−vu
Fig. 3.6. Conventional current control loop with considering Td-one
Fig. 3.6 illustrates the conventional current control loop with considering the Td-one
according to Gp(z) and Gc_d-one(z). The Td-one is modeled as a separate unit, and the existence of
the Td-one indicates that the delayed PWM update method is utilized. The open-loop gain
TI_d-one(z) is derived as
( ) ( )( ) ( ) ( ) ( ) ( )_ - _ - 1I d one c d one p
z KT z G z z G zz z z
= = − = −i
Ee
, (3.14)
and the closed-loop system transfer functions GI_d-one(z) is derived as
( ) ( )( )
( )( ) ( )
_ -_ - *
_ -1 1I d one
I d oneI d one
T zz KG zz T z z z K
= = =+ − +
ii
. (3.15)
The computation of the controller gain K remains the same as shown in (3.7).
41
3.2.2 Predictive control design
1e sampj Tze ω
Digital Controller
ˆe sampj Te ω
*i
( )ˆ ˆ1
ˆˆ
1
e sampj Te z eKRe
ω α
α
− −
−
−−
1z− ˆzEe
*v
i
Prediction
ˆ
ˆ1 1
ˆ e sampj Te
z Re
α
ω
−−ˆ
ˆe sampj Te
e
α
ω
−
d oneT −
*u *-d oneu
E
vui
Discrete Plant Model
( )1
1
11e sampj T
z eR e z e
α
ω α
− −
− −
−
−
Fig. 3.7. Predictive current control loop with considering Td-one
Fig. 3.7 illustrates the predictive current control loop, which is another method of
considering the Td-one. Instead of the unity current feedback i, the predicted current feedback i^ is
used [36] [37].
To derive the i^[k+1], the plant model Gp(z) in (3.1) is decomposed into scalar difference
equation forms, and then these are advanced by one sampling step. The difference equation
for i^q[k+1] is derived as
[ ][ ] ( ) [ ]
( )( ) [ ]
( )ˆˆ *ˆˆ 1 1sin 1ˆ 1
ˆ ˆcos cosqq e samp d
qe samp e samp
e v ke i k T i ki k
T R T
αα ω
ω ω
−− − −− ++ = + , (3.16)
and the difference equation for i^d[k+1] is derived as
[ ][ ] ( ) [ ]
( )( ) [ ]
( )ˆˆ *ˆˆ 1 1sin 1ˆ 1
ˆ ˆcos cosdd e samp q
de samp e samp
e v ke i k T i ki k
T R T
αα ω
ω ω
−− − −+ ++ = + . (3.17)
In (3.16) and (3.17), the predictions of i^q[k+1] and i^d[k+1] on the left side require i^d[k+1] and i^
q[k+1] on the right side, respectively, which are presently not known to the control system at the
[k]-th sampling period. To make the equations causal and computable, it is assumed that i^d[k+1]
equals i d* [k] for the prediction of i^ q[k+1], and sequentially i^ d[k+1] is computed using the
predicted i^q[k+1]. i^[k+1] is constructed from i^q[k+1] and i^d[k+1].
42
The current predictor model is also derived from the plant model Gp(z) in (3.1) as
( ) ( ) ( ) ( )( ) ( )
( ) ( )
1 *
ˆ ˆ1 *
ˆ ˆ
ˆ
1ˆe samp e sampj T j T
z z z A z B z
A z z B z
e ez z ze Re
α α
ω ω
−
− −−
= = +
= +
−= +
i i i v
i v
i v
, (3.18)
where A is a shorthand of the coefficient of the first term in the right hand side, and B is a
shorthand of the coefficient of the second term in the right hand side. Based on the plant model
Gp(z) in (3.1), the controller Gc(z) in (3.12), and the predictor model i^(z) in (3.18), the open-loop
transfer function TI_pred(z) is derived as
( ) ( )( ) ( ) ( ) ( ) ( ){ }( ) ( ) ( ){ }( ) ( ) ( )
1_ _ -
1
ˆ
1
I pred c d one p p
cp p
c cp
i zT z G z z G z G z B A
e z
G zG z G z B A
zG z G z
B G z Az z
Kz
−
−
= = − +
= +
= +
=−
E
, (3.19)
and the closed-loop system transfer functions GI_ pred(z) is derived as
( )( ) ( ) ( )
( ) ( ) ( ) ( ){ }
( )
_ -_ 1
_ -
2
1
1
11
c d one pI pred
c d one p p
G z z G zG z
G z z G z G z B A
Kz z K
K z z Kzz
−
− = + − +
−= =
− ++−
E
E
. (3.20)
The computation of the controller gain K remains the same as (3.7).
43
3.2.3 Control computation sequence
Speed control computation
Current control computation
Duty cycle range
*[ ]ki *[ 1]k +i
*[ 1]k +u Delayed PWM update
*[ 1]k +u *[ 2]k +u
[ ]-thk [ 1]-thk +
Position samplingCurrent sampling
Sampling period[ ]kθ [ 1]kθ +[ ]ki [ 1]k +iˆ [ ]e kω ˆ [ 1]e kω + Speed estimation
*[ ]ku
[ 1]k +i [ 2]k +i Current prediction
Fig. 3.8. Timing sequence with considering Td-one
Fig. 3.8 illustrates an example timing sequence with considering the one-step control
delay Td-one. The delayed PWM update method is utilized to enable the full duty cycle range, but
it causes the Td-one.
An entire Tsamp is allocated for the samplings and computations, and many operations are
executed during the allocated Tsamp, and a typical control computation sequence is as follows. At
the beginning of the [k]-th Tsamp, the position θ[k] and current i[k] are sampled simultaneously.
The speed feedback ω^ e[k] is estimated, and the speed controller computation generates the
current reference vector i*[k]. When the current controller compute the reference voltage vector
for next cycle u*[k+1], the conventional current control utilizes the sampled current vector i[k] as
the feedback vector, and the predictive current control utilizes the predicted current vector i^[k+1]
as the feedback vector. Using an appropriate feedback vector, u*[k+1] is computed using the
modified Gc(z) in (3.12). The delayed PWM update method is utilized to avoid the loss of duty
cycle range, in which the u*[k+1] is loaded to PWM output at the beginning of the [k+1]-th Tsamp.
44
3.2.4 Application example: two-cycle deadbeat control
samplings
Carriersw sampT T=
computations1: conversion2: speed control3: current control4: current estimation
duty cycle range ofdelayedPWM update
*[ ]ku *[ 1]k +u
delayed PWM update
2z−
ideal response time of two sampT
[ ]-thk [ 1]-thk +*start : [ ]ki
[ ]ki [ 1]k +i
1 2 3
*end : [ 2] [ ]k k+ =i i
4
-d oneT
Fig. 3.9. Timing diagram of two-cycle deadbeat control
Similar to the application example of the one-cycle deadbeat control in section 3.1.6, the
controller gain K is set equal to 1 to directly place the poles at the origin. When the K = 1, the
GI_pred(z) of (3.20) is reduced to z–2, and the current control loop of Fig. 3.7 becomes the two-
cycle deadbeat control, and Fig. 3.9 illustrates its timing diagram. It is referred as the two-cycle
deadbeat because the measured current at the [k+2]-th period (i.e. i[k+2]) ideally equals the
current reference i*[k] at the beginning of the [k]-th period.
45
3.3 Stability and robustness analysis of the conventional and predictive
controls
3.3.1 Current controller open-loop crossover frequency (ωcc) selection
The design objective is to achieve the maximum closed current loop bandwidth. Thus, the
open-loop crossover frequency ωcc is designed according to the “Magnitude Optimum” (MO)
design principle [38], which is to maintain the closed-loop magnitude frequency response curve
as flat and as close to unity for large a bandwidth as possible for a given plant and controller
combination. For other design objectives, different tuning methods can be employed. For
example, a tuning method for optimized settling time and overshoot has been proposed in [8],
which suggests setting ωcc to 4% of the sampling frequency.
For the plant modeling and control design without considering the Td-one, the open-loop
transfer function TI(z) is K/(z–1) as shown in (3.3). For the MO design, the ωcc value that
corresponds to the 1/6th of the fsamp is selected (i.e. ωcc = 2πfsamp/6). For the plant modeling and
conventional control design with considering the Td-one, the open-loop transfer function TI_d-one(z)
is K/z/(z–1) as shown in (3.14). For the MO design, the ωcc value corresponds to the 1/18th of the
fsamp is selected (i.e. ωcc = 2πfsamp/18). For the plant modeling and predictive control design with
considering the Td-one, the open-loop transfer function TI_pred(z) is K/(z–1) as shown in (3.19),
which is the same as the TI(z). Thus, for MO design, ωcc equals 2πfsamp/6. The controller gain K
values as a function of the ωcc can be computed using K(ωcc) in (3.7).
46
IT_ -I d oneT
_I predT
(a)
2 / 6cc sampfω π=
(b)
IT_ -I d oneT
_I predT
2 /18cc sampfω π=
Fig. 3.10. Open-loop Bode plots of TI(z), TI_d-one(z), and TI_pred(z)
(a) ωcc = 2πfsamp/6 (a) ωcc = 2πfsamp/18
Fig. 3.10 illustrates the Bode plots of the open-loop transfer functions TI (z), TI_d-one(z)
and TI_pred(z) when ωcc equals 2πfsamp/6 and when ωcc equals 2πfsamp/18. The fsamp is 20 kHz. The
open-loop gain and phase margins can be obtained from the figures.
47
(b)
_I predG_ -I d oneG
IG 1.52kHz 1.62kHz
1.38kHz 2.65kHz
(a)
_I predG_ -I d oneG
IG5.0kHz2.5kHz
Fig. 3.11. Closed-loop Bode plots of GI(z), GI_d-one(z) and GI_pred(z)
(a) ωcc = 2πfsamp/6 (a) ωcc = 2πfsamp/18
Fig. 3.11 illustrates the Bode plots of the closed-loop transfer functions GI (z), GI_d-one(z)
and GI_pred(z) when ωcc equals 2πfsamp/6 and when ωcc equals 2πfsamp/18. The ±3 dB qualification
and –90º qualification are utilized for the bandwidth evaluation as stated in section 2.4.1, and the
closed-loop bandwidths can be obtained from the figures.
48
Table 3.1. Gain and phase margins and closed current loop bandwidth
ωcc Gain Margin Phase Margin Bandwidth (±3dB)
Bandwidth (-90˚)
TI(z) & GI(z) 2πfsamp/6 6.02 dB 60 ˚ Inf. 5 kHz 2πfsamp/18 15.2 dB 80 ˚ 1.38 kHz 2.74 kHz
TI_d-one(z) & GI_d-one(z)
2πfsamp/6 0.0 dB 0 ˚ – – 2πfsamp/18 9.19 dB 60 ˚ 2.65 kHz 1.62 kHz
TI_pred(z) & GI_pred(z)
2πfsamp/6 6.02 dB 60 ˚ Inf. 2.5 kHz 2πfsamp/18 15.2 dB 80 ˚ 1.38 kHz 1.52 kHz
Table 3.1 summarize the gain and phase margins from Fig. 3.10 and the bandwidths from
Fig. 3.11. When ωcc equals 2πfsamp/6, both TI(z) and TI_pred(z) have 6.02 dB gain margin and 60°
phase margin and are stable; however, TI_d-one(z) is left with zero gain and phase margins. When
ωcc equals 2πfsamp/18, all of TI(z), TI_d-one(z), and TI_pred(z) are stable with good gain and phase
margins. However, both TI(z) and TI_pred(z) have an additional 6 dB gain margin and an
additional 20° phase margin than TI_d-one(z). The additional stability margins of TI(z) and TI_pred(z)
are acquired from the reduced Td-total and the predictive feedback, respectively.
The closed-loop bandwidth is evaluated with the ±3 dB qualification and –90º
qualification. The magnitudes of GI(z) and GI_pred(z) are 0 dB throughout the entire frequency
range when ωcc equals 2πfsamp/6; therefore, the ±3 dB qualification cannot be obtained. When 60º
phase margin is used as the benchmark, the bandwidth of GI(z) is two and three times higher than
the bandwidth of GI_pred(z) and GI_d-one(z), respectively. GI(z) has the highest –90º bandwidth, and
GI_pred(z) has the lowest –90º bandwidth.
When ωcc equals 2πfsamp/18, the ±3 dB bandwidth of GI_d-one(z) is larger than the
bandwidths of GI(z) and GI_pred(z), but GI(z) and GI_pred(z) have larger stability margins than
GI_d-one(z).
49
3.3.2 Theoretical stability range with respect to the parameter uncertainty
When the estimated values are not equal to the actual parameters (i.e. L^ ≠L and R^ ≠R), the
assumption of the perfect pole-zero cancellation is no longer valid. Thus, the previous loop gain
transfer functions and closed-loop transfer functions must be reevaluated.
For the plant modeling and control design without considering the Td-one, the original TI(z)
in (3.3) must be reevaluated as
( )ˆ ˆ
ˆ
ˆ 11 1
e samp
e samp
j T
I j TK R e ze eT z
z R e ze e
ωα α
ωα α
− −
− −
− −= − − −
, (3.21)
and the original GI(z) in (3.4) must be reevaluated as
( ) ( )( )
( )( )( ) ( )( ) ( )( )
ˆ ˆ
ˆˆ ˆ
1ˆ 1
ˆ1 1 1
e samp
e samp e samp
II
I
j T
j T j T
T zG z
T z
KR e ze e
z R e ze e KR e ze e
ωα α
ω ωα α α α
− −
− − − −
=+
− −=
− − − + − −
. (3.22)
Similarly, for the plant modeling and conventional control design with considering the
Td-one, the original TI_d-one(z) in (3.14) must be reevaluated as
( ) ( )
ˆ ˆ
_ ˆ
ˆ 11 1
e samp
e samp
j T
I d one j TK R e ze eT z
z z R e ze e
ωα α
ωα α
− −
− − −
− −= − − −
, (3.23)
and the original GI_d-one(z) in (3.15) must be reevaluated as
( ) ( )( )
( )( )( ) ( )( ) ( )( )
_ -_ -
_ -
ˆ ˆ
ˆˆ ˆ
1
ˆ 1ˆ1 1 1
e samp
e samp e samp
I d oneI d one
I d one
j T
j T j T
T zG z
T z
KR e ze e
z z R e ze e KR e ze e
ωα α
ω ωα α α α
− −
− − − −
=+
− −=
− − − + − −
. (3.24)
Similarly, for the plant modeling and predictive control design with considering the
Td-one, the original TI_pred(z) in (3.19) must be reevaluated as
50
( ) ( )
ˆ ˆˆ ˆ ˆ
_ ˆ ˆˆ
ˆ 11 1
e samp e samp
e sampe samp e samp
j T j T
I pred j Tj T j TK ze e R e ze e eT z
z z R e ze ee e
ω ωα α α α
ωω ωα α
− − − −
− −
− − −= + − − −
, (3.25)
and the original GI_ pred(z) in (3.20) must be reevaluated as
( )( ) ( ) ( )
( ) ( ) ( ) ( ){ }
( ) ( )
_ -_ 1
_ -
ˆ ˆ
ˆ
ˆ ˆ ˆˆ ˆ
ˆ ˆˆ
1
ˆ 11
ˆ1 111
e samp
e samp
e sampe samp
e sampe samp e samp
c d one pI pred
c d one p p
j T
j T
j Tj T
j Tj T j T
G z z G zG z
G z z G z G z B A
R ze e eKR eze e
R ze e e ez z K ze e KR eze ee e
ω α α
ω αα
ω α α αω α
ωω ωαα
−
− −
−−
− − −−
−−
− = + − +
− −−−=
− −− + − +
−−
E
E
. (3.26)
The parameter sensitivity of these three cases can be analyzed in several different ways.
One way is to evaluate the migration pattern of the complex-vector eigenvalues (a.k.a.
characteristic roots) as in [30], and the location of the complex-vector eigenvalues can be
examined for stability. Another way is to simply provide the boundary condition between the
stability and instability as in [7, 39]. The formal method is utilized in this section.
The evaluation of parameter uncertainty can be performed on the inductance L, resistance
R, synchronous frequency ωe, and back-emf E; however, only the uncertainty between L and L^ is
considered. The reasons for not evaluating other parameters are as follows. First, the uncertainty
between R and R^ does not significantly affect the stability, as reported in [7, 30, 39]. Second, the
uncertainty between ωe and ω^ e should small because the position is measured, and thus ω^ e should
be well estimated. Lastly, if E^ is estimated based on the multiplication between ω^ e and the back-
emf constant, then E^ should be well estimated. Additionally, any slow-varying difference
between E and E^ is compensated by the integrating action within the controller Gc(z) in (3.2).
Therefore, the parameter uncertainty analysis on R, ωe, and E are not considered.
51
2 1000 rad/seω π= ⋅
ˆ 0.0L L= ⋅ˆ 2.0L L= ⋅
ˆincreasing L
(a)
ˆ 5.8L L= ⋅
ˆincreasing L
ˆ 0.0L L= ⋅
2 1000 rad/seω π= ⋅
(b)
Fig. 3.12. Eigenvalue migration patterns of GI(z) when L^ is varied
(a) ωcc = 2πfsamp/6 (b) ωcc = 2πfsamp/18
(b)
2 1000 rad/seω π= ⋅
ˆ 2.9L L= ⋅
ˆincreasing L
ˆ 0.0L L= ⋅
ˆ 0.0L L= ⋅
(a)
2 1000 rad/seω π= ⋅
ˆ 1.0L L= ⋅
ˆincreasing L
ˆ 0.0L L= ⋅
ˆ 0.0L L= ⋅
Fig. 3.13. Eigenvalue migration patterns of GI_d-one(z) when L^ is varied
(a) ωcc = 2πfsamp/6 (b) ωcc = 2πfsamp/18
52
2 1000 rad/seω π= ⋅
ˆ 0.1L L= ⋅
ˆ 2.0L L= ⋅
ˆincreasing L
ˆ 2.0L L= ⋅
ˆ 0.1L L= ⋅
(a)
ˆ 0.0L L= ⋅
2 1000 rad/seω π= ⋅
ˆ 0.1L L= ⋅
ˆincreasing L
ˆ 3.6L L= ⋅
ˆ 0.1L L= ⋅
(b)
ˆ 0.0L L= ⋅
Fig. 3.14. Eigenvalue migration patterns of GI_pred(z) when L^ is varied
(a) ωcc = 2πfsamp/6 (b) ωcc = 2πfsamp/18
Fig. 3.12, Fig. 3.13, and Fig. 3.14 illustrate the eigenvalue migration patterns of GI(z),
GI_d-one(z) and GI_pred(z), respectively, when L^ is varied. Two cases are considered: ωcc = 2πfsamp/6
and ωcc = 2πfsamp/18. These eigenvalue migration patterns are numerically evaluated instead of
deriving closed form equations. The nominal L is 100 μH, ωe is 2∙π∙1000 rad/s, and fsamp is
20 kHz. L^ is varied in 10% increments from 0.0∙L until the poles move outside of the unit circle,
which indicates an unstable system. To minimize the damping effect of the resistance, R is set to
a small value of 1 mΩ.
Table 3.2. Stability boundary of GI(z), GI_d-one(z) and GI_pred(z)
ωcc Lower stability
boundary Upper stability
boundary
GI(z) 2πfsamp/6 L^ = 0.0∙L L^ = 2.0∙L 2πfsamp/18 L^ = 0.0∙L L^ ≈ 5.8∙L
GI_d-one(z) 2πfsamp/6 L^ = 0.0∙L L^ = 1.0∙L 2πfsamp/18 L^ = 0.0∙L L^ ≈ 2.9∙L
GI_pred(z) 2πfsamp/6 L^ = 0.0∙L L^ = 2.0∙L 2πfsamp/18 L^ = 0.0∙L L^ ≈ 3.6∙L
53
Table 3.2 summarizes the stability boundaries of GI(z), GI_d-one(z) and GI_pred(z). The
lower stability boundaries of all cases are at 0.0∙L, which implies that all systems can tolerate the
under-estimation of inductance. The stability boundary is determined based on the ratio
between L^ and L, and it should be noted that the error made on the estimated inductance L^ is
equivalent to the variation of L. The upper stability boundaries are different, and it can be
summarized as GI(z) has the largest upper boundary and GI_d-one(z) has the smallest boundary.
The effect of the inductance variations can be summarized as following. First, if L^ > L,
then the actual bandwidth is higher than the designed bandwidth. Second, if R^ > R, then it
slightly decreases the bandwidth, but its effect is negligible. In other words, the damping effect
of R can slightly widen the stability boundary when R is larger, but the increment can be ignored
for the purpose this analysis. Third, if L and R are varied simultaneously while the estimated time
constant (L^ /R^ ) remains the same as the actual system time constant (L/R), then the pole-zero
cancellation remains perfect (cf. (3.21)). Therefore, it is more important to estimate the correct
time constant than the individual inductances or resistances to maintain perfect pole-zero
cancellations. Additionally, if (L^ /R^ ) > (L/R), then it increases the scalar gain of the loop; thus it
has the same effect as the increasing the desired ωcc. With regards to the instability boundary, the
phases of TI(z) and TI_pred(z) cross the –180° at the Nyquist frequency as it can be observed in
Fig. 3.10. Therefore, the system is stable as long as the effective ωcc stays below the Nyquist
frequency.
The deadbeat characteristics can be observed in the GI(z) with ωcc=2πfsamp/6 and the
GI_pred(z) with ωcc=2πfsamp/6. When K(2πfsamp/6) is evaluated using (3.7), it yields 1. In turn, the
closed-loop responses of GI(z) and GI_ pred(z) become equivalent to one and two sampling period
delays, respectively. It is equivalent to placing the closed-loop poles at the origin of the complex
54
plane in the discrete-time domain, which corresponds to the poles at the minus infinity in the
continuous-time domain. This pole placement at the origin is similar to deadbeat/predictive
control schemes [4, 5, 23]. This fact is also noticeable in the closed-loop Bode plot of Fig. 3.11.
The magnitude curve is flat for all frequency, while the phase delays are –180° and –360° at the
Nyquist frequency. These cases are previously discussed in the application examples in sections
3.1.6 and 3.2.4.
3.3.3 Robustness against inverter non-linear characteristics
The robustness against inverter non-linear characteristics is discussed for the
conventional control without considering the Td-one when ωcc=2πfsamp/6 (i.e. one-cycle deadbeat
control) and the predictive control without considering the Td-one when ωcc=2πfsamp/6 (i.e. two-
cycle deadbeat control).
Above analysis of the parameter uncertainty yields that both GI(z) and GI_pred(z) have the
same stability ranges when ωcc=2πfsamp/6 (i.e. 0.0∙L < L^ < 2.0∙L). However, the practical stability
range is less than the theoretical values due to disturbances. An assumption during analysis is
that the applied inverter voltage vector u accurately matches the inverter voltage reference vector
u* (i.e. u = u* in Fig. 3.3 and u = ud-one* in Fig. 3.7). However, u deviates from u* due to inverter
non-linear characteristics, such as the deadtime and voltage drops across the IGBTs and diodes.
These and other non-linear characteristics can be considered as disturbances. Although simple
deadtime and on-state voltage compensation methods can be utilized to reduce the deviation
between u and u*, these are only partially effective due to its inability to account for the non-
linearity. More advanced compensation methods, such as disturbance feedforward [37, 40, 41],
have a limited bandwidth and cannot compensate when the disturbances are faster than its
bandwidth.
55
*i
( )ˆ ˆ1
ˆˆ
1
e sampj Te z eKRe
ω α
α
− −
−
−−
1z− E
Digital Controller
e*u*v
Ei
Discrete Plant Model
( )1
1
11e sampj T
z eR e z e
α
ω α
− −
− −
−
−vu
1e sampj Tze ω
Digital Controller
ˆe sampj Te ω
*i
( )ˆ ˆ1
ˆˆ
1
e sampj Te z eKRe
ω α
α
− −
−
−−
1z− ˆzEe
*v
i
Prediction
ˆ
ˆ1 1
ˆ e sampj Te
z Re
α
ω
−−ˆ
ˆe sampj Te
e
α
ω
−
d oneT −
*u *-d oneu
E
vui
Discrete Plant Model
( )1
1
11e sampj T
z eR e z e
α
ω α
− −
− −
−
−
(a)
(b)
Fig. 3.15. Current control loops
(a) conventional and (b) predictive
Although it is difficult to model how disturbances affect the stability, the robustness
against the inverter’s non-linear characteristics can be compared between the one-cycle and two-
cycle deadbeat controls through simple inspections. Fig. 3.15 duplicates the convention current
control without considering the Td-one in Fig. 3.3 and the predictive current control with
considering the Td-one in Fig. 3.7 for the ease of reference. The deviation between u and u* in Fig.
3.15(a) is the same as the deviation between u and ud-one* in Fig. 3.15(b) since the PWM is
modulated using the same VSI. Thus, its effects on the forward gain through the controller and
plant are the same in both. However, the feedback paths of the conventional and predictive
controls are different. The conventional control’s feedback is a simple unity feedback, whereas
the predictive control’s feedback gain is a current predictor; thus the deviation between u and
ud-one* causes an inaccurate current prediction, which leads to a less robustness.
Due to this vulnerability of the predictive control, the conventional control is inherently
more robust against the inverter non-linear characteristics than the predictive control.
56
Experiments are performed between one-cycle and two-cycle deadbeat controls, which are
presented in later sections. It confirms that the stability and performance degradations are indeed
more noticeable with the two-cycle deadbeat control that uses the predictive feedback path.
57
3.4 Hybrid PWM update method
When the immediate PWM update method is utilized, the one-step control delay Td-one is
eliminated at the expense of the loss of the duty cycle range. When the delayed PWM update
method is utilized, the full duty cycle range is restored, but it causes the Td-one. Thus, some
disadvantage exists when only one of either the immediate or the delayed PWM update method
is utilized.
In this dissertation, a hybrid PWM update method is proposed to overcome these
disadvantages and to eliminate the effect of the Td-one without the loss of the duty cycle range.
Additionally, a hybrid control method is proposed to optimize the sequence of control operations
and to take full advantages of the proposed hybrid PWM update method.
3.4.1 Proposed hybrid PWM update method
* [ ]im ku * [ 1]im k +u{ immediate PWM update(a)
*duty cycle range of imu
current samplings[ ]ki [ 1]k +i
* [ 1]dy k +u
delayed PWM update
(b)*duty cycle range of dyu
[ ]ki [ 1]k +i{ [ 1]k +icurrent prediction
Fig. 3.16. Conventional PWM update methods
(a) conventional control with immediate PWM update (b) predictive control with delayed PWM update
Fig. 3.16 illustrates the conventional PWM update methods, in which the PWM output is
updated only one time per Tsamp. Fig. 3.16(a) illustrates the conventional control with the
immediate PWM update method, in which the inverter voltage reference uim* is computed with a
measured current feedback vector i feedback. Fig. 3.16(b) illustrates the predictive control with
the delayed PWM update method that the inverter voltage reference udy* is computed with a
58
predicted current vector i^ feedback. The subscript ‘dy’ and ‘im’ are used to indicate the delayed
and immediate PWM update methods, respectively.
Hybrid PWM update
*Duty cycle range of hyu-d compT
Current samplings[ 1]k −i [ ]ki
* [ ]dy ku * [ ]im ku
[ ]ki Current prediction[ 1]k +i
Fig. 3.17. Hybrid PWM update method
Fig. 3.17 illustrates the proposed hybrid PWM update method. The hybrid PWM update
method is a simple concept that the PWM outputs are updated two times per Tsamp using both the
delayed and immediate PWM update methods. The first PWM update is executed at the
beginning of a sampling period using the delayed PWM update method, and the second PWM
update is executed in the middle of a sampling period using the immediate PWM update method.
The solid up-arrows indicate the delayed PWM updates, and the hollow up-arrows indicate the
immediate PWM updates. Since there are two PWM updates, two inverter voltage references are
required for each update, in which udy* and uim* are utilized for the delayed and immediate PWM
updates, respectively. Similar to uim* and udy* in Fig. 3.16, uim* is computed with the measured
current vector i and udy* is computed with the predicted current vector i^. The control design for
udy* and uim* , which is referred as the hybrid control design, is discussed in later sections.
As shown in Fig. 3.17, udy* is written at the beginning, and uim* over-writes udy* in every
Tsamp. Therefore, a combination of udy* and uim* creates the hybrid PWM update method’s inverter
voltage reference uhy* . The subscript ‘hy’ is used to indicate the hybrid PWM update method. The
full duty cycle range of the uhy* is guaranteed with the delayed PWM update.
59
It should be noted that the number of sampling per Tsamp is the same for both the
conventional and hybrid PWM update methods. The current is sampled once per Tsamp, and the
current sampling is restricted to the carrier peaks as discussed in section 2.1.
3.4.2 Non-ideal control computation sequence
Position samplingCurrent sampling
[ ]kθ [ 1]kθ +[ ]ki [ 1]k +i
-d compT
* [ 1]dy k +u* [ ]dy ku Delayed PWM update
Speed controlCurrent control
*[ ]ki *[ 1]k +i
* [ ]im ku * [ 1]im k +u Immediate PWM update
* [ ]im ku * [ 1]im k +u
[ 1]k +i* [ 1]dy k +u
[ 2]k +i* [ 2]dyu k + Current control
Current prediction
ˆ [ ]e kω ˆ [ 1]e kω + Speed estimation
*Duty cycle range of dyu
*Duty cycle range of imu
[ ]-thk [ 1]-thk +Sampling period
Simultaneous sampling: position & current
Fig. 3.18. Non-ideal control sequence of the hybrid PWM update method
Typically, the position θ and current i are sampled simultaneously as shown in sections
3.1.4 and 3.2.3. If the simultaneous sampling method is maintained, then the hybrid PWM update
method suffers from the non-ideal control sequence as shown in Fig. 3.18.
The computation sequence is as follows. First, at the beginnings of the [k]-th Tsamp, the
delayed PWM update is executed with udy* [k], which is computed from the previous Tsamp. At the
same time, the position θ[k] and current vector i[k] are sampled simultaneously. Second, the
speed feedback ω^ e[k] is estimated. Third, the speed controller produces the current reference
vector i*[k]. Fourth, the current controller Gc(z) in (3.2) generates uim* [k] based on i*[k] and i[k].
Fifth, uim* [k] is immediately loaded to PWM outputs via the immediate PWM update. Sixth, the
current prediction algorithm generates the i^[k+1]. Lastly, the current controller Gc_d-one(z) in
60
(3.13) generates udy* [k+1] based on i*[k] and i^[k+1], in which the sequence returns to the first step
and udy* [k+1] is loaded at the beginning of the [k+1]-th Tsamp via the delayed PWM update.
This computation sequence is non-ideal for two reasons. The first reason is that uim* [k]
and udy* [k] are generated using two different reference values. For the [k]-th Tsamp, uim* [k] is
generated with i*[k] and i[k], and udy* [k] is generated with i*[k–1] and i^[k]. If uim* [k] and the udy* [k]
are generated using two different reference values i*[k] and i*[k–1], respectively, then uim* [k] most
likely do not match udy* [k], even if i^[k] is well estimated to match i[k]. The discrepancy between
two reference vectors worsens if a transient is occurring. One possible solution is to generate uim*
[k] using i*[k–1] instead of i*[k], which synchronizes the references of both uim* [k] and udy* [k].
Although it may solve the reference vector discrepancy problem, the delay from the sampling of
i*[k–1] to the generation of uim* [k] is increased, which is undesirable,
The second reason is that the duty cycle range of uim* is much reduced due to a large
computation time of the Td-comp, which is the sum of speed estimation, speed control, and current
control. Ideally, it is desirable to maintain the Td-comp as short as possible to keep the system more
robust, and its reasons are explained in later sections.
61
3.4.3 Improved ideal control computation sequence
Position sampling
Current sampling
Speed control
Current control
*[ ]ki *[ 1]k +i
* [ ]im k >< u * [ 1]im k + >< u Immediate PWM update
[ ]kθ [ 1]kθ +
[ ]ki [ 1]k +i* [ ]im ku * [ 1]im k +u
[ 1]k +i
* [ ]dy ku* [ 1]dy k +u* [ ]dy ku
[ 2]k +i
* [ 1]dy k +u Current control
Current prediction
Delayed PWM update
ˆ [ ]e kω ˆ [ 1]e kω + Speed estimation
compT θ−
*Duty cycle range of imu-d compT
*Duty cycle range of deu
*First interrupt: position sampling & computationdeu*Second interrupt: current sampling & computationimu
[ ]-thk [ 1]-thk +Sampling periodCarrier
Fig. 3.19. Ideal control sequence of the hybrid PWM update method
Fig. 3.19 illustrates the ideal control sequence of the hybrid PWM update method, which
properly utilizes the hybrid PWM update method.
Two separate interrupt routines are utilized for the samplings of the position θ and current
i, instead of the simultaneous samplings of the two. The first interrupt routine starts with the θ[k]
sampling, and the interrupt is utilized for the computation of udy* . The interrupt instant starts
ahead of the peaks of the carrier, and this is acceptable since variables other than the currents can
be typically sampled at the non-peak position without incurring switching noise induced
harmonics. During this interrupt, ω^ e[k] is estimated, the speed controller computation generates
i*[k], and then the current controller Gc(z) in (3.2) generates udy* [k] using i*[k] and i^[k], in which i^
[k] is computed during the previous Tsamp. It ends the first interrupt routine, and the duration of
the first interrupt routine is referred as the Tθ-comp as shown in Fig. 3.19.
To minimize the delay from the position θ sampling to the delayed PWM update instant
of udy* [k], the beginning of the Tθ-comp is adjusted that its end is slightly ahead of the PWM
62
loading instant of udy* [k]. By moving the position θ sampling and speed ω^ e estimation as close as
possible toward the PWM loading instant, the delay from the perspective of the speed control
loop can be significantly reduced, and in turn, the speed loop bandwidth can be increased. A
similar concept has been previously reported in [5, 42].
The second interrupt routine start with the delayed PWM update of udy* [k] at the carrier
peak, as shown in Fig. 3.19. At the same time, the current i[k] is sampled to avoid the switching
noise induced harmonics. The only operation during the second interrupt routine is the
generation of uim* [k] based on i*[k] and i[k] using the current controller Gc(z) in (3.2). As soon as
uim* [k] is computed, uim* [k] is immediately updated to PWM outputs, which replaces udy* [k]. After
the immediate PWM update, the i^[k+1] is estimated for the computation of udy* [k+1].
Unlike the non-ideal control sequence in Fig. 3.18, the proposed ideal sequence
synchronizes the references of the udy* [k] and uim* [k]. For the [k]-th Tsamp, udy* [k] is generated with
i*[k] and i^[k], and uim* [k] is generated with i*[k] and i[k]; therefore, udy* [k] value should be very
similar to uim* [k] value as long as i^[k] is well estimated to match i[k]. Additionally, the duty cycle
range of uim* within uhy* is maximized by minimizing the duration of the Td-comp. Many operations,
such as the speed estimation, speed control, and current control for the udy* , are executed during
the Tθ-comp. Therefore, only the generation of uim* is executed during the Td-comp. This leads to a
better robustness of current loop under a wider mi range.
The proposed control sequence accomplishes two things. First, the delay seen by the
speed controller is minimized by moving the position sampling and speed estimation as close as
possible to the beginning of the current loop. Second, the duration of the Td-comp is minimized,
which increases the robustness of current loop under a wider mi range.
63
3.5 PWM output behaviors of hybrid PWM update method
cs
cs
2dcv
2dcv
au
bu
cu
nu
as
as
bs
bs
su
Three-phase SystemVoltage Source Inverter
LR E
Fig. 3.20. Three-phase VSI and a generic three-phase RLE load model
Conceptually, udy* is updated at the beginning of a Tsamp, and the update of uim* replaces udy*
in every Tsamp, as shown in Fig. 3.17. However, the literal values of udy* and uim* are not used in
the PWM output updates in practice. udy* and uim* must be converted to appropriate duty cycle
reference values as described in this section before these are applied to loads via a VSI.
For an easy reference, Fig. 3.20 duplicates the illustration of a three-phase VSI with a
generic three-phase RLE load model in Fig. 3.1. The mid-voltage of the supply voltage vdc is un.
The floating neutral point of the three-phase load is us. The output voltage of phase a, b, and c
are ua, ub, and uc, respectively. The phase voltages uxs are the voltage difference between ux and
us, in which the subscript ‘x’ refers to phase a, b, or c. The pole voltages uxn are the voltage
difference between ux and un. The neutral offset voltage usn is the voltage difference between us
and un.
64
*du
1*snu
0
referencephase voltages
referencepole voltages
bs
bs
PWM*anu
*qu
inverse coordinate
transformation2 3⇒
* *normalization
u d⇒
*ad
*bd
*cd
*bsu
*csu
*asu
*bnu
*cnu
*‹ ›ad
*‹ ›bd
*‹ ›cd
*
* *it
‹lim
›d
d d⇒
as
as
cs
csoffset voltage
injection
duty cycle limitedduty cycle
Fig. 3.21. Block diagram of operations from synchronous reference frame u* to PWM outputs
Fig. 3.21 illustrates the block diagram of operations that convert udy* and u im* in the
synchronous reference frame to PWM outputs. The conversion processes are as follows. First,
the complex-vector reference voltage u* is decomposed into the d-axis voltage reference ud* and
the q-axis voltage reference uq* (i.e. u = ud + j·uq). Second, since ud* and uq* are in the synchronous
reference frame, these are coordinate transformed to the stationary reference frame variables uas* ,
ubs* , and ucs* , which are the reference phase voltages. Third, the reference pole voltages uxn* are
computed with the reference phase voltages uxs* and the reference neutral offset voltage usn* . usn
provides a degree of freedom in determining the duty cycle of the three-phase inverter switches.
Using a degree of freedom, any arbitrary usn* can be optionally injected to uxs* to create uxn* . A
common practice is to apply the space vector PWM (SVPWM) method, which is selected as the
working example, and the offset voltage usn* computation method of the SVPWM is given as
* *
*
2max min
snu uu +
= − , (3.27)
where umax* and umin* are the maximum and minimum among uas* , ubs* and ucs* , respectively. This
offset voltage injection increases the linear mi range compared to the SPWM [43, 44]. The
computed usn* is added to uxs* to create uxn* as
65
* * *
* * *
* * *
an as sn
bn bs sn
cn cs sn
u u uu u uu u u
= +
= +
= +
. (3.28)
Fourth, the individual pole voltages uan* , ubn
* , and ucn* are normalized and translated to
individual duty cycle references da*, db*, and dc*. The range of the pole voltage is from –vdc/2 to
+vdc/2, and the range of the duty cycle is from 0 to 1. The relation between duty cycle and
inverter pole voltage is given as
0.5dc
udv
= + . (3.29)
Fifth, these duty cycle references are limited in preparation for modulation. For the
delayed PWM update, the full duty cycle range is available, and thus duty cycles are limited
between 0 and 1 (i.e. [0, 1]). For the immediate PWM update, duty cycles are limited according
to the dmax in (2.3) and dmin in (2.4) based on sampling points. If the single-sampling at top is
utilized, duty cycles are limited to [0, dmax]. If the single-sampling at bottom is utilized, duty
cycles are limited to [dmin, 1]. If the double-sampling is utilized, the limit on duty cycles is
alternated between [0, dmax] and [dmin, 1] based on the sampling point. The limited duty cycle is
marked as ‘‹d›’, as shown in Fig. 3.21. Sixth and lastly, the limited reference duty cycles ‹da*›, ‹db*
›, and ‹dc*› are compared with the carrier and modulated to PWM outputs sa, sb, and sc.
The collection of the individual duty cycle references da*, db* and dc* is referred as the duty
cycle vector dabc* . When dabc* is updated via the delayed PWM update method, it is referred as ddy* .
Similarly, when dabc* is updated via the immediate PWM update method, it is referred as dim* . The
subscript ‘abc’ is dropped to simplify expressions. It should be noted that ddy* and dim* are in the
stationary reference frame, whereas udy* and uim* are in the synchronous reference frame.
66
Conceptually, udy* is updated at the beginning, and the update of uim* replaces udy* in every
Tsamp. Practically, ddy* is updated at the beginning, and the update of dim* replaces ddy* in every
Tsamp. As discussed in the previous section, udy* and uim* may differ slightly due to a discrepancy
between the estimated current i^ and the measured current i. A slight difference between udy* and
uim* indicates a slight difference between ddy* and dim* as well. Therefore, it is important to examine
the behaviors of the hybrid PWM output method, and various cases of PWM outputs are
inspected in following sections.
3.5.1 Ideal case of when both mi(udy* ) and mi(uim
* ) are optimal
*im ad −
*dy ad −
*dy cd −
*dy bd −
*im cd −
*im bd −
(a) (b)
sampT
carrier
prohibited area
(c)
-d compTcs
asbs
duty
cyc
le (
)d
prohibited area
ZOH sample
* [ ]im kd
* [ ]dy kd
*immediate PWM update of [ ]im kd
*delayed PWM update of [ ]dy kd
*duty cycle range of [ ]im kd
1.0
0.6
0.8
0.4
0.0
0.2
1.0
0.6
0.8
0.4
0.0
0.2
Fig. 3.22. PWM outputs of the ideal case that both mi(udy* ) and mi(uim
* ) are optimal
(a) ddy* and dim
* for a half electrical period (b) ddy* and dim
* for one Tsamp (c) resulting PWM outputs
Fig. 3.22 illustrate the PWM outputs of the ideal case that both mi(udy* ) and mi(uim* ) are
optimal, in which both ddy* and dim* do not violate the dmax and dmin thresholds. The single-
sampling at top is utilized. The optimal level of a modulation index mi is discussed in section
67
3.1.5, and the dmax and dmin thresholds are discussed in section 2.2.1.1. Fig. 3.22(a) shows the
individual phases of ddy* in solid lines (i.e. ddy-a* , ddy-b* , and ddy-c* ) and the individual phases of dim* in
dashed lines (i.e. dim-a* , dim-b* and dim-c* ) for a half electrical period. The individual duty cycle
values of ddy* and dim* at the vertical line in Fig. 3.22(a) are sampled using a ZOH, and the
sampled values are the delayed and immediate PWM update values in Fig. 3.22(b).
Fig. 3.22(b) illustrates ddy* and dim* for one Tsamp along with the carrier, and Fig. 3.22(c)
illustrates the PWM outputs based on the interaction among the carrier and ddy* and dim* . The duty
cycle reference ddy* is updated at the beginning of the Tsamp, and the update of dim* at the end of
Td-comp replaces ddy* . If both mi(udy* ) and mi(uim* ) are optimal8, then all PWM output edges are the
results of the comparator action between dim* and the carrier. In other words, if all duty cycle
references of ddy* and dim* do not violate the dmax and dmin thresholds, then all PWM edges fall
inside of the dim* duty cycle range portion of the dhy* duty cycle range, as shown in Fig. 3.22(c).
8 The definition of the optimal mi level is given in (3.9) and (3.10).
68
3.5.2 Non-ideal case of when mi(udy* ) is sub-optimal
carrier
PWM output deviation
* [ ]im ad k−
* [ ]dy ad k−
* [ ]im kd* [ ]dy kd
-d compTcs
asbs
*im ad −
*dy ad −
*dy cd −
*dy bd −
*im cd −
*im bd −
prohibited area
1.0
0.60.8
0.4
0.00.2 du
ty c
ycle
(d)
*immediate PWM update of [ ]im kd
*delayed PWM update of [ ]dy kd
Fig. 3.23. Non-ideal case that mi(udy* ) is sub-optimal
In the ideal case, all six PWM edges are the result of dim* . However, some of the PWM
edges are not the result of dim* in non-ideal cases. Fig. 3.23 illustrates a non-ideal case that mi(udy* )
is sub-optimal. A PWM output deviation, which is indicated with a light blue box in the figure,
occurs when ddy-a* [k] is above the dmax threshold, and the amount of deviation is determined by
the difference between ddy-a* [k] and dim-a* [k]. The deviation should be small because both ddy* and
dim* are derived using the same control law Gc(z) of (3.2) with the same reference vector i*[k] and
similar feedback vectors, in which ddy* is derived using the estimated current i^[k] and dim* is
derived using the measured current i[k]. Due to the discrepancy between i^ and i, the rising edge
of sa deviates, which is the result of the crossing event between ddy-a* [k] and the carrier.
69
3.5.3 Faulty case of when mi(uim* ) is sub-optimal
*im ad −
*dy ad −
*dy cd −
*dy bd −
*im cd −
*im bd −
prohibited area
*immediate PWM update of [ ]im kd
*delayed PWM update of [ ]dy kd
*duty cycle range of [ ]im kd
carrier
PWM output error
* [ ]im ad k−
* [ ]dy ad k−
* [ ]im kd* [ ]dy kd
-d compTcs
asbs
1.0
0.60.8
0.4
0.00.2 du
ty c
ycle
(d)
carrier* [‹ ›]im ad k−
* [ ]im kd* [ ]dy kd
-d compTcs
asbs
1.0
0.60.8
0.4
0.00.2 du
ty c
ycle
(d)
* [ ]im ad k−
*‹ ›im ad −
PWM output deviation
*‹ ›im bd −*‹ ›im cd −
(a) (b)
Fig. 3.24. Faulty case that mi(uim* ) is sub-optimal
(a) without limiting the dim* (b) with limiting the d im
*
Fig. 3.24 illustrates a faulty case that mi(uim* ) is sub-optimal. In Fig. 3.24(a), all phases of
dim* , dim-b* [k], and dim-c* [k] are below the dmax threshold, but dim-a* [k] violates the threshold and is
inside of the prohibited area. ddy-a* [k] is initially below the dmax threshold, but dim-a* [k] moves
above dmax when the immediate PWM update occurs. dim-a* [k] is not limited, and thus, the
crossing event between the da* and the carrier does not occur during the first half of the Tsamp due
to the discontinuity. Consequently, sa does not flip to a high-state. Although a crossing event
between dim-a* [k] and the carrier during the second half of the Tsamp, it has no effect since sa is
already in a low-state. Therefore, sa stays low during entire period, and a large PWM output error
occurs.
In Fig. 3.24(b), the situation is similar to Fig. 3.24(a). The only difference is that dim-a* [k]
is limited, and ‹dim-a* [k]› is utilized for the modulation instead of dim-a* [k]. This moves ‹dim-a* [k]› to
outside of the prohibited area, which forces a crossing event between ‹dim-a* [k]› and the carrier at
70
the end of the Td-comp. PWM output deviations on sa, which are indicated with light blue boxes,
are caused by the difference between dim-a* [k] and ‹dim-a* [k]›. The deviations occur at both rising
and falling edges of sa, because ‹dim-a* [k]› is maintained for throughout the remainder of the Tsamp.
3.5.4 Non-ideal case of when both mi(udy* ) and mi(uim
* ) are sub-optimal
*im ad −
*dy ad −
*dy cd −
*dy bd −
*im cd −
*im bd −
prohibited area
*immediate PWM update of [ ]im kd
*delayed PWM update of [ ]dy kd
*duty cycle range of [ ]im kd
carrier* [ ]dy ad k−
* [ ]im kd* [ ]dy kd
-d compTcs
asbs
1.0
0.60.8
0.4
0.00.2 du
ty c
ycle
(d)
* [‹ ›]im ad k−* [ ]im ad k−
*‹ ›im ad −*‹ ›im bd −*‹ ›im cd −
PWM output deviation
Fig. 3.25. Non-ideal case that both mi(udy* ) and mi(uim
* ) are sub-optimal
Fig. 3.25 illustrates a non-ideal case that both mi(udy* ) and mi(uim* ) are sub-optimal. Both
ddy-a* [k] and dim-a* [k] are above the dmax threshold. Since dim-a* [k] is inside of the prohibited area, the
limited ‹dim-a* [k]› is used for the modulation. The rising edge of sa is from the crossing event
between ddy-a* [k] and the carrier. The difference between ddy-a* [k] and dim-a* [k] causes a deviation of
sa from the ideal, as indicated with light blue box in the figure during the first half of the Tsamp. In
comparison, the falling edge of sa is from the crossing event between ‹dim-a* [k]› and the carrier,
and thus the difference between dim-a* [k] and ‹dim-a* [k]› causes a deviation of sa from the ideal
during the second half of the Tsamp.
71
3.5.5 Mitigation of PWM deviation during second half of Tsamp
*im ad −
*dy ad −
*dy cd −
*dy bd −
*im cd −
*im bd −
prohibited area
*immediate PWM update of [ ]im kd
*delayed PWM update of [ ]dy kd
*duty cycle range of [ ]im kd
* [ ]dy ad k−
* [ ]im kd* [ ]dy kd
-d compTcs
asbs
1.0
0.60.8
0.4
0.00.2 du
ty c
ycle
(d)
* [‹ ›]im ad k−
* [ ]im ad k−
*‹ ›im ad −*‹ ›im bd −*‹ ›im cd −
PWM output deviation
* [ ]im kd
*delayed PWM update of [ ]im kd
Fig. 3.26. Additional PWM update to remove the PWM deviation during the second half of Tsamp
In both Fig. 3.24 and Fig. 3.25, the falling edge of sa deviates from the ideal due to the
difference between dim-a* [k] and ‹dim-a* [k]›. A simple solution is presented in Fig. 3.26, in which an
additional PWM update is utilized to remove the PWM deviation during the second half the
Tsamp. For the single-sampling method, the delayed PWM update can be executed at both the top
and bottom carrier peak. In the figure, the delayed PWM update of ddy* occupies the top carrier
peak, and the bottom carrier peak remains unoccupied. Therefore, using the original and
unlimited dim* , another delayed PWM update can be executed at this carrier peak to restores da*
from ‹dim-a* [k]› to dim-a* [k]. Fig. 3.26 illustrates this solution with a copy of Fig. 3.25. This does not
require any additional computation, and only a simple register configuration can effectively
remove the deviation. Obviously, this situation only occurs when the single-sampling method is
utilized, and thus, the solution only is applicable to the single-sampling method.
72
3.5.6 Application to double-sampling method
cs
as
bs
-d compT
*[
]im
kd*
[]
dyk
d *[
1]im
k+
d*[
1]dy
k+
d
PWM output deviation*
[2]
imk+
d*[
2]dy
k+
d *[
3]im
k+
d*[
3]dy
k+
d *[
4]dy
k+
d
prohibited areas
Carrier
*im cd −
*im ad −
*‹ ›im ad −*‹ ›im cd −
*im ad −
*dy ad −
*dy cd −
*dy bd −
*im cd −
*im bd −
prohibited area
*immediate PWM update of [ ]im kd
*delayed PWM update of [ ]dy kd
*‹ ›im ad −*‹ ›im bd −*‹ ›im cd −
1.0
0.60.8
0.4
0.00.2 du
ty c
ycle
(d)
Fig. 3.27. Example application of hybrid PWM update with double-sampling method
Similar to the single-sampling method that is shown in previous sections, the hybrid
PWM update method is also applicable to the double-sampling method, as shown in Fig. 3.27.
The beginning of the [k]-th Tsamp starts at the top peak of the carrier. ddy* [k] is updated at the top
peak, and dim* [k] is updated at the end of Td-comp. The beginning of the [k+1]-th Tsamp starts at the
bottom peak of the carrier. Similarly, ddy* [k+1] is updated at the bottom peak, and dim* [k+1] is
updated at the end of Td-comp. The same update procedures repeat for the [k+2]-th Tsamp, [k+3]-th
Tsamp, and so on. Since the sampling points alternate between the top and bottom peak of the
carrier, the prohibited area also alternates at the same time according to the dmax and dmin
thresholds.
The ideal case of Fig. 3.22 is illustrated in the [k]-th period. All three PWM edges are the
result of dim* . In the [k+1]-th period, the non-ideal case of Fig. 3.23 is illustrated, in which ddy-c*
[k+1] is below the dmin threshold. The falling edge of sc is from the crossing event between ddy-c*
73
E A[k+1] and the carrier has no effect since
sc is already in a low-state.
[k+1] and the carrier, and the crossing event between dim-c*
In the [k+2]-th period, the fixed faulty case of Fig. 3.24 is illustrated, in which dAim-a* E A[k+2]
is inside of the prohibited area. Since dAim-a* E A[k+2] is inside of the prohibited area, the limited ‹dAim-a*
E
A[k+2]› is used for the modulation. The crossing event between ‹dAim-a* E A[k+2]› and the carrier causes
the rising edge of sa at the end of the Tcomp. Due to discrepancy between ‹dAim-a* E A[k+2]› and dAim-a*
E
A[k+2], a PWM output deviation occurs.
In the [k+3]-th period, the non-ideal case of Fig. 3.25 is illustrated, in which d Ady-c* E A[k+3]
violates the dmin threshold, and dAim-c* E A[k+3] is inside of the prohibited area. Similar to the [k+2]-th
period, the limited ‹dAim-c* E A[k+3]› is used for modulation. The crossing event between d Ade-c*
E A[k+3] and
the carrier causes the falling edge of sc, and the crossing event between ‹dAim-c* E A[k+3]› and the
carrier has no effect since sc is in a low-state.
74
3.6 Stability and robustness analysis of hybrid PWM update method
3.6.1 Robustness evaluation based on PWM output inspections
The robustness of the hybrid PWM update method is evaluated based on the PWM output
inspections from Fig. 3.22 to Fig. 3.27. For the robustness evaluation, a new term Redge is
introduced as
*number of PWM edges from per
number of PWM edges per im samp
edgesamp
TR
T=
d, (3.30)
which is the ratio of PWM edges in a Tsamp. The denominator is the number of PWM edges per
Tsamp. For example, the total number PWM edges per Tsamp is six when the single-sampling
method is utilized with a three-phase application, as shown in Fig. 3.22. The numerator is the
total number of PWM edges from d Aim* EA per Tsamp. For example, the numerator would be six in the
ideal case of Fig. 3.22, since all PWM edges are from d Aim* EA; therefore, Redge is one (i.e. 1 = 6/6).
Similarly, the numerator would be five in the non-ideal case of Fig. 3.23; therefore, Redge is 5/6.
Using the same logic for the rest of figures, Redge is 4/6 in Fig. 3.24 and Fig. 3.25, and Redge is 5/6
in Fig. 3.26. When the double-sampling method is utilized as shown in Fig. 3.27, the number of
PWM edges per Tsamp is three. In the [k]-th, [k+1]-th, [k+2]-th, and [k+3]-th Tsamp in Fig. 3.27, the
number of PWM edges are from d Aim* EA are three, two, two, and two, respective; therefore, Redge are
3/3, 2/3, 2/3, and 2/3, respectively.
The reference duty cycle d Ahy* EA of the hybrid PWM update method is a combination of the
d Ady* EA and dAim*
EA, and Redge in (3.30) approximately quantifies the ratio of PWM output edges between
dAdy* E A and dAim*
E A. The hybrid PWM update method is more robust when a larger portion of d Ahy* E A is
75
consisted of dAim* EA, since dAim*
E A is more robust than dAdy* EA because dAim*
E A is computed based on measure
current and dAdy* EA is computed based on predicted current.
When Redge equals one, all of PWM edges are from d Aim* EA; therefore, the current loop is
equivalent to the conventional control with the immediate PWM update method, which is
discussed in section 3.1. In non-ideal cases where Redge is less than one, PWM edges are a
combination of dAdy* E A and dAim*
E A; therefore, the robustness is somewhere between the conventional
control with the immediate PWM update method and the predictive control with the delayed
PWM update method. When Redge is 5/6, its robustness is at about 83.3% (i.e. = 5/6) point
between the conventional and predictive control. Similarly, when Redge is 4/6, its robustness is at
about 66.7% (i.e. = 4/6) point. In order to maximize the robustness, the number of PWM edges
from d Aim* EA need to be maximized by keeping the Td-comp as short as possible.
3.6.2 Block diagram of hybrid control
Ei
Discrete Plant Model
( )1
1
11e sampj T
z eR e z e
α
ω α
− −
− −
−
−vu*u
Digital Controller
*i( )
ˆ ˆ1
ˆˆ
1
e sampj Te z eKRe
ω α
α
−−−
1z− Ee
*vhyi
ˆ
ˆe sampj Te
e
α
ω
−
ˆ
ˆ1ˆ e sampj T
eRe
α
ω
−− 1z−
1 edgeR−
edgeRPredictionMeasurement
ˆzii
Fig. 3.28. Hybrid current control loop with a hybrid feedback
Using the concept of Redge, the hybrid PWM update method and the hybrid control can be
modeled. Fig. 3.28 illustrates the block diagram of the hybrid control loop with a hybrid
feedback. The forward gain path is identical to the current control loop with the immediate PWM
update method of Fig. 3.3. The feedback path is a hybrid of two: measurement and prediction.
The measured feedback path is multiplied by Redge.
76
In the prediction path, the Ai^ E
A[k+1] is predicted using the current predictor model as
( ) ( ) ( ) ( )( ) ( )
( ) ( )
*
ˆ ˆ*
ˆ ˆ
ˆ
1ˆe samp e sampj T j T
z z z A z B z
A z B z
e ez ze Re
α α
ω ω
− −
= = +
= +
−= +
i i i v
i v
i v
, (3.31)
which is a slightly modification of (3.18) to account for the lack of Td-one in the forward path.
Although a more advanced prediction algorithm than the simple current prediction algorithm of
(3.31) can be utilized to improve the prediction accuracy, the proposed hybrid deadbeat control is
robust, and the simple prediction algorithm is more than sufficient. The prediction feedback Ai^ E
A[k+1] is delayed by one-step to synchronize with the measurement feedback i[k]. Additionally,
the resulting Ai^ E
A[k] is multiplied by (1–Redge). The summation of the measurement and prediction
path completes the hybrid feedback value, Ai^ E
Ahy.
3.6.3 Modeling of the hybrid control
The open-loop transfer function TI_hy(z) is derived as
( )( ) ( ) ( ) ( ){ }( ) ( ){ }( ) ( )
11_
1
ˆ1
1
1
hyI hy c p edge p edge
c p edge edge
c p
i zT G z G z R z G z B A R
e z
G z G z R z z R
KG z G zz
−−
−
= = − + +
= − +
= =−
, (3.32)
and the closed-loop system transfer functions GI_ hy(z) is derived as
( ) ( ) ( )( ) ( ) ( ){ }_ 111 1
111
1
c pI hy
c p edge p edge
G z G zG z
G z G z R z G z B A R
KKz
K z Kz
−−=
+ − + +
−= =− ++
−
. (3.33)
77
If the estimated parameters are equal to the actual parameters (i.e. ALE
A=L, ARE
A=R and AE^ E
A =E)
and u* is accurately modulated to u by the VSI, then the feedback path becomes a unity gain
regardless the Redge value. TI_hy(z) and GI_ hy(z) become the same as the conventional control with
the immediate PWM update method. The main difference between the conventional control and
the hybrid control is that the full duty cycle range is possible with the hybrid control.
3.6.4 Application example: hybrid deadbeat control
Similar to the application examples of the one-cycle deadbeat control in section 3.1.6 and
the two-cycle deadbeat control in section 3.2.4, a deadbeat control is possible with the hybrid
PWM update. The controller gain K is set equal to 1 in order to directly place the poles at the
origin, and the closed-loop transfer function is reduced to 1/z, which is the same as the one-cycle
deadbeat control. The main difference is that the full duty cycle range is possible with the hybrid
PWM update.
3.6.5 Stability boundary of the hybrid deadbeat control
When the estimated values are not equal to the actual parameters (i.e. ALE
A≠L and ARE
A≠R), the
assumption on the perfect pole-zero cancellation is no longer valid. Thus, the TI_hy(z) in (3.32) is
reevaluated without simplification as
( ) ( ) ( ) ( ){ }
( )
11_
ˆ ˆˆ ˆ ˆ
ˆ ˆˆ
ˆ ˆ
ˆ
1
ˆ 11 1
ˆ 111 1
e samp e samp
e sampe samp e samp
e samp
I hy c p edge p edge
j T j T
edge j Tj T j T
j T
edge
T z G z G z R z G z B A R
K ze e R e ze e eRz z R e ze ee e
K R e ze eRz R e z
ω ωα α α α
ωω ωα α
ωα α
α
−−
− − − −
− −
− −
−
= + + −
− − −= + − − −
− − + − − − e sampj Te eω α−
−
, (3.34)
and the GI_ hy(z) in (3.33) is reevaluated as
78
( ) ( ) ( )( ) ( ) ( ){ }
( )
_ 11
ˆ ˆ
ˆ
_
1 1
ˆ 11 1
1
e samp
e samp
c pI hy
c p edge p edge
j T
j T
I hy
G z G zG z
G z G z R z G z B A R
K R e ze ez R e ze e
T z
ωα α
ωα α
−−
− −
− −
= + + + −
− − − − − =
+
. (3.35)
(a)
2 1000 rad/seω π= ⋅
ˆ 0.1L L= ⋅
ˆ 2.5L L= ⋅
ˆincreasing Lˆ 2.4L L= ⋅
(b)
2 1000 rad/seω π= ⋅
ˆ 0.1L L= ⋅
ˆincreasing L
ˆ 3.0L L= ⋅
ˆ 0.0L L= ⋅ ˆ 0.0L L= ⋅
(c)
2 1000 rad/seω π= ⋅
ˆ 0.1L L= ⋅
ˆ 2.7L L= ⋅
ˆincreasing L
(d)
2 1000 rad/seω π= ⋅
ˆ 0.1L L= ⋅
ˆincreasing L
ˆ 2.4L L= ⋅
ˆ 0.0L L= ⋅ ˆ 0.0L L= ⋅
Fig. 3.29. Eigenvalue migration pattern of GI_hy(z) when the AL^ E
A is varied with ωcc = 2πfsamp/6
(a) Redge = 5/6 (b) Redge = 4/6 (c) Redge = 3/6 (d) Redge = 2/6
79
(e)
2 1000 rad/seω π= ⋅
ˆ 0.1L L= ⋅ˆincreasing L
ˆ 2.2L L= ⋅
ˆ 0.0L L= ⋅
Fig. 3.29. Eigenvalue migration pattern of GI_hy(z) when the L^ is varied with ωcc = 2πfsamp/6
(e) Redge = 1/6
The stability boundary changes based on the value of Redge. If Redge is one, then the
stability boundary is the same as GI(z), as shown in Fig. 3.12. If Redge is zero, then the stability
boundary is the same as GI_pred(z), as shown in Fig. 3.14. The stability boundaries of the hybrid
deadbeat control with varying Redge values between 1 and 0 are evaluated in Fig. 3.29, in which
the eigenvalue migration patterns of GI_hy(z) are illustrated when the L^ is varied with ωcc equals
2πfsamp/6.
Table 3.3. Theoretical stability boundaries of GI_hy(z) with respect to Redge
Redge Lower stability
boundary Upper stability
boundary 6/6 L^ = 0.0∙L L^ = 2.0∙L 5/6 L^ = 0.0∙L L^ ≈ 2.45∙L 4/6 L^ = 0.0∙L L^ ≈ 3.0∙L 3/6 L^ = 0.0∙L L^ ≈ 2.7∙L 2/6 L^ = 0.0∙L L^ ≈ 2.38∙L 1/6 L^ = 0.0∙L L^ ≈ 2.18∙L 0/6 L^ = 0.0∙L L^ = 2.0∙L
Table 3.3 summarizes the theoretical stability boundaries of GI_hy(z) with respect to Redge.
Expected results was that the stability boundary would remain the same as GI(z) and GI_pred(z),
80
because the GI_hy(z) is the combination of the two system. The lower boundary is the same, but
the upper stability boundary is larger than GI(z) and GI_pred(z) when Redge is between zero and
one. The reason for the increased stability boundary is not fully explored, but an initial guess is
that the hybrid feedback path behaves as a filter to provide the extra stability boundary.
81
3.7 Corrective duty cycle manipulation for PWM output deviation
compensation of the hybrid PWM update method
referencepole voltages
*anu
*bnu
*cnu
* *normalization
u d⇒
*ad
*bd
*cd
referenceduty cycle
**sndcorrective
duty cyclemanipulation
correctedreferenceduty cycle
**ad
**bd
**cd
**‹ ›ad
**‹ ›bd
**‹ ›cd
*
* *it
‹lim
›d
d d⇒
limitedduty cycle
1
0
bs
bs
PWM
as
as
cs
cs
Fig. 3.30. Block diagram of the proposed corrective duty cycle manipulation
The ideal case of the hybrid PWM update method can provide the same robustness as a
conventional current loop with the immediate PWM update method, but the practical robustness
of non-ideal cases is less than the robustness of the ideal case due to PWM output deviations, as
discussed in sections 3.3.3 and 3.5. PWM output deviations can be compensated using the
proposed corrective duty cycle manipulation, in which improves the robustness of non-ideal
cases.
A conventional neutral offset voltage injection method is briefly discussed in section 3.5.
The concept is that the neutral offset voltage usn provides a degree of freedom in determining the
duty cycle of the three-phase inverter switches; thus, the degree of freedom from usn is
traditionally utilized to increase the linear mi range compared to the SPWM. The same degree of
freedom can be utilized to compensate and correct the PWM output deviations of the hybrid
PWM update method.
Fig. 3.30 illustrates the block diagram of the proposed corrective duty cycle
manipulation. The manipulation is executed between the normalization and duty cycle limitation
82
in Fig. 3.21. After the pole voltages uan* , ubn
* , and ucn* are normalized to the individual duty cycles
da*, db*, and dc* using (3.29), a corrective duty cycle reference dsn** is computed, and dsn
** is added to
individual duty cycles as
** * **
** * **
** * **
a a sn
b b sn
c c sn
d d dd d dd d d
= +
= +
= +
(3.36)
to create the corrected duty cycle references d a **, d b
** and d c **. Then, these duty cycles are
modulated into PWM outputs.
The process in (3.36) is similar to the neutral offset voltage injection method in (3.28).
The difference is that the neutral offset injection is traditionally computed using the source
voltage vdc as the scale, whereas the proposed corrective method is more convenient when the
duty cycle is used as the scale.
3.7.1 Arbitration of corrective method
The computation of the corrective duty cycle reference dsn** differs based on how many
and which phases of ddy* and dim* violate the dmax threshold of (2.3) or dmin threshold of (2.4). Four
interactions are possible between the thresholds and phase references at any instant: zero, one,
two, or all three references violate the thresholds. It is very unlikely that all three references
violate the dmax or dmin threshold at the same time 9, and thus this case is disregarded, and
remaining three cases are considered.
9 It can happen when the Td-comp is more than half of a Tsw. Or a discontinuous PWM is utilized with double-sampling.
83
Table 3.4. Corrective action according to the number of references that violate dmax or dmin threshold
Number of dim* reference in violation
0 1 2
Number of ddy*
reference in
violation
0 no correction corrective method 1 corrective method 2†
1 corrective method 1 corrective method 1 corrective method 2
2 corrective method 2 † corrective method 2 corrective method 2
† - highly unlikely to happen
In the hybrid PWM update method, PWM outputs are updated twice, and thus, three
interactions between ddy* and the thresholds and another three interactions between dim* and the
thresholds are possible. The combinations of interactions yield a total of nine possible cases (i.e.
32 = 9) as shown in Table 3.4, which lists the proper corrective methods that can be applied to
different cases.
The nine cases can be organized into three sub-categories. The first sub-category is the
ideal case of Fig. 3.22 that zero reference of ddy* and dim* violate the threshold. Since all the PWM
edges are the result of d im* , there is zero PWM output deviation, and it does not need any
corrective action. The second sub-category is the non-ideal cases that only one reference of ddy*
and/or only one reference of dim* violate the threshold. In this sub-category, a corrective method 1
is prescribed. The third sub-category is the non-ideal cases that two references of ddy* and/or two
references of dim* violate the thresholds. In this sub-category, a corrective method 2 is prescribed.
84
3.7.2 Corrective method 1
*im ad −
*dy ad −
*dy cd −
*dy bd −
*im cd −
*im bd −
prohibited area
*immediate PWM update of [ ]im kd
*delayed PWM update of [ ]dy kd
*duty cycle range of [ ]im kd
carrier
PWM output deviation
* [ ]im ad k−* [ ]dy ad k−
* [ ]im kd* [ ]dy kd
-d compTcs
asbs
1.0
0.60.8
0.4
0.00.2
* [ ]im kd* [ ]dy kd
-d compTcs
asbs
1.0
0.60.8
0.4
0.00.2 du
ty c
ycle
(d)
(a) (b)
duty
cyc
le (d
)
* *
differencebetween & dy a im ad d− −
**snd
* **Shift [ ] by im snk dd
Fig. 3.31. First example of the corrective method 1
(a) original non-ideal case shown in Fig. 3.23 (b) corrected dim* references and PWM outputs
The proposed corrective method is a simple idea that the corrective duty cycle reference
dsn** is added to all three phases and compensates PWM output deviations, as given in (3.36). If
only one reference of ddy* and/or only one reference of dim* violates the threshold, then there is
only PWM output deviation, and thus only one reference needs to be compensated. The
compensation is straightforward, and an example is shown in Fig. 3.31, which duplicates the
non-ideal case in Fig. 3.23. In the original case, a PWM output deviation on the sa is caused by
the difference between ddy-a* [k] and dim-a* [k]. First, the difference between ddy-a* [k] and the dim-a* [k]
is computed as
** * *sn dy x im xd d d− −= − , (3.37)
where the subscript ‘x’ indicates the phase that violates the threshold. Since ddy* is updated and is
generating PWM outputs at this point, dsn** cannot correct ddy* . Therefore, dsn
** is added to dim* as
85
** * **- -
** * **- -
** * **- -
im a im a sn
im b im b sn
im c im c sn
d d dd d dd d d
= +
= +
= +
. (3.38)
Fig. 3.31(b) illustrates the shifts of all three phases. As long as all three phases move the same
amount, the average line-to-line voltages that are applied over a Tsamp to a three phase load
remain the same.
*im ad −
*dy ad −
*dy cd −
*dy bd −
*im cd −
*im bd −
prohibited area
*immediate PWM update of [ ]im kd
*delayed PWM update of [ ]dy kd
*duty cycle range of [ ]im kd
carrier
PWM output error
* [ ]im ad k−
* [ ]dy ad k−
* [ ]im kd* [ ]dy kd
-d compTcs
asbs
1.0
0.60.8
0.4
0.00.2 du
ty c
ycle
(d)
* [ ]im kd* [ ]dy kd
-d compTcs
asbs
1.0
0.60.8
0.4
0.00.2 duty
cyc
le (d
)
*‹ ›im ad −*‹ ›im bd −*‹ ›im cd −
(a) (b)
**snd
Fig. 3.32. Second example of the corrective method 1
(a) original non-ideal case shown in Fig. 3.24 (b) corrected dim* references and PWM outputs
86
*im ad −
*dy ad −
*dy cd −
*dy bd −
*im cd −
*im bd −
prohibited area
*immediate PWM update of [ ]im kd
*delayed PWM update of [ ]dy kd
*duty cycle range of [ ]im kd
carrier
PWM output deviation
* [ ]im ad k−* [ ]dy ad k−
* [ ]im kd* [ ]dy kd
-d compTcs
asbs
1.0
0.60.8
0.4
0.00.2
* [ ]im kd* [ ]dy kd
-d compTcs
asbs
1.0
0.60.8
0.4
0.00.2 du
ty c
ycle
(d)
(a) (b)
duty
cyc
le (d
)
* [‹ ›]im ad k−
PWM output deviation
* **Shift [ ] by im snk dd
**snu
Fig. 3.33. Third example of the corrective method 1
(a) original non-ideal case shown in Fig. 3.25 (b) corrected dim* references and PWM outputs
Fig. 3.32 and Fig. 3.33 illustrate the second and third examples of the corrective method
1. Fig. 3.32 and Fig. 3.33 are duplicates of the non-ideal cases in Fig. 3.24 and Fig. 3.25,
respectively. Using the same principle, dim* references are shifted and corrected. In Fig. 3.32(a),
the PWM output of sa stays at the low-state, as described in Fig. 3.24. A simple shifting of dim*
using dsn** restores the sa PWM output as shown in Fig. 3.32(b). Additionally, both the rising and
falling edges are corrected. In Fig. 3.33(a), the rising edge of sa has a small PWM output
deviation. A simple shifting of dim* using dsn** removes the rising edge deviation of the sa PWM
output as shown in Fig. 3.33(b), but the limited ‹dim-a* [k]› is utilized for the modulation instead of
the dim-a* [k] to avoid any possible PWM output error. It causes a worse PWM output deviation
during the falling edge of sa. It can be easily corrected using an extra PWM update at the bottom
of the carrier, which is described in section 3.5.5.
87
The corrective method 1 can correct any PWM output deviations when there is only one
reference violates the thresholds, and thus, the average voltages from the perspective of the loads
become the same as the dim* .
3.7.3 Corrective method 2
If two references of ddy* and/or two references of dim* violate the threshold, then there are
two PWM output deviations, and thus two references need to be corrected. However, dsn** can
provide only one degree of freedom, and thus both references cannot be corrected at the same
time. Thus, the reference with a greater discrepancy between udy-x* [k] and uim-x* [k] is prioritized
and corrected using the same principle as the corrective method 1. Good news is that when one
reference is corrected, the other reference also moves in a direction to minimize the overall
PWM output deviation.
88
as
-d compTcsbs
**snd
PWM output deviation less PWM output deviation
* [ ]im kd
* [ ]dy kd
ZOH sample
* *(a) &dy imd d * *(b) [ ]& [ ] without correction
dy imk kd d * *(c) [ ]& [ ] with correction
dy imk kd ddu
ty c
ycle
()d
as
-d compTcsbs
PWM output deviations less PWM output deviation
* *(d) [ ]& [ ] after limitation
dy imk kd d * *(e) [ ]& [ ] with addtional PWM update
dy imk kd d
1.0
0.6
0.8
0.4
0.0
0.2 duty
cyc
le (
)d
* [‹ ›]im ad k−
*im ad −
*dy ad −
*dy cd −
*dy bd −
*im cd −
*im bd −
prohibited area
*immediate PWM updateof [ ]im kd
*delayed PWM update of [ ]dy kd
*delayed PWM updateof [ ]im kd
1.0
0.6
0.8
0.4
0.0
0.2
1.0
0.6
0.8
0.4
0.0
0.2
Fig. 3.34. First example of corrective method 2
(a) ddy* and dim
* for a half period (b) ddy* and dim
* for one Tsw without correction (c) ddy* and dim
* with correction
(d) ddy* and dim
* after limitation (e) ddy* and dim
* with additional PWM update
Fig. 3.34 illustrates the first example of the corrective method 2 that two ddy* references
(ddy-a* [k] and ddy-c* [k]) violate the threshold and two dim* references (dim-a* [k] and dim-c* [k]) are in the
prohibited area. Fig. 3.34(a) shows the individual phases of ddy* in solid lines (i.e. ddy-a* , ddy-b* , and
ddy-c* ) and the individual phases of dim* in dashed lines (i.e. dim-a* , dim-b* and dim-c* ) for a half electrical
89
period. The individual duty cycle values of ddy* and dim* at the vertical line in Fig. 3.34(a) are
sampled using a ZOH, and the sampled values are used for the delayed and immediate PWM
update values in Fig. 3.34(b).
Fig. 3.34(b) illustrates ddy* and dim* for one Tsamp along with the carrier. Both da* and dc
*
violate the dmax threshold, but dsn** can provide only one degree of freedom, and thus both cannot
be corrected at the same time. Between da* and dc
*, da* is selected as the phase for correction since
the difference between ddy-a* [k] and dim-a* [k] is larger than the difference between ddy-c* [k] and dim-c*
[k]. The all three phases are shifted as given in (3.38), which is shown in Fig. 3.34(c). However,
the dim-a* [k] and dim-c* [k] in Fig. 3.34(c) are inside the prohibited area, and both must be limited as
shown in Fig. 3.34(d). It leads to a relatively large PWM output deviation at the second half of
the carrier period. This problem is easily corrected using the additional PWM update method at
the bottom of the carrier peak, which is implemented as discussed in section 3.5.5 and is shown
in Fig. 3.34(e).
90
as
-d compTcsbs
**snd
PWM output deviation less PWM output deviation
* [ ]im kd
* [ ]dy kd
ZOH sample
* *(a) &dy imd d * *(b) [ ]& [ ] without correction
dy imk kd d * *(c) [ ]& [ ] with correction
dy imk kd ddu
ty c
ycle
()d
as
-d compTcsbs
PWM output deviations less PWM output deviation
* *(d) [ ]& [ ] after limitation
dy imk kd d * *(e) [ ]& [ ] with addtional PWM update
dy imk kd d
1.0
0.6
0.8
0.4
0.0
0.2 duty
cyc
le (
)d
*im ad −
*dy ad −
*dy cd −
*dy bd −
*im cd −
*im bd −
prohibited area
*immediate PWM updateof [ ]im kd
*delayed PWM update of [ ]dy kd
* [‹ ›]im ad k−
*delayed PWM updateof [ ]im kd
1.0
0.6
0.8
0.4
0.0
0.2
1.0
0.6
0.8
0.4
0.0
0.2
Fig. 3.35. Second example of corrective method 2
(a) ddy* and dim
* for a half period (b) ddy* and dim
* for one Tsw without correction (c) ddy* and dim
* with correction
(d) ddy* and dim
* after limitation (e) ddy* and dim
* with additional PWM update
Fig. 3.35 illustrates the second example of the corrective method 2 that two ddy* references
(ddy-a* [k] and ddy-c* [k]) violates the threshold and only one d im* references (dim-a* [k]) is in the
prohibited area. Similar to the previous case, da* is selected for d sn
** correction because its
difference is bigger than dc*. A similar procedure as shown in Fig. 3.34 is followed.
91
as
-d compTcsbs
**snd
PWM output deviation & error
* [ ]im ku
* [ ]dy ku
ZOH sample
* *(a) &dy imd d * *(b) [ ]& [ ] without correction
dy imk kd d * *(c) [ ]& [ ] with correction
dy imk kd ddu
ty c
ycle
()d
as
-d compTcsbs
PWM output deviations
* *(d) [ ]& [ ] after limitation
dy imk kd d * *(e) [ ]& [ ] with addtional PWM update
dy imk kd d
1.0
0.6
0.8
0.4
0.0
0.2 duty
cyc
le (
)d
*im ad −
*dy ad −
*dy cd −
*dy bd −
*im cd −
*im bd −
prohibited area
*immediate PWM updateof [ ]im kd
*delayed PWM update of [ ]dy kd
* [‹ ›]im ad k−
*delayed PWM updateof [ ]im kd
"negative" PWM output required
less "negative" PWM output required
1.0
0.6
0.8
0.4
0.0
0.2
1.0
0.6
0.8
0.4
0.0
0.2
Fig. 3.36. Third example of corrective method 2
(a) ddy* and dim
* for a half period (b) ddy* and dim
* for one Tsw without correction (c) ddy* and dim
* with correction
(d) ddy* and dim
* after limitation (e) ddy* and dim
* with additional PWM update
Fig. 3.36 illustrates the third example of the corrective method 2 that one ddy* reference
(ddy-a* [k]) violates the threshold and two dim* references (dim-a* [k] and dim-c* [k]) are inside of the
prohibited area. Similar to the previous cases, da* is selected for d sn
** correction because its
difference is bigger than dc*. The correction requires that all three phases need to be shifted down,
92
but db* is already at the minimum point, and it cannot be shifted down as shown in Fig. 3.36(b). db
*
required a “negative” duty cycle output, but a negative duty cycle cannot be produced as shown
in Fig. 3.36(c). Therefore, this shifting can be viewed as removing the sa and sc PWM output
deviations and adding to the sb PWM output deviation. After the duty cycle limitation as shown
in Fig. 3.36(d) and with additional PWM update at the bottom of the carrier peak as shown in
Fig. 3.36(e), the “negative” duty cycle in sb is reduced, all the while the PWM outputs in sa and
sc are corrected. When the proposed corrective method 2 is utilized, the total deviation amount is
reduced, as shown in Fig. 3.34 and Fig. 3.35. However, there are cases that the reduction of the
total deviation may not be significant, as shown in Fig. 3.36. In such cases, the total deviation
may not change, and the total deviation never increases.
The case that goes from zero ddy* reference in violation to two dim* references in violation
and the case that goes from two ddy* reference in violation to zero dim* references in violation are
highly unlikely to happen as indicated in Table 3.4. Only a very large change between ddy* and dim*
within the same Tsamp can cause such cases. ddy* and dim* are computed using the same controller
Gc(z) in (3.2) based on the same current reference i*[k] and slightly different feedbacks i^[k] and
i[k], respectively. Therefore, a very large change between ddy* and dim* within the same Tsamp is
highly unlikely to happen.
The proposed neutral offset voltage correction for the hybrid PWM update method can be
applied to most three-phase applications. As shown in section 3.5.6, the corrective method can be
applied to double-sampling as well. Additionally, these corrective methods are also effective
during a over-modulation.
93
3.7.4 Advantages and disadvantages
The advantage of the proposed offset voltage manipulation is that the PWM deviations
are significantly reduced. However, the disadvantage is that extra computations cause a longer
Td-comp. The necessary operations for the corrective method are quite small, which are a few “if-
then” statements for arbitration and a few operations for computing and adding dsn** to da*, db*, and
d c* . Therefore, small extra computation overheads can be accommodated, and the potential
robustness improvement is significant. With the hybrid PWM update and corrective duty cycle
manipulation, the hybrid PWM update can emulate the performance of the immediate PWM
update with very little PWM output deviation. Moreover, the hybrid PWM update method is
capable of the full duty cycle range.
94
Chapter 4
Applications of the Hybrid PWM Update Method
4.1 Test setup
The validity of the proposed hybrid PWM update method and hybrid control are
demonstrated with experimental results. Two different applications of the proposed methods are
performed: deadbeat current control and high speed control of three-phase ac drive.
Two identical PMSMs are coupled together in a motor-generator configuration, where the
loading PMSM system is speed controlled while the testing PMSM system is current/torque
controlled. The experimental setup is shown in Fig. 4.1, and the experiment specification is given
in Table 4.1. After the control algorithms are implemented on a digital signal processor platform,
the execution time of the Td-comp is measured to be around 4 µs. However, the Td-comp may vary,
the calculation of the dmax and dmin thresholds assumes that the Td-comp equals 5 µs to make sure
any potential PWM output errors do not occur.
95
Fig. 4.1. Experimental Test Setup
Table 4.1. Specification of the experimental test setup
Mac
hine
Model BK90-S024300 Machine Type Surface PMSM Rated Voltage 24 V Rated Output 300 W
Rated rms Current 17.8 A Rated Speed 3,000 rpm
Number of Poles 12 poles Inductance (approximate value) 100~110 µH Resistance (Motor and Driver) 0.2~0.4 Ω
Back-emf (line-to-line rms voltage at
1,000 rpm) 4.76 V
Driv
er Power Module (IGBT) FNB41560
Switching Frequency 10 kHz Driver Supply Voltage 24 V & 30 V
Deadtime 1.5 µs
Con
trol
DSP TMS320F28377D Sampling method Double-sampling
Sampling Frequency 20 kHz Measured Computation Time ≈ 4 µs
Implemented Computation Time (Td-comp)
5 µs
Maximum mi for immediate update 0.92
96
4.2 Deadbeat control of three-phase ac drives
4.2.1 Literature review on deadbeat controls
A deadbeat current control, which is a part of a very wide class of predictive controls [2],
has been applied to many applications, including variable-speed electric drives (permanent
magnet [3, 25, 36, 37, 40, 41, 45] and induction [46, 47]), uninterruptible power supplies [48,
49], power factor correctors [50], dc-dc converters [51], active filters/rectifiers [52-55], three-
phase inverters [4, 28, 39, 56], etc. These conventional deadbeat current control implementations
have two disadvantages that arise from the existence of the one-step control delay Td-one.
The first disadvantage of the Td-one is an increased response time. The main reason for
employing the deadbeat control is its good dynamic properties, in which the targeted state
variables are brought to the desired reference points in the smallest number of time steps. For
example, the deadbeat current control of inductive loads ideally requires only one time step to
bring the current to the desired reference current point since the inductive loads are a first order
system. However, the Td-one adds a Tsamp delay to the overall responses in the practical
implementation of a conventional deadbeat control, and thus the ideal response time becomes
two sampling periods [4, 25, 36, 37].
The second disadvantage of the Td-one is an increased susceptibility to disturbances, such
as parameter uncertainties, model mismatches and non-linear behaviors of an inverter. The
deadbeat control is inherently susceptible to disturbances two reasons: high controller gain and
model-based feedback prediction. In past literature, algorithms are proposed to improve the
stability, robustness and/or response quality of steady-state and transient responses under
different disturbances. Adaptive methods are utilized for the parameter uncertainties [4, 57, 58],
97
and disturbance feedforward compensation methods are utilized for the model mismatch and
inverter non-linear characteristics [37, 40, 41]. These adaptive and disturbance feedforward
methods are typically employed to keep a system stable despite large initial parameter
mismatches, and as well as to improve system performances. In some applications, disturbance
observers are employed to simply assist the transient responses of a deadbeat controller without
concerning system stabilities [49, 50]. Deadbeat controls with some filtering elements can be
utilized to improve stability [39, 48, 49, 54, 56].
These variations of a deadbeat control with the one-step control delay Td-one generally rely
on combinations of different compensation algorithms to improve the stability and robustness
against the disturbances; however, the algorithms can become very complex and difficult to
understand. Without these algorithms, a deadbeat control is not robust, and thus performances
can degrade, and a system can easily become unstable from disturbances.
The responses and robustness of a deadbeat control can be improved if the Td-one is
eliminated. One possible method to eliminate the Td-one is to utilize the immediate PWM update
method. Without the Td-one, the response time to the inductive load is reduced from two Tsamp to
one Tsamp, and the robustness is significantly increased by reducing the uncertainty of the model-
based feedback prediction. The deadbeat control with the immediate PWM update is referred as
the one-cycle deadbeat control, since the ideal response time is only one Tsamp. However, a
disadvantage is that the inherent property of the immediate PWM update method causes some
loss of PWM duty cycle range due to the delay from current sampling through algorithm
computation to the PWM update instant [14-16]. Although the immediate PWM update method
has been utilized in some motor drive applications [26, 27], either a powerful processor is
required to keep the computation time reasonably low or an excessive algorithm computation
98
time had made the immediate PWM update nearly impractical to utilize it in the past due to a
significantly reduced duty cycle range.
The proposed novel hybrid PWM update method and hybrid control are utilized to
eliminate the Td-one while maintaining the full duty cycle range.
4.2.2 Experimental results
di
qi
ai
qi
5.0ms/div
ˆ(c) 0.8L L≈ ⋅ˆ(b) 0.1L L≈ ⋅ˆ(a) 0.0L L≈ ⋅ ˆ(d) 0.9L L≈ ⋅
0A
10A
10A−
ˆ (5A/div): -axis current predictio(5A /div) : -axis current fe
(5A/div): -
edback (
axis current
5A/div)
feedbac
: -axis current feedback
kn
d
q
a
q
i a
i qd
i
i
q
Fig. 4.2. Stability boundary of the two-cycle deadbeat control
The experimental results aim to show three points: improved robustness against
disturbances, better response characteristics and the full mi utilization. The improved robustness
is illustrated by comparing the stability range of two-cycle deadbeat control, one-cycle deadbeat
control, and hybrid deadbeat control. Fig. 4.2 shows the stability boundary of the two-cycle
deadbeat control. The q-axis and d-axis current references are held at 10A and 0A, respectively,
vdc is 24 V, ωe is 2π∙100 rad/s, and the double-sampling method is utilized. Constant R^ and L^
values are utilized. No compensation methods, such as deadtime and device on-state voltage
drop compensation, are applied to emphasize the difference of robustness between different
deadbeat controls. For the stability boundary test, different L^ values are applied for one electrical
99
cycle, and its steady-state responses are observed. In the figure, when L^ = 0.0∙L, which is
indicated by (a), the current loop is unstable, which can be observed from a growing oscillation
of iq. When L^ ≈ 0.1∙L, which is indicated by (b), the current loop stability is restored, which can
be observed as the iq oscillation goes away. Although the loop is stable, the iq and id current
waveforms are offset and distorted, which are caused by a large difference between L^ and L. The
estimated q-axis current i^q is used as the feedback for the two-cycle deadbeat control, and i^q is
well regulated to the desired 10 A. However, the measured q-axis current iq is around 8.5 A due
to the estimation offset error between i^q and iq. Additionally, a very low L^ effectively reduces the
current loop bandwidth, and the 6th harmonics due to zero-crossing errors are not suppressed,
which can be observed in iq, id and ia. When L^ ≈ 0.8∙L, which is indicated by (c), the current loop
is near the upper stability boundary. When L^ ≈ 0.9∙L, which is indicated by (d), the current loop
become unstable.
100
ˆ(b) 0.0L L≈ ⋅ ˆ(d) 0.01L L≈ − ⋅ˆ(a) 1.9L L≈ ⋅ ˆ(c) 1.8L L≈ ⋅
qiai
*im ad −
5.0ms/div
*de ad −
0A10A
10A−
0.5
1.0
0.0
prohibited areas
*
* (0.125unit/ div) :
(5A/div): -axis
-axis delayed (5A/div):
duty cycle-axis current feedbac
(0.125unit/div) : -axis immedia
current fee
te
dbac
duty cycle
kk
a
im a
de a
q
dd ai q
a
i a
−
−
Fig. 4.3. Stability boundary of the hybrid deadbeat control when Redge = 3/3
ˆ(b) 0.0L L≈ ⋅ ˆ(d) 0.01L L≈ − ⋅ˆ(a) 1.7L L≈ ⋅ ˆ(c) 1.5L L≈ ⋅
5.0ms/div
0A10A
10A−
0.5
1.0
0.0
prohibited areasqiai
*im ad −
*de ad −
*
* (0.125unit/ div) :
(5A/div): -axis
-axis delayed (5A/div):
duty cycle-axis current feedbac
(0.125unit/div) : -axis immedia
current fee
te
dbac
duty cycle
kk
a
im a
de a
q
dd ai q
a
i a
−
−
Fig. 4.4. Stability boundary of the hybrid deadbeat control when Redge = 2/3
Under the same conditions, the stability boundaries of the hybrid deadbeat control are
examined. In Fig. 4.3, the stability boundary of the hybrid deadbeat control is examined when
Redge equals 3/3, which is equivalent to the one-cycle deadbeat control. Both the delayed duty
cycle of phase-a dde-a* and the immediate duty cycle of phase-a dim-a* do not violate the dmax and
dmin thresholds, and all the PWM edges are the result of dim* . When L^ = 1.9∙L and L^ = –0.01∙L,
which are indicated by (a) and (d), respectively, the current loop is unstable, which can be
101
observed from the oscillating iq. When L^ = 0.0∙L and L^ = 1.8∙L, which are indicated by (b) and
(c), respectively, the stability is restored.
In Fig. 4.4, the stability boundaries of the hybrid deadbeat control are examined when the
Redge is equal to 2/3. The vdc is reduced from 24 V to 18 V. Due to the lower vdc, the dde-a* and dim-a*
violate the dmax and dmin thresholds, which are between 1.0 and 0.9 and between 0.1 and 0.0,
respectively. When the L^ = 1.7∙L and L^ = –0.01∙L, which are indicated with (a) and (d),
respectively, the current loop is unstable. When the L^ = 0.0∙L and L^ = 1.5∙L, which are indicated
with (b) and (c), respectively, the current loop is stable.
In Fig. 4.2 and Fig. 4.3, the stability ranges of the two-cycle and one-cycle deadbeat
control are measured to be about 0.1∙L ≤ L^ ≤ 0.8∙L and to be about 0.0∙L ≤ L^ ≤ 1.8∙L,
respectively. The theoretical stability ranges of both the one-cycle and two-cycle deadbeat
controls are 0.0∙L < L^ < 2.0∙L; however, the practical stability ranges are less than the theoretical
due to disturbances. The practical stability range of the two-cycle deadbeat control is much less
than the practical stability range of the one-cycle deadbeat control, and it is largely attributed to
the difference of the feedback signals, in which the one-cycle deadbeat utilizes the measured
current i, whereas the two-cycle deadbeat control utilizes the predicted current i^ . Other
disturbances are assumed to be the same between two since the same platform is being utilized.
The difference can be reduced if the accuracy of i^ is improved.
In Fig. 4.4, the stability range of the hybrid control is measured when Redge equals 2/3.
The range is measured to be about 0.0∙L ≤ L^ ≤ 1.5∙L. The measured upper boundary of 1.5∙L is
about at 70% point between the 1.8∙L and 0.8∙L, which agrees the PWM edge counting method
that the stability should be at about 66% point when Redge = 2/3. It shows that the hybrid
102
deadbeat control’s robustness is much improved compared to the two-cycle deadbeat control
without any conventional compensation methods.
qiai di0A
10A
10A−
0.5
1.0
0.02.0ms/div
2A2A−
_(c) (z), =2 / 7I pred cc sampG fω π
*
*(0.12
(5A/
5unit
div): -ax
/ div)
: -axis delayed duty cycle(0.125unit/ div) : -axis immediate
(2A/ div)
dut
(5A/div)is curre
: -axis curren: -axis curren
y cycl
ntt
t
ede a
im a
d
q
a
d a
i
d a
iqa
i d−
−
2.0ms/div
_(b) (z), =2 / 6I pred cc sampG fω π
qiai di
*dy ad −
0A10A
10A−
0.5
1.0
0.02.0ms/div
2A2A−
_(a) (z), =2 /18I one cc sampG fω π
_(d) (z), =2 / 6I hy cc sampG fω π
qiai di
*im ad −
0A10A
10A−
0.5
1.0
0.02.0ms/div
2A2A−
*dy ad −
Fig. 4.5. Steady-state responses
(a) conventional control with delayed PWM update method
(b) & (c) predictive control with delayed PWM update method
(d) hybrid control with hybrid PWM update method when Redge = 3/3
103
Fig. 4.5 illustrates the steady-state responses of different control methods. Fig. 4.5(a) is
the conventional control loop with the delayed PWM update method. The open-loop crossover
frequency ωcc is set equals to 2πfsamp/18. With fsamp equals 20 kHz, it yields fcc (i.e. ωcc = 2πfcc)
equals 1.11 kHz. Additionally, the closed-loop bandwidth using the –90º qualification is 1.62
kHz. Since the deadtime compensation is not implemented and due to a relatively low
bandwidth, the sixth harmonics from zero crossing errors are very noticeable. Fig. 4.5(b) and (c)
are the predictive control with the delayed PWM update method. In Fig. 4.5(b), ωcc is set equals
to 2πfsamp/6 (i.e. fcc = 3.33 kHz). Additionally, the closed-loop bandwidth using the –90º
qualification is 2.5 kHz. The current loop is unstable due to the lack of compensations and high
bandwidth. In Fig. 4.5(c), ωcc is reduced and set equals to 2πfsamp/7 (i.e. fcc = 2.86 kHz), and the
current loop stabilizes. Although the phase-a current waveform is stable and sinusoidal, the
current loop is near the instability. Fig. 4.5(d) is the hybrid control with the hybrid PWM update
method when Redge equals 3/3. ωcc is set equals to 2πfsamp/6 (i.e. fcc = 3.33 kHz), and the closed-
loop bandwidth using the –90º qualification is 5 kHz. Due to the lack of the Td-one, a very high
bandwidth is easily achieved without incurring instability. Additionally, a very high bandwidth
suppresses the sixth harmonics without any compensations.
104
0A10A
10A−
0.5
1.0
0.02.0ms/div
*
*(0.125unit/ div): delayed PWM u
(5pda
A/div)te dut
: a-axis curry
(5A/div):
(0.125unit/ div) : immediate PWM update d
qe
-axis curren
t
t
tn
u yde a
dy
q
a
a
id
i
d−
−
qiai
*dy ad −
*im ad −
(b) : 2 / 3, 16Vedge dcR v =
qiai
0A10A
10A−
0.5
1.0
0.02.0ms/div
*dy ad −
*im ad −
(a) : 3 / 3, 24Vedge dcR v =
prohibited areas
Fig. 4.6. Detailed steady-state responses of the hybrid PWM update method
(a) Redge = 3/3 (b) Redge = 2/3
The hybrid PWM update method utilizes ddy* and dim* for the delayed and immediate PWM
updates, respectively. Fig. 4.6 illustrates the detailed steady-state responses of the hybrid PWM
update method. The phase-a duty cycles of ddy* and dim* (i.e. ddy-a* and dim-a* ) are shown in the
figure. Fig. 4.6(a) illustrates the case when Redge = 3/3. Both ddy* and dim* are outside of the
prohibited area. Fig. 4.6(b) illustrates the case when Redge = 2/3, in which vdc is reduced from
24V to 16V to increase the modulation index. Although ddy* and dim* enter the prohibited area, a
stable and clean current waveform is exhibited.
105
*
*(0.125unit/ div): delayed PWM u
(5pda
A/div)te dut
: a-axis curry
(5A/div):
(0.125unit/ div) : immediate PWM update d
qe
-axis curren
t
t
tn
u yde a
dy
q
a
a
id
i
d−
−
0A10A
10A−
0.5
1.0
0.02.0ms/div
ai
*dy ad −
*im ad −
: 2 / 3, 16Vedge dcR v =
qi
prohibited areas
Fig. 4.7. Hybrid PWM update method during over modulation
Fig. 4.7 illustrates the hybrid PWM update method during over modulation. Although the
modulation index is well into the non-linear region, the hybrid PWM update operates well, and
the phase-a current waveform is near sinusoidal. Some distortion is not avoidable in over
modulation region.
-
-
-
conventional : 2 / 6without predictive with : 2 / 6conventional with : 2 /18
cc sampd one
d one cc samp
d one cc samp
fTT f
T f
ω πω πω π
===
Fig. 4.8. Simulated step responses
(a) conventional control with delayed PWM update method (b) predictive control with delayed PWM update method
(c) conventional method with immediate PWM update method
Fig. 4.8 shows the simulated step responses. With the immediate PWM update method,
the step response reacts after one Tsamp delay (i.e. 50 µs) due to the elimination of the Td-one. In
comparison, with the delayed PWM update method, the step response reacts after two Tsamp delay
due to the existence of the Td-one. The one-cycle and two-cycle deadbeat controls track the
106
reference after only one and two cycles, respectively. In contrast, the step response of the
conventional control with the delayed PWM update method reacts after two Tsamp delays due to
the existence of the Td-update, and it takes about 10 Tsamp to reach the steady-state.
12 sampT
(c)
*
(5A/div): -axis cur (5A/div
(5A/ div) : -axis current re
): -axis cur(2A/ div): -axis
ren
current
f
re
e
t
et
n
renc
d
q
q
a
i q
dii ai q
(b)
qi
ai
di
*qi
0A
10A
10A−
2.0ms/div
2A
2A−
(a)
ai
di*qi
0A
10A
10A−
100 s/divµ
2A
2A−
qi
ai
di
*qi
0A
10A
10A−
100 s/divµ
2A
2A−
qi
4 sampT
Fig. 4.9. Small-signal transient responses of conventional control with delayed PWM update
(a) zoomed-out (b) &(c) zoomed-in
Fig. 4.9 illustrates the small-signal transient responses of the conventional control with
the delayed PWM update method. A transient is considered small when a current reference is
small enough that the modulation index mi does not saturate. The open-loop crossover frequency
ωcc equals 2πfsamp/18. Fig. 4.9(a) is a zoomed-out figure, and the q-axis reference current i EE
A is
changed from +10 A to 0 A to –10 A while the PMSM is operating at 1000 rpm (i.e. 100 Hz
electrical frequency), and the d-axis current reference iAAd*
EE
A is held at zero. vdc is set at 30 V.
q*
Fig.
107
4.9(b) and Fig. 4.9(c) are the zoomed-in figures of the first and second transients, respectively.
The first and second transients take about 4 and 12 steps of Tsamp. The 4 steps is much faster than
the simulation in Fig. 4.8, and the cause is assumed to be the much larger damping of the
equivalent series resistance (ESR) due to device voltage drops near zero current. The 12 steps of
the second transient is more representative of the simulation.
(c)
*
(5A/div): -axis cur (5A/div
(5A/ div) : -axis current re
): -axis cur(2A/ div): -axis
ren
current
f
re
e
t
et
n
renc
d
q
q
a
i q
dii ai q
(b)
qi
ai
di
*qi
0A
10A
10A−
2.0ms/div
2A
2A−
(a)
ai
di*qi
0A
10A
10A−
200 s/divµ
2A
2A−
qi
ai
di
*qi
0A
10A
10A−
200 s/divµ
2A
2A−
qi
Fig. 4.10. Small-signal transient responses of predictive control with delayed PWM update under small reference
change
(a) zoomed-out (b) &(c) zoomed-in
Fig. 4.10 illustrates the small-signal transient responses of the predictive control with the
delayed PWM update method. ωcc is set equals 2πfsamp/7 to avoid the instability, and other
108
settings are identical to the setting of Fig. 4.9. The transient is expected to about 2 steps of Tsamp
as the simulation in Fig. 4.8; however, oscillations occur after transients because the current loop
is near the instability boundary, as shown in Fig. 4.5(c). The oscillation amplitudes of the first
transient diminishes much faster than that of the second transient because of larger ESR damping
near zero current.
1.0 sampT
(c)
*
(5A/div): -axis cur (5A/div
(5A/ div) : -axis current re
): -axis cur(2A/ div): -axis
ren
current
f
re
e
t
et
n
renc
d
q
q
a
i q
dii ai q
(b)
qi
ai
di
*qi
0A
10A
10A−
2.0ms/div
2A
2A−
(a)
ai
di*qi
0A
10A
10A−
100 s/divµ
2A
2A−
qi
ai
di
*qi
0A
10A
10A−
100 s/divµ
2A
2A−
qi
1.0 sampT
Fig. 4.11. Small-signal transient responses of hybrid control with hybrid PWM update under small reference change
(a) zoomed-out (b) &(c) zoomed-in
Fig. 4.11 illustrates the small-signal transient responses of the hybrid control with the
hybrid PWM update method. ωcc equals 2πfsamp/6, and other settings are identical to the setting of
Fig. 4.9. In spite of a very high ωcc, the current loop stays very stable, and both transients take
109
only 1 step of Tsamp to settle at reference values. The responses are equivalent to the conventional
control with the immediate PWM update method.
In Fig. 4.9 and Fig. 4.11, despite a rapid iq current change, the id current is well decoupled
and regulated to zero. It illustrates a strong cross-coupling rejection capability between q-axis
and d-axis currents. In Fig. 4.10, the oscillation of d-axis current is due to instability, and thus it
does not need to be considered.
2ms/div
0A
6A
6A−
0.0
1.0
prohibited areas
100 s/divµ
100 s/divµ
=1.15im
=0.92im
(a)
*
(2A/div): -axis current fe (2A/div):
(2A/ div): -axis current referen
-axis curren(0.25u
ce
ni
e
t
db
/ d
ac
ivt
) : modulatio i
k
n ndexi
q
a
q
i am
ii q
q
ai
qi
im
*qi
0A
6A
6A−
0.0
1.0
(a)
ai
qi
im
*qi
0A
6A
6A−
0.0
1.0
(a)
ai
qi
im
*qi
prohibited areas
prohibited areas
Fig. 4.12. Detailed small-signal transient responses of the hybrid deadbeat control
(a) zoomed-out (b) zoomed-in: transient outside prohibited area (c) zoomed-in: transient inside prohibited area
110
Fig. 4.12 illustrates the detailed small-signal transient responses of the hybrid deadbeat
control. Fig. 4.12(a) is a zoomed-out figure, and the q-axis reference current i EE
A is changed from
+5A to 0A back to +5A, and other settings are identical to the setting of
q*
Fig. 4.11. It should be
noted that the SVPWM is utilized; thus, the maximum mi is about 1.15, and the prohibited areas
for the mi is between 0.92 and 1.15, which is marked with hashes in the figure. Fig. 4.11(b) and
Fig. 4.11(c) are the zoomed-in figures of the first and second transients, in which iq follows i Aq*
E
A
after one Tsamp without and with entering the prohibited area, respectively. A conventional
control with the immediate PWM update method is capable of the first transient since mi stays
below 0.92. However, the conventional control is not capable of the second transient since mi is
over 0.92. The conventional control requires two Tsamp steps to complete the second transient due
to limited mi. However, the hybrid control utilizes the full modulation index to complete the
transient with only one Tsamp step. It demonstrates that the hybrid PWM update method can
utilize the full duty cycle and mi to reach the desired reference point faster. This point is further
illustrated in the next experiment.
111
100 s/divµ
0A
10A
10A−
(5A/div): -axis feedback (5A/div)
(5A/ div): -axis predicted curren
: -axis current(0.5unit / div) : modulation inde
cur
x
tˆrent
a
q
q
i
i qi a
qi
m
11 sampT
2 sampT
7 sampT
9.5A
11A
3.4A
4.4A
2 sampT
0.0
1.0
(a)
ai qi
im
qi
prohibited areas
0A
10A
10A−
0.0
1.0
(b) ai
qi
im
prohibited areas
0A
10A
10A−
0.0
1.0
(c)
ai
qi
im
prohibited areas
0A
10A
10A−
0.0
1.0
(d)
aiqi
im
prohibited areas
0A
10A
10A−
0.0
1.0
(e)
ai
qi
im
prohibited areas
100 s/divµ
100 s/divµ
100 s/divµ
2ms/div
Fig. 4.13. Large-signal transient responses
(a) zoomed-out (b) & (c) zoomed-in: conventional control with immediate PWM update method
(d) &(e) zoomed-in: hybrid control with hybrid PWM update method
112
Fig. 4.13 illustrates the large-signal transient responses. The transient is considered large
when mi saturates and multiple cycles are needed to reach steady states. vdc is set at 24 V. Fig.
4.13(a) is a zoomed-out figure, and iAq*
E
A changes back and forth between 15 A and 0 A. Fig. 4.13(b)
and Fig. 4.13(c) are the zoomed-in figures of the first and second transients using the
conventional control with the immediate PWM update method. Fig. 4.13(d) and Fig. 4.13(e) are
the zoomed-in figures of the third and fourth transients using the hybrid control with the hybrid
PWM update method. The maximum mi is limited to 0.95 and 1.15 in the conventional and
hybrid controls.
Two advantages of the hybrid control are demonstrated. First, the full mi of the hybrid
control facilitates a larger transient amplitude per Tsamp. For example, the 11A transient in (d) is
larger than the 9.5A transient in (b). Second, a larger transient per Tsamp facilitates a faster overall
transient. For example, only about 7 Tsamp steps are required to reach a steady-state in (e),
whereas about 11 Tsamp steps are required in figure (c). Additionally, the q-axis predicted
current Ai E
Aq is also shown in the figures. Although there is some discrepancy between Ai E
Aq and iq due
to the inverter non-linear characteristics, the hybrid deadbeat control is robust and reaches the
steady-state without any problem. These large-signal transient response experiments demonstrate
that the hybrid control achieves faster responses than the conventional control.
113
(b)
(a)
*
*(0.125unit/ div) : duty cycle reference of phase- with delayed PWM update
(5A (5A/div): -axis current
(0.125unit/ d
/div): -axis current
iv) : duty cycle reference of phase- with immediate dy a
i
q
m a
ad ad a
iqa
i
−
−(1000 / div): PMSM rotation s
PWM peed per minut
updateeRPM rpm
*im ad −
RPM
20ms/div0.0
1.0
0A
20A
20A−
prohibited areas
20ms/div
*dy ad −
RPM
qiai
qiai
0A
20A
20A−
0.0
1.0
`
Fig. 4.14. Maximum speed test
(a) conventional control with delayed PWM update method (b) hybrid control with hybrid PWM update method
Fig. 4.14 shows the maximum speed test using the conventional and hybrid controls. vdc
is 24V, and a PMSM is tested without any load. The maximum mi is set at 1.5. Initially, iq* is set
at –20A, and the PMSM is rotating at the maximum negative speed. Once iq* is step changed from
–20A to +20A, the PMSM rapidly changes its speed from the maximum negative speed to the
maximum positive limit. In both cases, the maximum speed range is ±3300 rpm. It demonstrates
that the hybrid PWM update method with the full duty cycle range can achieve the same
maximum speed as the delayed PWM update method.
114
4.3 High speed control of three-phase ac drives
4.3.1 Literature review on high speed ac drives
The ratio between the switching frequency fsw of a driver and the electrical fundamental
frequency f1 of a machine becomes smaller as the speed of an ac machine increases. This ratio is
defined as
1
swratio
fFf
= . (4.1)
When a Fratio is less than 15, it is considered a high speed because f1 is relatively high for a given
fsw.
A Fratio might be small because f1 is large. For example, the rated f1 of a high-speed
machine often exceeds 1 kHz [59-63], and the fsw of medium and large industry machine drives
are typically set somewhere between 4 kHz and 40 kHz. On the other hand, a Fratio might be
small because fsw is small. For example, fsw can be in a sub-kHz range in some very high power
applications [64]. The excessive switching losses of devices, such as thyristors, IGBTs,
MOSFETs and diodes, require that the fsw of an ac drive be below a certain level of an fsw.
In past literature, different techniques are employed to achieve high-speed operations of
ac drives. A V/f scale control scheme is a simple technique for high-speed applications where
loads are predictable. It is an open-loop control with a predetermined V/f curve, in which the V/f
curve largely determines the system stability and operation performances. Its disadvantages are
poor dynamic performances and disturbance rejection. In [59] and [60], the f1 of 3.33kHz is
achieved with the fsw and sampling frequency fsamp of 33.3kHz (Fratio=10), and the f1 of 3 kHz is
achieved with the fsw of 20 kHz (Fratio=6.67), respectively.
115
A six-step/block commutation scheme is another simple technique that a fundamental
frequency f1 is matched with the same fsw by continuously conducting each phase for 120
electrical degrees, and thus a driver is capable of a very high fundamental frequency f1. However,
its disadvantages are that currents are not sinusoidal and that the fsw is not constant. This scheme
is employed in [65] to reach the f1 of 8.33 kHz with the fsw of 8.33 kHz for an ultra-high speed,
low power electrical drive system (Fratio=1.0).
Although V/f and six-step schemes are acceptable solutions for some specific high-speed
ac drive applications, a cascaded control scheme is a more general solution that provides better
performances in high speed ac drives. The cascade control refers to a scheme that an outer speed
control loop generates the references for inner current control loops, and it is shown in Fig. 3.2.
In [59], the f1 of 1.8 kHz is achieved with the fsw of 33.3 kHz (Fratio=18.5). In [61], the f1 of 1083
Hz is achieved with the fsw of 15 kHz (Fratio=13.8). In [62], the f1 of 1.77 kHz is achieved with
the fsw of 15 kHz (Fratio=8.4). In [63], the f1 of 2 kHz is achieved with the fsw of 15 kHz
(Fratio=7.5). In [62, 66], the f1 of 440 Hz is achieved with the fsw of 2 kHz (Fratio=4.55).
In the cascade control scheme, the maximum achievable driving speed is determined by
the performance of the position/speed sensorless technique and the stability of current control
loops. The focus is on the current control loop design and its stability, and it is assumed that the
position/speed is either measured with a sensor or well estimated by a sensorless technique.
A couple of techniques can be administered to improve the current loop stability at high
speed. First, a suitable current controller design method for high speed operation is utilized.
Since the conventional PI control cannot compensate the accumulated effect of time delays,
discretization and cross-coupling terms during high-speed operations, the control must be
designed directly in the discrete-time domain with a proper plant model, which is given in
116
sections 3.1 and 3.2. This method is also previously proposed in [30]. For low and medium speed
ac drives, a PI current control is an acceptable option since the effect is negligible; however,
maintaining stable current control loops becomes progressively difficult as a Fratio becomes
smaller [66]. Second, the hybrid PWM update method is utilized to eliminate the effect of the
Td-one. The elimination of the Td-one provides additional phase margins. Additionally, the
controller gain is tuned less aggressively than the deadbeat control to provide larger gain and
phase margins.
4.3.2 Gain design and stability analysis
In the deadbeat control, ωcc is set equal to the 1/6th of the fsamp (i.e. ωcc = 2πfsamp/6). For
the high speed control, the focus is on the current loop stability, rather than the fast response
characteristics. Thus, ωcc is tuned less aggressively, and thus, ωcc is set equal to 1/18th of the
fsamp (i.e. ωcc = 2πfsamp/18).
Table 4.2. Gain and phase margins and closed current loop bandwidth
ωcc Gain Margin Phase Margin Bandwidth (±3dB)
Bandwidth (-90˚)
TI(z) & GI(z) 2πfsamp/6 6.02 dB 60 ˚ Inf. 5 kHz 2πfsamp/18 15.2 dB 80 ˚ 1.38 kHz 2.74 kHz
TI_d-one(z) & GI_d-one(z)
2πfsamp/6 0.0 dB 0 ˚ – – 2πfsamp/18 9.19 dB 60 ˚ 2.65 kHz 1.62 kHz
TI_pred(z) & GI_pred(z)
2πfsamp/6 6.02 dB 60 ˚ Inf. 2.5 kHz 2πfsamp/18 15.2 dB 80 ˚ 1.38 kHz 1.52 kHz
117
The gain and phase margins and closed current loop bandwidth in Table 3.1 is duplicated
in Table 4.2 for an easy reference. When the delayed PWM update method is utilized, the gain
and phase margins of TI_d-one(z) with ωcc = 2πfsamp/18 are 9.19 dB and 60˚, respectively. When the
hybrid PWM update method is utilized and the Td-one is eliminated, the gain and phase margins of
the TI(z) with ωcc = 2πfsamp/18 are 15.2 dB and 80˚, respectively. The hybrid PWM update can
provide extra 6 dB gain and 20˚ phase margins. The gain and phase margins of the hybrid PWM
update is the same as TI(z) & GI(z).
increasingsynchronousfrequency
(a)
out of unit circle
increasingsynchronousfrequency
stays stationarysat all synchronous frequency
(b)
Fig. 4.15. Complex-vector eigenvalue migration patterns without Td-one when ωe increases
(a) PI controller and feedforward compensation (b) perfect pole-zero cancellation controller
Fig. 4.15 illustrates the complex-vector eigenvalue migration patterns when the
synchronous frequency ωe increases from 0 to 1/4th of the fsamp of 20 kHz, and the migration step
is 200 Hz. The one-step control delay Td-one is assumed to be eliminated, and the stability
characteristic between a conventional PI control with a feedforward and the pole-zero
cancellation controller is compared. The estimated machine parameters L^ and R^ are assumed to
be equal to the actual parameters L and R. Typical inductances and resistances of a high power,
118
high speed PMSM are around 100~300 µH and less than 10 mΩ. Although the inductances are
set to 100 µH, which is a reasonable value, the resistances are set to 100 mΩ, which is much
larger than typical, to accentuate the divergence of poles and zeros. ωcc equals 1/18th of fsamp.
Fig. 4.15(a) illustrates the migration patterns of current loop with a PI control. The poles
near (1,0) are perfectly cancelled by the zeros only when ωe is zero. As ωe increases and Fratio
becomes smaller, the accumulated effect of the time delays, discretization, and cross-coupling
terms starts to play more dominant roles, and the PI controller method does not accurately
account for these. A consequence is that the poles move toward the unit circle while the zeros
remain stationary. Thus, the pole-zero cancellations are approximate, even if appropriate delays
are compensated and actual parameter values are used in the controllers. Additionally, the
dominant poles, which are not cancelled by zeros, move toward the unit circle, and the poles
eventually move outside of the unit circle as the synchronous frequency increases.
Fig. 4.15(b) illustrates the migration patterns of current loop with the perfect pole-zero
cancellation control. All the synchronous frequency dependent moving poles near the unit circle
are perfectly canceled by the moving controller zeros at all synchronous frequencies.
Additionally, the stationary dominant poles ensure the same transient response with the same
gain and phase margin at all ωe.
119
4.3.3 Experimental results of high speed ac drives
0A
-40A
40A
180°0°
180− °
1ms/div
(20A/div): -axis current (actu(20A/ div): -axis cu
(100V/div): line
rrent (measured)
-to-line volta
(18
al
0 / div) : electrical angl
g
e
)el
e
a
a
liv
iaa
θ
−
°
ai
l lv −
ai
eθ
100V+
100V−
0A
-40A
40A
180°0°
180− °
ai
l lv −
ai
eθ
100V+
100V−
1ms/div
(b)
(a)
Fig. 4.16. Steady-state operation with a very small Fratio
(a) Fratio = 3.33, f1 = 300 Hz,1 kHz switching and 1 kHz sampling frequency
(b) Fratio = 2.0, f1 = 500 Hz, 1 kHz switching and 2 kHz sampling frequency
The experimental results aim to show two points. First, the proposed method’s ability to
operate at a very small Fratio. Second, the proposed method’s ability to reject cross-coupling at
high speed.
Fig. 4.16 illustrates the steady-state operations with a very small Fratio. The hybrid PWM
update method with ωcc = 2πfsamp/18 is applied for extra stability margins. Also, vdc is increased
to 45V in order to drive the motor at a higher speed. Fig. 4.16(a) illustrates the experiment result
when the Fratio of 3.33 (f1 = 300 Hz) is achieved with 1 kHz switching and sampling frequency.
Fig. 4.16(b) illustrates the experiment result when the Fratio of 2.0 (f1 = 500 Hz) is achieved with
1 kHz switching frequency and 2 kHz sampling frequency. These small Fratio are rarely
encountered in normal operating conditions. In fact, such small Fratio may be even undesirable
120
due to poor current waveform may lead to large torque ripples and poor motor efficiency. The
importance of these experiments is to verify that the proposed hybrid current controller can
maintain a stable current loop even under a very small Fratio.
The current waveforms are only quasi-sinusoidal waveforms due to a very small Fratio,
high switching ripples, and a low fundamental current amplitude with respect to the switching
ripple amplitude. Similarly, the sensed currents are quasi-sinusoidal due to a very small Fratio.
The current waveforms will improve and start to resemble sinusoidal if the Fratio is increased to a
reasonable operating condition, and this can be observed in following figures.
0A
20A
-20A
2.0ms/div
(a)
0A
20A
-20A
2.0ms/div
(b)
* (10A/div) : -axis current refer
(10A/div) : -axis current (ac
(10A/ div): -axi
(10A/div) : -axis curre
s current feedback (10A/ div): -axis curren
t
t feedb
nt (measur
a
ence
u)
ck
dal)
e
q
d
a
q
ai aq
d
i
i
a
iq
i
aiai
*qi
di
qi
aiai
qi
Fig. 4.17. Transient responses of the proposed method to step current changes at Fratio=5.0
(a) on q-axis (b) on d-axis
Fig. 4.17 shows the transient responses to step current changes on the q-axis and d-axis.
The hybrid PWM update method with ωcc = 2πfsamp/6 is applied. ωcc is increased from 2πfsamp/18
to 2πfsamp/6, which is the most demanding to the current controllers. The switching and sampling
frequencies are set at 2 kHz and 4 kHz, respectively, and the synchronous frequency is 400 Hz
121
(Fratio = 5.0). In Fig. 4.16(a), the q-axis current reference changes from 0 A to 20 A at 4 ms and
back to 0 A at 16 ms, while the d-axis current (not shown) is at 0A. Due to the deadbeat
characteristic of the selected operation conditions, the feedback current immediately matches the
reference at the next sampling period, which can be observed in the q-axis and the phase-a
current feedbacks. In Fig. 4.16(b), the d-axis current reference changes from -15 A to +15 A at 6
ms and back to -15A at 14 ms, while the q-axis current is at 10A. Similar to the q-axis transients,
the d-axis current feedback match the reference in one sampling period. This figure also
demonstrates the high cross-coupling rejection capability of the proposed control method.
Despite a very steep and abrupt d-axis current change, all the cross-coupling from the d-axis to
the q-axis is rejected, and the q-axis current is held constant. Also, this figure shows that the
proposed method can be applied to field weakening regions since the controller operates well
from the field weakening at -15 A to the field “strengthening” at +15 A. Lastly, the slight ripples
on the feedback currents are mainly due to current zero-crossing distortions. The zero-crossing
distortions are difficult to compensate during the low Fratio operations because the current
changes from one sampling to next sampling are large and rapid. Other factors that may cause
the ripples are parameter mismatches, but its affects are small compared to the zero-crossing
distortions.
122
(a)
0A
20A
-20A
2.0ms/div
2.0ms/div
(b)
(10A/div) : -axis current (measured) (10A/div) : -axis current fe
(10A/div)
edback
: -axis current
(10A/ div
(actua
): -axis current feedback
l)a
a
q
qi d
aq
aii
i
0A
20A
-20A
aiai
qi di
aiai
qi di
Fig. 4.18. Transient responses of PI controller to step current changes
(a) at Fratio=6.66 (b) at Fratio=5.0
Fig. 4.18 shows the identical test as in Fig. 4.17(b) when a PI controller with a
feedforward compensation utilized instead of the perfect pole-zero cancellation controller. The
phase delay of the Td-PWM is compensated with the addition of an equivalent 0.5 Tsamp Euler
rotation vector in the controller. In Fig. 4.18(a), the synchronous frequency is 300 Hz (Fratio =
6.66). Unlike the proposed control method, the step changes on the d-axis have large overshoots
and the cross-coupling on the q-axis is clearly observed. In Fig. 4.18(b), the synchronous
frequency is increased to 400 Hz (Fratio = 5.0). When the synchronous speed increases, the
overshoot and the cross-coupling have increased noticeably and the transient ringing last much
longer than that of from the 300 Hz. Comparison between Fig. 4.17 and Fig. 4.18 clearly shows
the superior performance of the perfect pole-zero cancellation control method.
123
Chapter 5
Conclusion and Future Direction
5.1 Conclusion
A novel hybrid PWM update method is proposed. The major works are summarized as
follows.
First, the conventional PWM update methods, such as the immediate and delayed PWM
updates, are analyzed to show its advantages and disadvantages. The immediate PWM update
method can eliminate the effect of the one-step control time delay Td-one at the cost of the reduced
duty cycle range. In comparison, the delayed PWM update method has the full duty cycle range,
but the Td-one exists. Existing novel PWM update methods are also analyzed, but these existing
methods cannot guarantee the full duty cycle range under all conditions. Additionally, these can
be applied only to single-phase applications with the single-sampling method.
Second, the hybrid PWM update method is proposed to eliminate the effect of the Td-one
without losing the full duty cycle range. Unlike existing novel PWM update methods, the
proposed method is applicable to both the single- and double-sampling methods, as well as
single-phase and three-phase applications. The hybrid PWM update method is a simple concept
that the PWM is updated multiple times per sampling period (Tsamp) whereas the conventional
methods only update the PWM one time per Tsamp. To take full advantages of the hybrid PWM
update method, the hybrid control method is proposed to optimize the sequence of control
124
operations. It maximizes the current loops’ robustness and minimizes the delay from the
sampling instant of outer control loops’ variables to the duty cycle update instant. The minimum
delay enables the maximization of the outer control loops’ bandwidth. Additionally, a corrective
neutral offset voltage injection method is proposed to correct small PWM output deviations that
may occur with the hybrid PWM update method.
Third, the control laws of the hybrid control is established. The plant is discretized and
modeled, and current controllers are designed in discrete-time domain. If the plant parameters
are known, such as inductances, resistances and back-emf constant, then the control law requires
only one parameter to complete the control design: a desired open-loop crossover frequency ωcc.
The stability ranges of the hybrid control is analyzed and compared to the conventional and
predictive controls, which revealed superior stability and robustness characteristics of the
proposed method.
Fourth, utilizing a three-phase voltage source inverter with a permanent magnet
synchronous machine as the platform, a deadbeat current control and a high speed ac drive
experiments have been conducted to demonstrate the feasibility and validity. Notable results
include a closed current loop response of one Tsamp with the deadbeat control and a 500 Hz
current fundamental frequency with 1 kHz switching frequency in a high speed ac drive.
A high closed current loop bandwidth is selected as the working example to demonstrate
the performance improvements, and this is achieved using the proposed hybrid control and the
deadbeat algorithms. The deadbeat controls’ performances with the conventional and proposed
PWM update methods are summarized in Table 5.1 for comparison.
125
Table 5.1. Comparison of the conventional and hybrid PWM update methods with deadbeat control
One-cycle deadbeat Two-cycle Deadbeat Proposed Hybrid Deadbeat
PWM update method Immediate Delayed Hybrid
= Immediate + Delayed
Ideal response time 1 Tsamp 2 Tsamp 1 Tsamp Duty cycle range Reduced Full Full
Robustness Good Poor Nearly as good as one-cycle deadbeat
Number of PWM updates per sampling
period 1 1 2 or 3
Number of sampling per sampling period 1 1 1
Number of required interrupt 1 1 2
Computation requirement
Current sampling, Speed estimation,
Speed control, Current control
One-cycle deadbeat + current prediction
Two-cycle deadbeat + extra interrupt + one extra current control
computation
Notable achievements are as follows
i) the ideal deadbeat response of one Tsamp delay is achieved, which is equivalent of
doubling the closed-loop bandwidth when compared to the bandwidth of the two-
cycle deadbeat control with two Tsamp delays,
ii) the robustness is significantly improved without any additional compensation
algorithms when compared to the two-cycle deadbeat control, and
iii) the full duty cycle range is maintained, whereas the duty cycle must be limited in
the immediate PWM update.
Overall, the performance of the hybrid deadbeat control is inherently superior to the
performance of any two-cycle deadbeat controls and can either match or exceed the performance
of conventional one-cycle deadbeat controls. Compared to the conventional and predictive
126
controls, the hybrid control only requires small extra overheads, such are one more interrupt, one
more current controller computation, and one or two more PWM updates.
127
5.2 Contribution
One major contribution and two supplemental contributions have been made, which are
summarized as follows.
A novel hybrid PWM update method is proposed, which eliminate the effect of the one-
step control time delay Td-one without losing the full duty cycle range.
In order to supplement the hybrid PWM update method, the hybrid control method is
proposed to optimize the sequence of control operations. It maximizes the current loops’
robustness and minimizes the delay from the sampling instant of outer control loop’s variables to
the duty cycle update instant. It enables the maximization of the outer control loop’s bandwidth.
Another proposed supplement to the hybrid PWM update method is the corrective neutral
offset voltage injection method, which corrects small PWM output deviations that may occur
with the hybrid PWM update method.
Without the Td-one and with the full duty cycle range, a very high quality digital current
control can be achieved with the proposed method, which are
i) fast dynamic responses of the current loops during a transient,
ii) lower current ripples in the steady-state,
iii) a highly stable PWM inverter operation,
iv) robustness against the disturbances,
v) minimum delay for the outer control loops, and
vi) maximum supply voltage utilization.
128
5.3 Future direction
The hybrid PWM update method is a simple concept of updating the PWM outputs
multiple times in a Tsamp. In spite of the simplicity of the proposed method, the performance
improvements in stability, robustness and response characteristics are significant. On the other
hand, the proposed method can be easily applied to many PWM based digital controls because of
its simplicity. Only requirements are that a control target variable is predictable and PWM can be
updated multiple times.
The proposed concept is verified using an ac motor drive system with a PMSM; however,
it can be applied to a variety of systems. Possible applications include but not limited to the
examples of the current control applications in section 1.2 and many other applications, such as
single-phase and three-phase UPS applications, grid-tied inverter applications, high-speed motor
drives, servo motor drives and active filters. The proposed method can be easily applied to these
applications for performance improvements.
Lastly, the application of the proposed hybrid PWM update concept is studied with the
uniformly sampled system. However, the fundamental concept can be extended to non-uniformly
sampled system as well.
129
Appendix A Plant modeling
The derivation of the discrete plant model Gp(z) in (3.1) is as follows. The overall
procedure is also given in [30] as well.
Without a back-emf voltage term, a symmetric machines, such as surface PMSM and
induction, can be modeled as a simple resistor and inductor complex vector transfer function in
the stationary reference frame as
( ) 1spG s
L s R=
⋅ +. (A.1)
Superscript “s” denotes that equations are in stationary reference frame. The digital PWM with a
triangular modulation can be modeled as an ideal zero-order hold (ZOH) transfer function, which
is detailed in section 2.1. Thus, the plant model with a ZOH can be modeled as
( )_1 1 sampsT
sp ZOH
eG sL s R s
− −= ⋅ +
. (A.2)
The continuous-time domain transfer function of (A.2) is easily discretized as
( ) ( )( )
( )
( )( ) ( )/
/
1 1samp
samp
R L Tssp s R L T
z e eG zz R z eR z e
α
α
− −
−−
− −= = =
−−
iv
. (A.3)
The resulting difference equation in the stationary reference frame is given as
[ ] [ ] ( ) [ ]1
1 1s s se
k k k eR
αα
−−
−= − −i v + i . (A.4)
This is coordinate transformed to the synchronous reference frame as
130
[ ] [ ] [ ] [ ] ( ) [ ] [ ]
[ ] [ ] [ ]( ) ( ) [ ] [ ] [ ]( )
[ ] [ ] [ ] ( ) [ ] [ ] [ ]
1 1 1 1
1 11 1
11 1
11 1
11 1
e samp e samp
e samp e samp
j k j k j ks s s
j k k T j k k Ts s
j k T j k Tj k j ks s
ek e k e k e e
Re
k e k e eR
ek e e k e e e
R
αθ θ θ α
αθ ω θ ω α
αω ωθ θ α
−− − − −
−− − + − − − + − −
−− − − −− − − − −
−⋅ = − ⋅ − ⋅ ⋅
−= − ⋅ − ⋅ ⋅
−= − ⋅ ⋅ − ⋅ ⋅ ⋅
i v + i
v + i
v + i
, (A.5)
which simplifies as
[ ] [ ] [ ] ( ) [ ] [ ]
[ ] ( ) [ ] [ ]
1 1
1
11 1
11 1
e samp e samp
e samp
j k T j k Te e e
j k Te e
ek k e k e e
Re
k k e eR
αω ω α
αωα
−− − − − −
−− −−
−= − ⋅ − ⋅ ⋅
− = − − ⋅ ⋅
i v + i
v + i. (A.6)
Superscript “e” denotes that equations are in the synchronous reference frame. The transfer
function is reconstructed from the difference equation to a transfer function as
( ) ( )( )
1 1e samp
eep j Te
z eG zz R ze e
α
ω α
−
−
−= =
−
iv
. (A.7)
The final equation of (A.7) is the discrete plant model in (3.1) after adding a back-emf term and
after dropping the superscript “e” for a simplified expression.
131
Appendix B Scalar representation of the current loop
ˆsin( )e sampTω
*qi
ˆ1ˆcos( )e sampT z e αω − −−ˆ
ˆ
1KR
e α−−
Digital Controller
ˆ
ˆ
1KR
e α−−
ˆsin( )e sampTω
ˆ1ˆcos( )e sampT z e αω − −−*di
de
qe
Plant
di
1z− ˆˆe fω φ
qi
e fω φ
*qv ( )1 1z e
R
α− −−( ) 1
1cos e sampT z e αω − −−
sin( )e sampTω
sin( )e sampTω
1z−
*dv
( )1 1z eR
α− −−( ) 1
1cos e sampT z e αω − −−
Fig. Appendix B.1. Scalar representation of the proposed current control loop in Fig. 3.3
In the analyses of main text, the complex-vector notations are utilized to simplify the
models from a two-input, two-output structure to an equivalent single-input, single-output
complex-vector structure. However, a scalar representation with a two-input and two-output
structure is necessary and convenient for the actual implementation of the proposed controllers.
The complex-vector representation is shown in Fig. 3.3, and its equivalent scalar representation
is shown in Fig. Appendix B.1.
132
Appendix C Increase of the modulation index limitation by
neutral offset voltage manipulation
In section 3.1.5, the modulation index mi limitation is discussed. The mi(max) thresholds
are given as
-* 4( ) ( ) 1 d comp
i isw
Tm m max
T≤ = −u (C.1)
when SPWM is utilized, and given as
-* 42( ) ( ) 13
d compi i
sw
Tm m max
T
≤ = −
u (C.2)
when SVPWM is utilized. These thresholds can be increased when the single-sampling is
utilized. The thresholds remain the same for double-sampling.
0.6im =/ 2dcv
0.0
*anu *
bnu*cnu
*snu
/ 2dcv−0 π 2π
Fig. Appendix C.1 SPWM with usn* =0 and mi=0.6
Fig. Appendix C.1 illustrates the PWM with usn* =0 and mi=0.6. The Td-comp is assumed to
be 10% of Tsw. Thus, the mi(max) threshold is 0.6 according to (C.1). For single-sampling at top,
the prohibited area is applied only at the area near the vdc/2, as shown in the figure. The area near
133
the –vdc/2 is not being utilized. Therefore, the mi(max) threshold can be increased simply by
applying a usn* offset. For single-sampling at top, the usn
* offset is given as
-* 22
d comp dcsn
sw
T vuT
= − ⋅ . (C.3)
For single-sampling at bottom, the usn* offset is given as
-* 22
d comp dcsn
sw
T vuT
= ⋅ . (C.4)
0.8im =/ 2dcv
0.0
*anu
*bnu *
cnu
*snu
/ 2dcv−0 π 2π
Fig. Appendix C.2 SPWM with usn* = –2Td-samp/Tsw and mi=0.8
Fig. Appendix C.2 illustrates the usn* offset for single-sampling at top. This usn
* offset can
increase the mi(max) threshold as
-* 2( ) ( ) 1 d comp
i isw
Tm m max
T≤ = −u . (C.5)
The same offset concept can be applied to the SVPWM as well.
Instead of the offset, a discontinuous PWM can be applied to achieve a similar mi(max)
threshold increase. The 120(OFF)DPWM can be utilized for the single-sampling at top, the usn*
offset is given as
* *
2dc
sn maxvu u= − . (C.6)
134
The 120(ON)DPWM can be utilized for the single-sampling at bottom, the usn* offset is given as
* *
2dc
sn minvu u= − − . (C.7)
2 3 0.8im = ⋅/ 2dcv
0.0
*anu *
bnu *cnu
*snu
/ 2dcv−0 π 2π
Fig. Appendix C.3 120(OFF)DPWM with and mi=1.15*0.8
Fig. Appendix C.3 illustrates the The 120(OFF)DPWM for single-sampling at top. This
usn* offset can increase the mi(max) threshold as
-* 22( ) ( ) 13
d compi i
sw
Tm m max
T
≤ = −
u (C.8)
135
References
[1] B. K. Bose, Power Electronics and Motor Drives: Advances and Trends: Elsevier Science, 2010.
[2] P. Cortes, M. P. Kazmierkowski, R. M. Kennel, D. E. Quevedo, and J. Rodriguez, "Predictive Control in Power Electronics and Drives," IEEE Trans. Ind. Electron. , vol. 55, pp. 4312-4324, 2008.
[3] F. Morel, L.-S. Xuefang, J. M. Retif, B. Allard, and C. Buttay, "A Comparative Study of Predictive Current Control Schemes for a Permanent-Magnet Synchronous Machine Drive," IEEE Trans. Ind. Electron., vol. 56, pp. 2715-2728, 2009.
[4] Y. A. R. I. Mohamed and E. F. El-Saadany, "An Improved Deadbeat Current Control Scheme With a Novel Adaptive Self-Tuning Load Model for a Three-Phase PWM Voltage-Source Inverter," IEEE Trans. Ind. Electron., vol. 54, pp. 747-759, 2007.
[5] S. Buso and P. Mattavelli, Digital Control in Power Electronics: Morgan & Claypool Publishers, 2006.
[6] C. Jong-Woo and S. Seung-Ki, "New current control concept-minimum time current control in the three-phase PWM converter," IEEE Trans. Power Electron., vol. 12, pp. 124-131, 1997.
[7] M. Hinkkanen, H. A. A. Awan, Z. Qu, T. Tuovinen, and F. Briz, "Current Control for Synchronous Motor Drives: Direct Discrete-Time Pole-Placement Design," IEEE Trans. Ind. Appl., vol. 52, pp. 1530-1541, 2016.
[8] A. G. Yepes, A. Vidal, J. Malvar, L. O, x00F, pez, et al., "Tuning Method Aimed at Optimized Settling Time and Overshoot for Synchronous Proportional-Integral Current Control in Electric Machines," IEEE Trans. Power Electron., vol. 29, pp. 3041-3054, 2014.
[9] L. Harnefors and H. P. Nee, "Model-based current control of AC machines using the internal model control method," IEEE Trans. Ind. Appl., vol. 34, pp. 133-141, 1998.
[10] C. Byungcho, "Current Mode Control - Functional Basics and Classical Analysis," in Pulsewidth Modulated DC-to-DC Power Conversion:Circuits, Dynamics, and Control Designs, ed: Wiley-IEEE Press, 2013, p. 664.
[11] J. Bocker, S. Beineke, and A. Bahr, "On the control bandwidth of servo drives," in Power Electronics and Applications, 2009. EPE '09. 13th European Conference on, 2009, pp. 1-10.
[12] D. G. Holmes and T. A. Lipo, Pulse Width Modulation for Power Converters: Principles and Practice: John Wiley & Sons, 2003.
[13] D. M. Van De Sype, K. De Gusseme, A. P. Van Den Bossche, and J. A. Melkebeek, "Small-signal Laplace-domain analysis of uniformly-sampled pulse-width modulators," in Power Electronics Specialists Conference, 2004. PESC 04. 2004 IEEE 35th Annual, 2004, pp. 4292-4298 Vol.6.
[14] D. Heng, R. Oruganti, and D. Srinivasan, "PWM methods to handle time delay in digital control of a UPS inverter," IEEE Power Electron. Lett., vol. 3, pp. 1-6, 2005.
[15] D. Yang, X. Ruan, and H. Wu, "A Real-Time Computation Method With Dual Sampling Mode to Improve the Current Control Performance of the LCL-Type Grid-Connected Inverter," IEEE Trans. Ind. Electron., vol. 62, pp. 4563-4572, 2015.
136
[16] S. Moon, J.-M. Choe, J.-S. Lai, Z. Yu, R. Ramamoorthy, S. Sabapathy, et al., "Under review: High Bandwidth Digital Current Controller Combining Sub-Cycle and One-Cycle PWM Updates for Ac Motor Drives," IEEE Trans. Emerg. Sel. Topics Power Electron., 2016.
[17] Texas Instruments. TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual: 14 Enhanced Pulse Width Modulator (ePWM)
[18] B.-H. Bae and S.-K. Sul, "A compensation method for time delay of full-digital synchronous frame current regulator of PWM AC drives," IEEE Trans. Ind. Appl., vol. 39, pp. 802-810, 2003.
[19] N. S. Nise, Control Systems Engineering: Wiley, 2004. [20] National Electrical Manufacturers Association, "Industrial Control and Systems:
Motion/Position Control Motors, Controls and Feedback Devices," in NEMA Standard Publication ICS 16, ed, 2004.
[21] V. Blasko, V. Kaura, and W. Niewiadomski, "Sampling of discontinuous voltage and current signals in electrical drives: a system approach," IEEE Trans. Ind. Appl., vol. 34, pp. 1123-1130, 1998.
[22] P. Cortes, J. Rodriguez, C. Silva, and A. Flores, "Delay Compensation in Model Predictive Current Control of a Three-Phase Inverter," IEEE Trans. Ind. Electron., vol. 59, pp. 1323-1325, 2012.
[23] J. M. Espi, J. Castello, R. Garcia-Gil, G. Garcera, and E. Figueres, "An Adaptive Robust Predictive Current Control for Three-Phase Grid-Connected Inverters," IEEE Trans. Ind. Electron., vol. 58, pp. 3537-3546, 2011.
[24] L. Jae Sik, P. Changreung, H. Jungho, and L. Young Il, "Robust Tracking Control of a Three-Phase DC-AC Inverter for UPS Applications," IEEE Trans. Ind. Electron., vol. 61, pp. 4142-4151, 2014.
[25] H.-T. Moon, H.-S. Kim, and M.-J. Youn, "A discrete-time predictive current control for PMSM," IEEE Trans. Power Electron., vol. 18, pp. 464-472, 2003.
[26] E. Jung, H.-J. Lee, and S.-K. Sul, "FPGA-based motion controller with a high bandwidth current regulator," in Power Electronics Specialists Conference, 2008. PESC 2008. IEEE, 2008, pp. 3043-3047.
[27] A. Yoo, Y.-D. Yoon, S.-K. Sul, M. Hisatune, S. Morimoto, and K. Ide, "Design of a Current Regulator with Extended Bandwidth for Servo Motor Drive," in Power Conversion Conference - Nagoya, 2007. PCC '07, 2007, pp. 1308-1314.
[28] H. Abu-Rub, J. Guzinski, Z. Krzeminski, and H. A. Toliyat, "Predictive current control of voltage-source inverters," IEEE Trans. Ind. Electron., vol. 51, pp. 585-593, 2004.
[29] S. Moon, J.-M. Choe, Y. Cho, and J.-S. Lai, "Priority Based Current Control Design in High Speed Sensorless PMSM Drives," in Power Electronics and ECCE Asia (ICPE & ECCE), 2015 IEEE 9th International Conference on, Korea, 2015.
[30] H. Kim, M. W. Degner, J. M. Guerrero, F. Briz, and R. D. Lorenz, "Discrete-Time Current Regulator Design for AC Machine Drives," IEEE Trans. Ind. Appl., vol. 46, pp. 1425-1435, 2010.
[31] L. Harnefors, X. Wang, A. G. Yepes, and F. Blaabjerg, "Passivity-Based Stability Assessment of Grid-Connected VSCs - An Overview," IEEE Trans. Emerg. Sel. Topics Power Electron., vol. 4, pp. 116-125, 2016.
137
[32] C. Chen, J. Xiong, Z. Wan, J. Lei, and K. Zhang, "A Time Delay Compensation Method Based on Area Equivalence For Active Damping of an LCL-Type Converter," IEEE Trans. Power Electron., vol. 32, pp. 762-772, 2017.
[33] L. Corradini and P. Mattavelli, "Modeling of Multisampled Pulse Width Modulators for Digitally Controlled DC-DC Converters," IEEE Trans. Power Electron., vol. 23, pp. 1839-1847, 2008.
[34] J. Allmeling and H. Stemmler, "A fast current control technique for active filters with low switching frequency," in Industrial Electronics Society, 2001. IECON '01. The 27th Annual Conference of the IEEE, 2001, pp. 1125-1131 vol.2.
[35] F. Briz, M. W. Degner, and R. D. Lorenz, "Analysis and design of current regulators using complex vectors," IEEE Trans. Ind. Appl., vol. 36, pp. 817-825, 2000.
[36] L. Springob and J. Holtz, "High-bandwidth current control for torque-ripple compensation in PM synchronous machines," IEEE Trans. Ind. Electron., vol. 45, pp. 713-721, 1998.
[37] X. Zhang, B. Hou, and Y. Mei, "Deadbeat Predictive Current Control of Permanent Magnet Synchronous Motors with Stator Current and Disturbance Observer," IEEE Trans. Power Electron., vol. PP, pp. 1-1, 2016.
[38] J. W. Umland and M. Safiuddin, "Magnitude and symmetric optimum criterion for the design of linear control systems: what is it and how does it compare with the others?," IEEE Trans. Ind. Appl., vol. 26, pp. 489-497, 1990.
[39] J. C. Moreno, J. M. E. Huerta, R. G. Gil, and S. A. Gonzalez, "A Robust Predictive Current Control for Three-Phase Grid-Connected Inverters," IEEE Trans. Ind. Electron., vol. 56, pp. 1993-2004, 2009.
[40] K.-H. Kim and M.-J. Youn, "A simple and robust digital current control technique of a PM synchronous motor using time delay control approach," IEEE Trans. Power Electron., vol. 16, pp. 72-82, 2001.
[41] P. Wipasuramonton, Z. Q. Zhu, and D. Howe, "Predictive current control with current-error correction for PM brushless AC drives," IEEE Trans. Ind. Appl., vol. 42, pp. 1071-1079, 2006.
[42] P. Mattavelli, F. Polo, F. Dal Lago, and S. Saggini, "Analysis of Control-Delay Reduction for the Improvement of UPS Voltage-Loop Bandwidth," IEEE Trans. Ind. Electron., vol. 55, pp. 2903-2911, 2008.
[43] A. M. Hava, R. J. Kerkman, and T. A. Lipo, "A high-performance generalized discontinuous PWM algorithm," IEEE Trans. Ind. Appl., vol. 34, pp. 1059-1071, 1998.
[44] A. M. Hava, R. J. Kerkman, and T. A. Lipo, "Simple analytical and graphical methods for carrier-based PWM-VSI drives," IEEE Trans. Power Electron., vol. 14, pp. 49-61, 1999.
[45] L.-H. Hoang, K. Slimani, and P. Viarouge, "Analysis and implementation of a real-time predictive current controller for permanent-magnet synchronous servo drives," IEEE Trans. Ind. Electron., vol. 41, pp. 110-117, 1994.
[46] P. Correa, M. Pacas, and J. Rodriguez, "Predictive Torque Control for Inverter-Fed Induction Machines," IEEE Trans. Ind. Electron., vol. 54, pp. 1073-1079, 2007.
[47] S.-M. Yang and C.-H. Lee, "A deadbeat current controller for field oriented induction motor drives," IEEE Trans. Power Electron., vol. 17, pp. 772-778, 2002.
138
[48] S. Buso, S. Fasolo, and P. Mattavelli, "Uninterruptible power supply multiloop control employing digital predictive voltage and current regulators," IEEE Trans. Ind. Appl., vol. 37, pp. 1846-1854, 2001.
[49] P. Mattavelli, "An improved deadbeat control for UPS using disturbance observers," IEEE Trans. Ind. Electron., vol. 52, pp. 206-212, 2005.
[50] P. Mattavelli, G. Spiazzi, and P. Tenti, "Predictive digital control of power factor preregulators with input voltage estimation using disturbance observers," IEEE Trans. Power Electron., vol. 20, pp. 140-147, 2005.
[51] S. Saggini, W. Stefanutti, E. Tedeschi, and P. Mattavelli, "Digital Deadbeat Control Tuning for dc-dc Converters Using Error Correlation," IEEE Trans. Power Electron., vol. 22, pp. 1566-1570, 2007.
[52] J. Seung-Gi and W. Myung-Ho, "DSP-based active power filter with predictive current control," IEEE Trans. Ind. Electron., vol. 44, pp. 329-336, 1997.
[53] J. Mossoba and P. W. Lehn, "A controller architecture for high bandwidth active power filters," IEEE Trans. Power Electron., vol. 18, pp. 317-325, 2003.
[54] L. Malesani, P. Mattavelli, and S. Buso, "Robust dead-beat current control for PWM rectifiers and active filters," IEEE Trans. Ind. Appl., vol. 35, pp. 613-620, 1999.
[55] Y. Nishida, O. Miyashita, T. Haneyoshi, H. Tomita, and A. Maeda, "A predictive instantaneous-current PWM controlled rectifier with AC-side harmonic current reduction," IEEE Trans. Ind. Electron., vol. 44, pp. 337-343, 1997.
[56] G. H. Bode, L. Poh Chiang, M. J. Newman, and D. G. Holmes, "An improved robust predictive current regulation algorithm," IEEE Trans. Ind. Appl., vol. 41, pp. 1720-1733, 2005.
[57] Y. A. R. I. Mohamed and E. F. El-Saadany, "Robust High Bandwidth Discrete-Time Predictive Current Control with Predictive Internal Model - A Unified Approach for Voltage-Source PWM Converters," IEEE Trans. Power Electron., vol. 23, pp. 126-136, 2008.
[58] Y. A. R. I. Mohamed and E. F. El-Saadany, "Adaptive Discrete-Time Grid-Voltage Sensorless Interfacing Scheme for Grid-Connected DG-Inverters Based on Neural-Network Identification and Deadbeat Current Regulation," IEEE Trans. Power Electron., vol. 23, pp. 308-321, 2008.
[59] L. Xu and C. Wang, "Implementation and experimental investigation of sensorless control schemes for PMSM in super-high variable speed operation," in Industry Applications Conference, 1998. Thirty-Third IAS Annual Meeting. The 1998 IEEE, 1998, pp. 483-489 vol.1.
[60] J. Oyama, T. Higuchi, T. Abe, K. Shigematsu, X. Yang, and E. Matsuo, "A trial production of small size ultra-high speed drive system," in Electric Machines and Drives Conference, 2003. IEMDC'03. IEEE International, 2003, pp. 31-36 vol.1.
[61] B.-H. Bae, S.-K. Sul, J.-H. Kwon, and J.-S. Byeon, "Implementation of sensorless vector control for super-high-speed PMSM of turbo-compressor," IEEE Trans. Ind. Appl., vol. 39, pp. 811-818, 2003.
[62] J.-S. Yim, "Control of High-Speed ac Motor with Limited Sampling Frequency," Thesis, Seoul National University, Seoul, 2009.
[63] J.-S. Yim, W.-J. Lee, S.-K. Sul, H.-S. Yang, and J.-T. Kim, "Sensorless vector control of super high speed turbo compressor," in Applied Power Electronics Conference and Exposition, 2005. APEC 2005. Twentieth Annual IEEE, 2005, pp. 950-953 Vol. 2.
139
[64] J. Holtz, G. d. Cunha, N. Petry, and P. J. Torri, "Control of Large Salient-Pole Synchronous Machines Using Synchronous Optimal Pulsewidth Modulation," IEEE Trans. Ind. Electron., vol. 62, pp. 3372-3379, 2015.
[65] C. Zwyssig, S. D. Round, and J. W. Kolar, "An Ultrahigh-Speed, Low Power Electrical Drive System," IEEE Trans. Ind. Electron., vol. 55, pp. 577-585, 2008.
[66] J.-S. Yim, S.-K. Sul, B.-H. Bae, N. R. Patel, and S. Hiti, "Modified Current Control Schemes for High-Performance Permanent-Magnet AC Drives With Low Sampling to Operating Frequency Ratio," IEEE Trans. Ind. Appl., vol. 45, pp. 763-771, 2009.
140