hyper threadingtechnology

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INTRODUCTION

Hyper-threading or Hyper-Threading Technology(HTT), is actually Intels

trademark for their multi-threading, but has become a common name for all

processors of this type. It is essentially a cut down ersion of dual ersion of dual

core. !"ecution units on a hyper-threaded #$% share certain elements, such as cache

and pipelines.

The operating system sees a single hyper-threaded processor as two separate

logical #$%s. Threads can be scheduled to e"ecute on any of these logicalprocessors. The main strength of hyper-threading is that it allows for fle"ible

scheduling of all aailable e"ecution slots, which increases efficiency by keeping the

e"ecution core as busy as possible. &ll that is re'uired to take adantage of this

technology is symmetric multiprocessing support in the operating system .Hyper-

threaded processors still share the same cache it is possible for applications

performance to actually degrade if both threads are contending for the #$% cache at

the same time.

icroprocessor designers mainly gie emphasis to two main factors-*$!!+

and $&&!I* in their 'uest towards efficiency. otion of thread and process

are used by computer programmers and hardware designers in arying conte"ts.

/arious operating systems and architecture gie different definitions to them. &

process is a program in e"ecution which has a memory associated with it and a

thread is an actual running component of a process, a process can be a multi-

threaded.

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$arallelism- initial microprocessors in the 01"02 series supported one

instruction at a time. &lso, the pre-dominant operating system during those days 3

* +4* 3 supported only one process at a time. $entium and $entium 3$ro series

had increased number of e"ecution cores. Their super-scalar architecture and

pipelining resulted in a certain degree of parallelism. 5ut no processor had the

capability to e"ecute two instructions from different threads simultaneously.

Intel Hyper-Threading technology allows multithreaded operating systems to

iew a single physical processor as if it were two logical processors. & processor that

in cooperates this technology shares #$% resources among multiple threads, thereby

enabling faster enterprise-serer response times and proiding additional #$%processing power to handle larger workloads. &s a result serer performance can

improe.

The ama6ing growth of the internet and telecommunications is powered by

eer-faster systems demanding increasingly higher leels of processor performance.

To keep up with this demand we cannot rely entirely on traditional approaches to

processor design. icroarchitecture techni'ues used to achiee past processor

performance improement 3super-pipelining, branch prediction, super scalar

e"ecution, out-of order e"ecution, caches-hae made microprocessors increasingly

more comple", hae more transistor counts and power are increasing at rates greater

than processor performance. $rocessor architects are therefore looking foe ways to

improe performance at a greater rate than transistor counts and power dissipation.

Hyper-Threading Technology is form of simultaneously multithreading

technology(*T) introduced by intel. &rchitecturally, a processor with Hyper-

Threading Technology consist of two logical processors, each of which has its own

processor architectural state. &fter power-up and initiali6ation, each logical

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processor can be indiidually halted, interrupted or directed to e"ecute a specified

thread, independently from the other logical processor on the chip. %nlike a

traditional dual processor(+$) configuration that uses two separated physical

processors, the logical processors in a processor with Hyper-Threading

Technology share the e"ecution resources of the processor core. These resources

include the e"ecution engine, the caches, the system-bus interface and the firmware

Hyper-Threading Technology represents a new approach to improing the

instruction throughput of processors that are targeted for serers, high performance

workstations and desktops . It also proides a iew into the future of microprocessor

design where the performance of a processor when e"ecuting a specific type of

application or the space and power re'uirements of a physical processor within a

serer may be as important as its raw processing speed.

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Hyper-Threading Technology is feasible for platforms ranging from mobile

processors to serers. Its introduction into market segments other than serers is

gated only by the aailability and prealence of threaded applications and workloads

in these markets.

&lthough e"isting operating systems and application codes will run correctly

on a processor with Hyper-Threading Technology, some relatiely simple code

practices are recommended to get the optimum benefit from Hyper-Threading

Technology.

Hyper-Threading Technology does not delier multiprocessor scaling,Typically applications make use of about 789 of the internal processor e"ecution

resources. The ideas behind Hyper-Threading Technology is to enable better

processor usage and to achiee about 81 percent utili6ation of resources.

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ARCHITECTURE OF PROCESSOR WITH HYPER-THREADING TECHNOLOGY

& $rocessor with Hyper-Threading Technology may proide a performance

gain of 71 percent when e"ecuting multi-threaded operating system and applicationcode oer that of a comparable Intel architecture processor without Hyper-Threading

Technology. :hen placed in a multiprocessor based system, the increase in

computing power generally scales linearly as the number of physical processors in a

system is increased although as in any multiprocessor system, the scalability of

performance is highly dependent on the nature of the application.

Two logical processors do not proide the same leel of performance as a dual

processor-based system.

!ach logical processor has;-

Its own architecture state.

!"ecutes its own code stream concurrently.

#an be interred and halted independently.

Two logical processors share the same

!"ecution engine and catches, and


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Why Hyper threading

!en with the optimised pipelining architecture and increased number of

e"ecution units aailable with modern microprocessors like $entium and athlon,only

one-third of the resources were being used at a time. This is because of the inability

of the processor to e"ecute more than one thread at a time. !en after applying the

intricacies of out of order !"ecution and adanced branch prediction logic,

instruction from a single thread are far below the ma"imum utilisation potential of a

processor resulting in wastage of resources.

Sing!e Threaded CPU

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In this figure-The processor has seen e"ecution paths in the e"ecution core.

ed colour indicates e"ecuting threads and white spaces are blank slots. $rocessor

uses =ust one-third of its aailable potential.

S"perthreading

&n alternatie mechanism called *uper threading, implemented in some

microprocessors proided some capability to e"ecute multiple threads at a time.

5ut it also had its limitations. &ll instructions in one pipeline stage of a

superthreaded processor hae to be from the same thread. *uperthreading inoled

limited amount of conte"t switching too. This technology also didnt eliminate the

wastage of resources completely.S"per threaded CPU

The ed and >ellow colours indicate e"ecuting threads. !ach of the si" pipeline

stages has one thread.

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#"!tipr$%e&&$r &y&te'&

%sing more than one processor in a system directly proided thread

leel parallelism. 5ut this was a costly solution and re'uired special on

board support for multiple processors. These systems also re'uired some

type of synchronising mechanism so that both processors function in

unison. The oerhead for this synchroni6ation and the fre'uent collision

for the need of resources slowed down such implementation considerably.

+ue to these reasons, multiprocessor systems remain confined to special

purpose implementations and dedicated systems. Hyperthreading,

introduced by Intel proided the solution for this problem.

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What i& Hyper Threading

Hyperthreding is super threading without the restriction that each pipeline

stage or clock cycle must contain instructions from the same thread. /acant

e"ecution slots in each pipeline stage is filled by instructions from another thread

,enabling thread leel parallelism. This can be done as long as there is no collision of

resources re'uired by two threads.

In&ide the pr$%e&&$r

*ince more than one thread is being run at the same time, certain architectural

features are replicated, some are shared and some are partitioned. The replicated

resources are instructions pointer ,return stack pointer etc...#aches and e"ecution

units are shared. $artitioned resources include scheduling 'ueues, load-store and

reorder buffers. &nother subtle feature is that when only one thread is e"ecuting, all

shared and partitioned resources are combined to gie ma"imum throughput. These

additional resources in a hyper threaded $entium ? or @enon processors increased

the processor die area by =ust fie percent. Hyperthreadings strength is that it allows

the scheduling logic ma"imum fle"ibility to fill the e"ecution slots, thereby making

more efficient use of aailable e"ecution resources by keeping the e"ecution core

busier.

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Fr$' Operating Sy&te'(& )ie*

:hen iewed from 4* or user leel, the hyper threaded processor is split up

into two or more logical processors and threads can be scheduled to e"ecute on any

of the two logical processors and threads can be scheduled to e"ecute on any of the

two logical processors as they are free.

4perating system schedules the threads appro"imately into the aailable

logical processors. *cheduling is done in such a way that two running threads wont

re'uest for a resources simultaneously as far as possible. It is a must that operatingsystem support hyper threading. $resently the number of logical processors

supported by most operating systems and underlying hardware is two. atest

operating systems like :indows @$ and ed Hat inu" A support hyper threading.

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#"!tithreading and #e&&age-pa&&ing App!i%ati$n&

In general, processors enabled with Hyper-Threading technology can improe the

performance of applications with high degree of parallelism. $reious studies hae

shown that the Hyper-Threading technology improes multi-threaded applications

performance by the range of B1 to 71 percentages depending on the characteristics of

the applications. These studies also suggest that the potential gain is only obtained if

the application is multi-threaded by any means of paralleli6ation techni'ues. &

multithreading program is capable of creating multiple processes, or threads, at a

time without haing to hae multiple copies of the program running in the computer.

:ith the addition of Hyper-Threading support in inu" kernels C.?.A-7B and aboe,

inu" cluster practitioners hae started to assess its performance impact on their

applications. In our area of interest, high performance computing (H$#) clusters,

applications are commonly implemented by using standard message-passing

Per+$'an%eHyperthreading technology improes oerall performance in two ways,


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HYPER-THREADING TECHNOLOGY ARCHITECTURE

Hyper-threading technology makes a single physical processor appear as multiple

logical processors. To do this, there is one copy of the architecture state for each

logical processor, and the logical processors share a single set of physical e"ecution

resources.


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ultiprocessor system with two physical processors that are not Hyper-

Threading capable, but multiprocessor system with two physical processors that are

Hyper-Threading Technology-capable. :ith two copies of the architectural state on

each physical processor ,the system appears to hae four logical processors.

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The hyperthreading technology implementation on the etburst

microarchitecture has two logical processors on each physical processor.

!ach logical processor maintains a complete sat of the architectural state. The

architectural state consists of registers, including general purpose registers, and those

for control, the adanced programmable interrupt controller (&$I#), and some for

machine state.


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DIFFERENCE ,ETWEEN HYPERTHREADING AND #ULTITHREADING

Hyper-Threading Technology uses the process- and thread-leel parallelism

found in contemporary operating systems and high-performance applications by

implementing two logical processors on a single chip. This configuration allows a

thread to be e"ecuted on each logical processor. Instructions from both threads are

simultaneously dispatched for e"ecution by the processor core. The processor core

e"ecutes these two threads concurrently, using out-of-order instruction scheduling to

keep as many of its e"ecution units as possible busy during each clock cycle.

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I#PLE#ENTATION O+ HYPER THREADING TECHNOLOGY

The first implementation of Hyper-Threading Technology is being made

aailable on intel @enon processor family for dual and multiprocessor serers, with

two logical processors per physical processor. 5y more efficiently using e"iting

processor resources resources, the intel @enon processor family can significantly

improe performance at irtually the same system cost. This implementation of

Hyper-Threading Technology added lees than 89 to the relatie chip si6e and

ma"imum power re'uirements, but can proide performance benefits much greater

than that.

!ach logical processor maintains a complete set of the architecture state. The

architecture state consists of registers including the general-purpose registers, the

control registers, the adanced programmable interrupt controller (&$I#) registers,

and some machine state registers.


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SOFTWARE ON A HYPERTHREADED PROCESSOR

Toget full adantage out of hyper threaded processor, an application must not

only be multithreaded, but the indiidual threads must be coded in such a way that

they should not raise the re'uest for one resource simultaneously.


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Thread& +r$' di++erent pr$%e&&e&

It is not possible to write optimised hyperthreaded code considering the other

applications that will be running on the system. $rogrammer of one application will

be obliious to the internals and resources re'uirements of another application. &nd

in normal case,it will be difficult to anticipate the applications running in tandem.


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Operating &y&te' and app!i%ati$n&.

& system with processors that use Hyper-Threading Technology appears to

the 4perating *ystem and applicaton software as haing twice the number of

processors than it physically has operating systems manage logical processors as

they do physical processors, scheduling runnable tasks or threads to logical

processors. Howeer, for best performance,the operating system should implement

two optimi6ations.

The first is to use the H&T instruction if one logical processor is actie and

the other is not. H&T will allow the processor to transition to either the *T4- or

*TB-mode. &n operating system that does not use this optimi6ation would e"ecute

on the idle logical processor a se'uence of instruction that repeatedly checks for

work to do. This so-called Didle loopE can consume significant e"ecution resources

that could otherwise be used to make faster progress on the other actie logical

processor.

The second optimi6ation is in scheduling software threads to logical

processors. In general, for best performance, the operating system should schedule

threads to logical processors on different physical processors before scheduling

multiple threads to the same physical processor. This optimi6ation allows software

threads to use different physical e"ecution resources when possible.

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C$n%!"&i$n

Intels Hyper 3Threading Technology brings the concept of simultaneous

multi-threading to the Intel &rchitecture. This is a significant new technology

direction for Intels


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Re+eren%e&

B Tau eng, $h.+. , DIntel Hyperthreading technology to &chiee #omputational

!fficiency E, oember C117.

C 4nur #elebioglu , DIntel Hyperthreading technology to &chiee #omputational

!fficiencyE , oember C117.

7 i6wan &li, DIntel Hyperthreading technology to &chiee #omputational !fficiency E,

oember C117.

? Jenwei Hsieh, $h.+. , DIntel Hyperthreading technology to &chiee #omputational

!fficiencyE , oember C117.

8 Tau eng, i6wan &li, Jenwei Hsieh, /ictor ashayekhi, e6a ooholamini , D &n

!mpirical *tudy of Hyper-Threading in High $erformance #omputing #lusters E, +ell

#omputer #orp, ay C1BC.

2 +ecipher Information *ystems ,EHyper-threaded and +ual-#ore #$% Technology

E,June C112 .

F Intel, DIntelK Hyper-Threading Technology E,ay C1BC.

0 Intel, DIntel Hyper-Threading Technology -Technical %sers Luide E, January C117.

A +eborah T. arr, +esktop $roducts Lroup, Intel #orp, DHyper-Threading Technology&rchitecture and icroarchitecture E January C11C.

B1 in #hao, DIntel Technology Journal E,

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