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100 Hz Chassis Service Manual

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CONTENTS

Technical Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Recommendation for service repairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Component description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Specifications of the connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7General Inf›rmation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Component Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

- CCU3000, CCU3000-I, CCU3001, CCU3001-I (Micro Controller) . . . . . . . . . . . . . . .18- M27C2001 (2 Megabit (256 kx8) UV EPROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24- TL7702A, TL7705A, TL7709A, TL7712A, TL7715A (Supply-Voltage Supervisors) . .27- TPU3035, TPU3040, TPU3050 (Teletext Processor) . . . . . . . . . . . . . . . . . . . . . . . .29- K6T4008C1B Family (K6E0808V1E) (512Kx8 bit Low Power CMOS Static RAM) . . .34- AS7C1024, AS7C31024 (5V/3.3V 128Kx8 CMOS SRAM) . . . . . . . . . . . . . . . . . . . .38- A42L2604 Series (Preliminary 4M X 4 CMOS Dynamic Ram With Edo Page Mode) .42- ST24C16, ST25C16 (Serial 16K (2Kx8) EEPROM) . . . . . . . . . . . . . . . . . . . . . . . . .46- TDA4470B (Multistandard Video-If and Quasi Parallel Sand Processing) . . . . . . . . .48- MSP34x1G (Multistandart Sound Processor (Virtual Dolby) . . . . . . . . . . . . . . . . . . .52- TDA6920 (Scart Switch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60- TDA7264, TDA7264A (25+25W Stereo Amplifier with Mute/St-By) . . . . . . . . . . . . . .65- TDA7050 (Low voltage mono/stereo power amplifier) . . . . . . . . . . . . . . . . . . . . . . . .68- SDA9488X, SDA9588X (PTP Processor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71- VPC323XD (Multi standard Video Decoder) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74- MSM54V12222A (OKI Semiconductor, 262,214 Words x 12 bits FIELD MEMORY) .86- DDP3310B (Digital Deflection and RGB Processor) . . . . . . . . . . . . . . . . . . . . . . . . .89- TDA6111Q (Video Output Amplifier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91- TDA16846 (Controller For Switch Mode Power Supplies) . . . . . . . . . . . . . . . . . . . . .94- TCDT1100(G) Series (Optocoupler with Phototransistor Output) . . . . . . . . . . . . . . . .98- L4931 Series (BA033T) (Very Low Drop Voltage Regulators With Inhibit) . . . . . . . .100- L7800 Series (Positive Voltage Regulators) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102- STV9379A (Vertical Deflection Booster) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108- M54HCT86, M74HCT86 (Quad Exclusive or Gate) . . . . . . . . . . . . . . . . . . . . . . . . .112- BU4525AX (Silicon Diffused Power Transistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . .114- BD533/5/7, BD534/6/8 (Complementary Silicon Power Transistors) . . . . . . . . . . . .118- BDX53B, BDX54B, BDX53C, BDX54C (Complementary Silicon Power Darlington Transistors) . . . . . . . . . . . . . . . . . . . . . . .120- SPP07N60C2, SPB07N60* (Cool MOS Power Transistor) . . . . . . . . . . . . . . . . . . .122- TL431 (Programmable Voltage Reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124- BY229 Series (Rectifier diodes fast, soft recovery) . . . . . . . . . . . . . . . . . . . . . . . . .125- TSOP52 (Photo Module for High Data Rates PMC Remote Control Systems) . . . . .126- BYW72-76 (Fast Silicon Mesa Rectifiers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128


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CHASSIS Consept MICRONASTuner PLL

PICTURE Picture tube diagonal / Deflection28”-33”/110”

28”-32”106” (16:9)Format 33”/ 4:3

28”-32”/16:9

FEATURES TV-Standards PAL BG

PAL I

PAL DK

PALI / Secam BG

PALI / Secam BG + DK

PAL / Secam BG + LL’

NTSC 4.43MHz Playback

NTSC 3.58MHz Playback

Stereo systems A2 / Nicam / A2+Nicam

Channelcoverage VHF / UHF

CATV / Hyperband (S1-S41)

No. of Programmes 99+2 (3) AV + CHINCH + VGAOn-screen display (OSD) User Friendly Menu

Menu appereance 3D and full-background

Remote control operation (OSD)

On-set Programme and Volume controls

Teletext Fast

Flof text

Number Of Teletext Pages 26



SOFTWARE Intelligent program keys

Intelligent Auto Shut Off

Text capability in OSD Languages

Fine-tuning

Sleep timer (between 0-120 min. With 15 min.step)

Auto shut-off

Auto Programming

EPG

Clock

Numerical lock

Program naming (max. 7 Chr.)

Menu commands in 8 languages

Audio Volume Limiting -AVL

IPQ LFI

Running Four favorite Programs

Motion Estimation

Noise reduction

Comb Filter

scan Velocity

TECHNICAL DATA SHEET


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Freeze

PIS

SIP

Slow Motion

4:1:1/4:2:2

Twlve Folde Mode

Zoom

CTI

Real PIP

SOUND Stereo

Sound selection

Virtual Dolby

DBE

5 band Equalizer

Audio output RMS 28”-33”Stereo 2*8W(10%THD)Subwoofer

3D Sound / Panoramic Sound

Bass/Treble/Balance

Spatial Stereo

Sound effect

POWER SUPPLY Operating Voltage (165-265 Vac / 50 Hz)

Operating Voltage (90-270 Vac / 50 Hz)

Power consumption 28” Dolby Prologic 150W28” 130W Stereo

Standby power consumption <2W

CONNECTIONS Antenna input (75 ohm IEC ) IEuro-AV Scart 1 (RGB + AV)

Euro-AV Scart 2 (RGB + AV)

Third Euro-AV (AV only)

Front AV (IN only)

VGA

Headphone

ACCESSORIES Remote control unit (Full function)

Instruction manual

Circuit diagram

: Standart : optional.


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1- Use only original spare parts. Only use compo-nents with the same specifications for replace-ment.

2- Original fuse value only should be used.3- Main leads and connecting leads should be chec-

ked for external damage before connection. Check the insulation.

4- Parts contributing to the safety of the product mustnot be damaged or obviously unsuitable. This is valid especially for insulators and insulatingparts.

5- Thermally loaded solder pads are to be sucked offand re-soldered.

6- Ensure that the ventilation slots are not obstruc-ted.

7- Potentials as high as 31 KV are present when thisreceiver is operating. Operation of the receiveroutside the cabinet or with back cover removed in-volve a shock hazard from the receiver.Servicing should not be attempted by anyone whois not thoroughly familiar with the precautions ne-cessary when working on high voltage equipment.Perfectly discharge the high potential of the pictu-re tube before handling the tube. The picture tubeis highly evacuated and if broken.Glass fragments will be violently expelled.Always discharge the picture tube anode to the re-ceiver chassis to keep of the shock hazard beforeremoving the anode cap.

8- Keep wire away from the high voltage or high tem-

perature components.

9- When replacing a wattage resistor in circuit board,keep the resistor 10 mm away from circuit board.

10) Discharging of the picture tube is effected only bythe connection point of the aquadaq coating thepicture tube.

11) When carrying out repairing process at control unitdo not approach too near to the picture tube inorder to avoid any charge transfer.

12) Measurements within the primary circuit of theswitched mode power supply are allowed to becarried out only when using potential-free measur-ing equipment. Voltages indicated for this circuitare based on mains voltage reference level.

13) The defined local radiation dosage according tothe x-ray radiation regulation is given by the spe-cific type of the picture tube and the maximum per-missible EHT voltage. The EHT voltage must notexceed the maximum value of 31kv.

14) When the repair process is carried out 12 V linevoltage should not be interrupted because videooutput stage is endangered by the interruption of12 V line voltage.

MOS circuit requires special attention with regard tostatic charges. Static charges may occur with anyhighly insulating plastics and can be transferred topersons wearing clothes and shoes made of syntheticmaterials. Protective circuits on the inputs and outputsof mos circuits give protection to a limited extend onlydue to time of reaction.Please observe the following instructions to protectthe components against damage from static charges.1- Keep mos components in conductive package until

they are used. Most components must never be

stored in styropor materials or plastic magazines.2- Persons have to rid themselves of electrostatic

charges by touching MOS components.3- Hold the component by the body touching the ter-

minals.4- Use only grounded instruments for testing and pro-

cessing purposes.5- Remove or connect MOS ICs when operating vol-

tage is disconnected.

RECOMMENDATION FOR SERVICE REPAIRS

HANDLING OF MOS CHIP COMPONENTS


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1- Excessive high voltage can be produce potentiallyhazardous X-RAY radiation. To avoid such hazard,the high voltage must not be above the specified li-mit. The value of the high voltage of this receiver is30KV at zero beam current (minimum brightness)under 220V AC power source. The high voltagemust not under any circumstance, exceed 31.5KV.It is recommended the reading of the high voltagebe recorded as a part of the service record. It is im-

portant to use an accurate and reliable high voltagemeter.

2- The primary source of X-RAY radiation in this TVreceiver is the picture tube. For continued X-RAYradiation protection, the replacement tube must beexactly the same type tube as specified in the partlist.

1) SMD Components (Surface MountedDevice)

Desoldering:Heat up the component from its terminals for 2 or 3

seconds with a soldering iron and afterwards take outthe component carefully by means of the tweezers.Remove superfluous solder at the solder surfaces ofthe components place at pcb by means of desolderingstrand or suction de-solder equipment. Never forcethe component for removing without heating the termi-nals sufficiently. Unsoldered components should notbe used for once more.

Soldering: Place the component properly to its position by meansof tweezers and solder one side of the component.Then check out the position of the component and besure if it is soldered to the right place and then solderother side of the component. Terminals of the SMDcomponents must not contact directly to the solderingiron.

2)PLCC Components

Desoldering: Heat up the terminals of PLCC component for 3 or 5seconds by means of SMD soldering iron and PLCCdesoldering pair (angle 900C, Leg: 24mm). Take outPLCC component carefully by slightly turning of desol-dering tweezers.

Soldering: Remove superfluous solder at the solder surfaces ofthe components placed on pcb by means of de-solde-ring iron or suction de-solder equipment. Apply fluxwith low grease content. Place PLCC device on thesoldering surface and take care for its correct place-ment. Secure diagonally by means of two solderingjoints. Apply soldering paste along PLCC pins. Shortcircuits which may occure during soldering processhave to be removed immediately with a soldering iron.

X-RAY RADIATION PRECAUTION

SOLDERING PROCESS


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CO

MP

ON

EN

T D

ES

CR

IPTI

ON

SPOWER CORD

SAW FILTER

IR SENSOR

VOLTAGE REGULATOR

ON/OFF SWITCH

HEADPHONE

RELAY

LINE FILTER

PTC

NPN TRANSISTOR

PNP TRANSISTOR

CERAMIC FILTER

COIL

LINEARITY COIL

FUSIBLE RESISTOR

CERAMIC CAPACITOR /POLYESTER CAPACITOR

ELECTROLYTIC CAPACITOR

DIODE

ZENER DIODE

SWITCH JUMPER

NET (INPUT)

NET (OUTPUT)

TACT SWITCH

IW METAL OXIDE RESISTOR

1/2W METAL OXIDE RESISTOR

1/4 OR 1/6W CARBON FILM RESISTOR


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I- Audio output 1. right channel 0.5 VRMS/<1 k 0

2- Audio input 1. right channel 0.5 VRMS (connected to No.6)3- Audio output 2. left channel 0.5 VRMS (connected to No.1)4- GND (audio)5- GND6- Audio input 2. left channel 0.5 VRMS/>10k 07- RGB input, blue (B)8- Switch signal video (status)9- GND

10- Reserved for clock signals (not connected)11- RGB input, green (G)12- Reserved for remote control (not connected)13- GND14- GND switch signal RGB15- RGB input, red (R)16- Switch signal RGB17- GND (video)18- GND19- Video output 1 Vpp/75 ohm20- Video input 1 Vpp/75 ohm21- Shield

SPECIFICATIONS OF THE CONNECTOR(EURO SCART)

20 18 16 14 12 10 8 6 4 2

21 19 17 15 13 11 9 7 5 3 1


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The PT100 chassis consist of 4 important module asUP, F.Box, CRT, Power board and main board.Description of the boards.

UP Board:The board consist of fallowing IC a)IM01, CCU300. b)IM05, TPU3050.c)IM02, 27C2001 d)IM07 this ICdepends on the number of Teletext pages. e)IM09, 24C16CCU300 is controller IC. The CPU core is fully compatible with the 65C02 micro-processor. However, not all the pins of the 65C02 proces-sor are accessible for the user outside the chip. Oneswitch in the control register allows the CPU to beswitched off, so that an external processor can take overs tasks. This external processor can of course also be anin-circuit emulator.This IC has 5 MHz clock frequency and derived via XM01quartz.. This IC is rhomless and all the S/W programsloaded to IM02 at the factory during production.Please care some important pins of the CCU:Pin 6 is reset, Pin 60 and 14 are IR inputs, pin42 and 43are SDA and SCL . Pin 52, 53, 45 and 46 controls theScart 1 and Scart 2 active or connected device is 4/3 or16/9IM09 is eeprom and stored all the channel, program,brightness, contrast values and service values. The S/W

intelligent that can understand that when you replace thenew IC and load the eeprom most important data’s forthe IIC controlled IC in the chassis.IM 05 is an intelligent Teletext decoder and processor thatthe pages data’s stored in IM07.Type of IM07 depends on the requested Teletext pages. Ifthis IC 32X8 ram makes about 26 pages, if it is 128X8SRAM makes about 126 pages, 4X1 Dram makes 512pages so on.IM03 is general reset that some IC in this TV need activelove and some of them need active high, this IC triggeredafter power on via CCU300..

F.Box.There are mainly 2 type of F.Box in the PT100 chassisthat as I explained order lines.Idea F.Box.Idea, has three main IC that VPC3230, MSM54V2222 andDDP3310BVPC is main video decoder and ADC for video processor,please check the data sheets.All the syncron, colour decoding, digitising made by VPCIC. Output of the IC has 4 bit luminance and 1 bit blueand 1 bit red digitalis. This Digital colour informationfeeds the MSM54V12222 FRAM IC ( FRAM means Fieldrandom acces memory).

AnalogFront-end

AGC2xADC

AnalogComponentFront-end

4xADC

ProcessingMatrix

ContrastSaturationBrightness

Tint

I2C Bus Sync+

ClockGenerationClock

Gen.

AdaptiveCombFilter

NTSCPAL

ColorDecoder

NTSCPAL

SECAMSaturation

Tint

Mixer

2D ScalerPIP

PanoramaMode

ContrastBrightness

Peaking

OutputFormatter

ITU-R 656ITU-R 601

MemoryControl

CIN

VIN1

VIN2

VIN3

VIN4

VOUT

Y/G

U/B

V/R

FB

Y/G

U/B

V/R

FB

20.25 MHz I2C Bus

RGB/YCrCb

RGB/YCrCb

FB

Y

Cr

Cb

Y

Cr

Cb

Y OUT

CrCbOUT

YCOE

FIFOCNTL

LL Clock

H Sync

V Sync

AV0

GENERAL INFORMATION ABOUT PT100 CHASSIS


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MSM54V2222 works as field memory and scan rate converter that, VPC support 50 Hz digital video information to FRAMand DDP gets and progress this signals twice so it makes 100 Hz digitised signals output of the FRAM. This FRAM has noIICBUS controlled it is slave.

DDP3310B: DDP3310B works as an back and IC for PT100 chassis digitised and scan rated output of the FRAM feeds the DDP3310Bdigital input as 4:1:1 video colour format.Line lock Clock signals feeds by the VPC. For general synchronisation from vertical and horizontal pulses feed the verticaland horizontal syncs input of the DDP3310B.The OSD information that derived from the TPU3050 feeds the RGB inputs of the DDP3310B. It means that output of theTeletext IC is 100 Hz formats.All the geometry, colour, CRT adjustment and frequency doubling controls made by DDP3310B.

SDA9400:Also roughly SDA9400 is scanrate converter but in 4:2:2 formats and has Fallowing improvement features.Noise reduction, LAFR, 3D motion estimation, zoom etc.4:2:2 luminance and chrominance parallel (2 x 8 wires)ITU-R 656 data format (8 wires)Digital vertical compression of the input signal (1.0, 1.25, 1.5, 1.75, 2.0, 3.0, 4.0)Motion adaptive spatial and temporal noise reduction (3D-NR)Temporal noise reduction for luminance frame based or field based.Temporal noise reduction for chrominance field basedSeparate motion detectors for luminance and chrominance.High performance motion detector for scan rate conversion5 Mbit embedded DRAM core for field memories.

Hori-zontalScaler

Y FeaturesC Features

DigitalRGB

Matrix

3 x DAC(10 Bit)

Tube-Control

AnalogRGB

Switch

ScanVelocity

Modulation

DACs

DisplayFrequencyDoubling

H / VDeflectionSecurity

Unit

PictureFrame

Generator

ClockGen.

I2CInter-face

PWMMeasure-

mentADC

YCrCb4:2:2/4:1:1

Line-LockedClock27/32 MHz

SDA/SCL

PWM1 & 2

SenseInput

2H / 2V(1H/1V)

HFlyback

RGBOut

2xRGB/FBIn

SVM

H DriveV & E/W

FIFOControlling


10

CRT:The CRT board has three TDA6111 IC that the IC’has fal-lowing features:The TDA6111Q is a video output amplifier with 16MHzbandwidth. The device is contained in a single in-line 9-pin medium power (DBS9MPF) package, using high-volt-age DMOS technology, intended to drive the cathode of acolour CRT.

Power board:This TV set has two SMPS that we are talking about thestand by SMPS now. This SMPS works as an oscillator that works about 50kHz. Depends on the loads frequency will be shift up andtown. During the Standby mode there no voltage at themain SMPS, if the user send the on information via RCunit or using keyboard, the relay on the board (rel1) willbe on position and main SMPS will get their voltage viarelay REL1.

ADJUSTMENT OF THE SCHASSIS.Pre information about the chassis.

1: SYS Voltage.It is 140 V for all the picture size and the formats. Andadjusted via RP16 on the Cathode diode DP07.

2: AGC adjustment

a) Remove the antenna signal and check the voltage onCT05 just beside the tuner.b) Decrease the voltage 0.4v less then item a.

3: G2 adjustment:a) Adjust the TV set to the colour bar test pattern.b) Go to the service mode by pressing the volume- buttonon the keyboard and time button on the RC unit at thesame time.c) Go to the G2 Adjustment section by pressing continu-ously via RC .d) Adjust the voltage on the screen that R or G or B about25.

4: Geometry Adjustment.a) Horizontal Position: Shits the picture horizontal andvertical direction.b) Horizontal With: For adjust the horizontal amplitude.c) Cushion: To adjust the pincushion distortion this adjust-ment is used.d) Trapeze: To correct Trapeze distortion.e) Angle: Complete rotate the picture.f) Bow. It is bow the picture left and right direction.g) Upper corner: It is correct only the top or bottom pincushion distortion.h) For upper corner adjustment please use Volume leftand right; for bottom corners please use 19/9 and AV

HINVIN

SYNCEN

YIN

UVIN

RESET

ISCInput synccontroller

OSCOutput synccontroller

OFCoutputformat

conversion

PLL2Clock

doubling

HDRScan rate

conversion

Verticalinterpolation

LMLine Memory

LDRVertical,

Horizontaldecimation

NoiseReduction andmeasurement

Motiondetector

Movie modeand phasedetection

IFCInput

formatconversion

I2CI2C Bus

InterfaceLM

Line Memory

PLL1Clock doubling

MCMemory Controller

EDeDRAM

Interfaces

Data buffer

Voltage control

Test controller

SDA SCL CLK1 X1/CLK2 X2

VOUT/VEXTHOUT/VEXTHREFINTERLACED

YOUT

UVOUT

CLKOUT


11

buttons.i) Vertical position: It is shift the picture up and downdirections.j) Vertical amplitude: To adjust the vertical amplitude.k) Vertical S Correction: Via Volume – button decreasemiddle of the picture and increase the upper and downamplitude; you can make just opposite this progress ViaVolume + button.l) Vertical Symmetry: Via volume + decrease the up sideof the picture, via volume –increase the bottom side of thepicture.m) 4/3(16/9 vert amplitude) For adjusting 16/9 picture sizefor 4/3 TV set.n) 4/3(16/9 vert cushion) For adjusting 16/9 picture cush-ion distortion.o) 4/3 (16/9 TV upper corner) For adjusting 16/9 pictureupper corner cushion distortion via volume – and volume+ button.p) 4/3 (16/9 TV lower corner) For adjusting 16/9 picturelower corner cushion distortion via 16/9 and AV buttonson the RC handset.q) 4/3 TV waterglass Cus : Only, valid for waterglass pincushion adjustment.r) 4/3 TV Cinema Cush. : Valid only for Cinema mod, foradjust the pin cushion.s) 4/3 TV Subtitle cush : valid only for subtitle mod and foradjust the pin cushion.t) 4/3 TV Cinema Hor: Valid for cinema mod , adjust thehorizontal amplitude for cinema mode.

H/W 16/9 Bit:If this bit 0 it is mean that this TV set for 4/3 TV.If this bit 1 it is mean that this TV set for 16/9 TV.

DVD Bit:If this bit 0 ; means TV set without DVD Equipped.If this bit 1 ; means TV set with DVD Equipped and Scart2 without RGB mode.

Welcome Bit:After this bit set 1; The TV set will open with welcomemenu.

Eeprom Init: If this bit made 1, and turn off and on again the TV set, Allthe eeprom value will be erased and factory values willloaded.It means: Language will English, all geometry adjustmentwill be optimum values and all the analog values will beoptimum values.

Tuner selectionIf this bit is 0 Orega tuner is selected.If this bit is 1 Temic tuner is selected.

If this bit is 2 Philips tuner is selected.If this bit is 3 Alps tuner is selected.

Top / FlofIf this Bit 0 TOP and FLOF text are not supported.If this Bit 1 TOP supported and FLOF does not supported.If this Bit 2 TOP not supported but FLOF text is support-ed.If this Bit 3 both TOP and FLOF text are supported.

Test patternThis mode normally 0 for TV mode , when you changethis bit 1,2 ,3,4,5,6 you will see the some coloured andblack and white patterns on the screen. This is only forservice and to understand where is the problem comingfrom.

4H Without IR.If this bit 1, the TV set will automatically will turn of after 4hours if there are no valid IR signal.It means that TV set will think that no body is not controlit.

Peripheral workingThis TV set normally has 2 Scart and the third one isoption by service mode.The third scart only AV in and output. AV3 doesn’supportRGB.The second Scart Has no FB pin you can sellect RGBmode via RC hendset.The Side AV inputs parallel to the AV2 .S-VHS parallel to the Scart 1


12

ENCORE F BOX


13

IDEA F BOX


14

MAIN

FF BB

ooxx WW

iitthh--WW

iihhttoo

uutt PP

IIPP

BBDD

224411

BBDD

224422

SSTT

AANN

DDBB

YYPP

OOWW

EERR


15

MICOPROCESSOR


16


17

COMPONENT DESCRIPTIONS- CCU3000, CCU3000-I, CCU3001, CCU3001-I

- M27C2001

- TL7702A, TL7705A, TL7709A, TL7712A, TL7715A

- TPU3035, TPU3040, TPU3050

- K6T4008C1B Family (K6E0808V1E)

- AS7C1024, AS7C31024

- A42L2604 Series

- ST24C16, ST25C16

- TDA4470B

- MSP34x1G

- TDA6920

- TDA7264, TDA7264A

- TDA7050

- SDA9488X, SDA9588X

- VPC323XD

- MSM54V12222A

- DDP3310B

- TDA6111Q

- TDA16846

- TCDT1100(G) Series

- L4931 Series (BA033T)

- L7800 Series

- STV9379A

- M54HCT86, M74HCT86

- BU4525AX

- BD533/5/7, BD534/6/8

- BDX53B, BDX54B, BDX53C, BDX54C

- SPP07N60C2, SPB07N60*

- TL431

- BY229 Series

- TSOP52

- BYW72-76


SpecificationsOutline Dimensions

68-Pin Plastic Leaded Chip Carrier Package(PLCC68)Weight approximately 4.8 g Dimensions in mm

Pinning of the CCU 3000, CCU 3001 in PLCC68package

CCU 3000, CCU 3000-I, CCU 3001, CCU 3001-IMicro Controller

18


19

Pin Configuration

64 -Pin Plastic Shrink Dual Inline Package(PSDIP64)1

Weight approximately 9.0 gDimensions in mm

Pinning of the CCU 3000, CCU 3001 inPSDIP64 and PSDIP64F package

64 -Pin Plastic Shrink Dual Inline Package(PSDIP64F)2

Weight approximately 9.0 gDimensions in mm

1) PSDIP64 = Manufactured in Freiburg2) PSDIP64F = Second Source


20

Pin No. Con- I: Pin Name Short Descriptionnection Input

68–pin 64–pin O:PLCC SDIP Output

1 16 +5V I VSUP Supply Voltage2 15 GND I GND Ground3 14 Crystal I/O X2 Crystal connector 24 13 Crystal I X1 Crystal connector 15 12 +3V to I V Stand-by Standby Supply Voltage

+5V6 11 X I/O RES Reset input/Reset output7 10 DA I/O DAT-IM1 IM bus 1 data signal8 9 ID O ID-IM1 IM bus 1 ident signal output9 8 CL O CLK-IM1 IM bus 1 clock signal output10 – DA I/O DAT-IM2 IM bus 2 data signal11 – ID O ID-IM2 IM bus 2 ident signal output12 – CL O CLK-IM2 IM bus 2 clock signal output13 7 X I/O TIMER1 Timer 1 signal14 6 X I/O TIMER2 Timer 2 signal15 5 X I/O TIMER3 Timer 3 signal16 4 external I IR Infrared signal input

infraredreceiver

17 3 X I/O (O) P40 (R/W) Port 4 bit 0 (CPU read/write)18 2 X I/O P10 (D0) Port 1 bit 0 (CPU data bus bit 0)

(I/O)19 1 X I/O P11 (D1) Port 1 bit 1 (CPU data bus bit 1)







(I/O)26 58 X I/O (O) P20 (A0) Port 2 bit 0 (CPU address bus bit 0)27 57 X I/O (O) P21 (A1) Port 2 bit 1 (CPU address bus bit 1)28 56 X I/O (O) P22 (A2) Port 2 bit 2 (CPU address bus bit 2)29 55 X I/O (O) P23 (A3) Port 2 bit 3 (CPU address bus bit 3)30 54 X I/O (O) P24 (A4) Port 2 bit 4 (CPU address bus bit 4)31 53 X I/O (O) P25 (A5) Port 2 bit 5 (CPU address bus bit 5)32 52 X I/O (O) P26 (A6) Port 2 bit 6 (CPU address bus bit 6)

Pin Connections and Short DescriptionsDA = IM bus data line of external devicesID = IM bus ident line of external devicesCL = IM bus clock line of external devicesX = obligatory; connections depend on application


21

Pin No. Con- I: Pin Name Short Descriptionnection Input

68–pin 64–pin O:PLCC SDIP Output

33 51 X I/O (O) P27 (A7) Port 2 bit 7 (CPU address bus bit 7)34 50 X I/O (O) P30 (A8) Port 3 bit 0 (CPU address bus bit 8)35 49 X I/O (O) P31 (A9) Port 3 bit 1 (CPU address bus bit 9)36 48 X I/O (O) P32 (A10) Port 3 bit 2 (CPU address bus bit 10)37 47 X I/O (O) P33 (A11) Port 3 bit 3 (CPU address bus bit 11)38 46 X I/O (O) P34 (A12) Port 3 bit 4 (CPU address bus bit 12)39 45 X I/O (O) P35 (A13) Port 3 bit 5 (CPU address bus bit 13)40 44 X I/O (O) P36 (A14) Port 3 bit 6 (CPU address bus bit 14)41 43 X I/O (O) P37 (A15) Port 3 bit 7 (CPU address bus bit 15)42 42 X I/O (O) P50 (RD Port 1) Port 5 bit 0 (CCU read Port 1)43 41 X I/O (O) P51 (WR Port 1) Port 5 bit 1 (CCU write Port 1)44 40 X I/O (O) P52 (RD Port 2) Port 5 bit 2 (CCU read Port 2)45 39 X I/O (O) P53 (WR Port 2) Port 5 bit 3 (CCU write Port 2)46 38 X I/O (O) P54 (RD Port 3) Port 5 bit 4 (CCU read Port 3)47 37 X I/O (O) P55 (WR Port 3) Port 5 bit 5 (CCU write Port 3)48 36 X I/O (O) P70 (Memory Bank Port 7 bit 0 (Memory Bank Address 0)

Address 0)49 35 X I/O (O) P71 (Memory Bank Port 7 bit 1 (Memory Bank Address 1)





Address 5)54 30 X I/O (O) P76 (R/W) Port 7 bit 6 (CPU read/write)55 29 X I/O (O) P77 (Power-Down Port 7 bit 7 (Power-Down Control)

Control)56 28 X I/O P80 Port 8 bit 057 27 X I/O P81 Port 8 bit 158 26 X I/O P82 Port 8 bit 259 – X I/O P83 Port 8 bit 360 25 X I/O /I P87/INT Port 8 bit 7 /interrupt input61 24 X I/O P60 Port 6 bit 062 23 X I/O P61 Port 6 bit 163 22 X I/O P62 Port 6 bit 264 21 X I/O P63 Port 6 bit 365 20 X I/O P64 Port 6 bit 466 19 X I/O P65 Port 6 bit 567 18 X I/O P66 Port 6 bit 668 17 X I/O P67 Port 6 bit 7


22

Pin DescriptionsCCU 3000, CCU 3001 Pin Descriptions.Pin numbers refer to the 68–pin PLCC housing.The functions of some pins are influenced by bit 4 of theCCU control register (addr. 201H, copied from FFF9H atreset: CCU control register bit 4 = ‘1’ switches the CCU inPort Mode , CCU control register bit 4 = ‘0’ switches theCCU in Bus Mode.In addition, some port bit functions may be changed be-tween Normal Mode and Special Mode by setting the spe-cific bit in its port mode registers.Pin 1: V sup : +5V power supplyPin 2: GND: Digital groundPin 3: X2: Second Crystal connectorPin 4: X1: First Crystal connectorPin 5: V Stand–by: +5V Stand–by Supply VoltagePin 6: RES\: CCU Reset input / output (open drain)Pin 7: DAT_IM1: IM bus 1 data signal (I/O)Pin 8: ID_IM1: IM bus 1 ident signal outputPin 9: CLK_IM1: IM bus 1 clock signal outputPin 10: DAT_IM2: IM bus 2 data signal (I/O)Pin 11: ID_IM2: IM bus 2 ident signal outputPin 12: CLK_IM2: IM bus 2 clock signal outputPin 13: TIMER1: Timer 1 signal (I/O)Pin 14: TIMER2: Timer 2 signal (I/O)Pin 15: TIMER3: Timer 3 signal (I/O)Pin 16: IR: Infrared signal inputPin 17: P40 or R/W\:

in Port Mode: Port 4 Bit 0in Bus Mode: CPU read/not write output

Pin 18 : P10 or data bit 0:in Port Mode: Port 1 Bit 0in Bus Mode: CPU data bit 0







Pin 25 : P17 or data bit 7:in Port Mode: Port 1 Bit 7

in Bus Mode: CPU data bit 7Pin 26 : P20 or address bit 0:

in Port Mode: Port 2 Bit 0in Bus Mode: CPU address bit 0

Pin 27 : P21 or address bit 1:in Port Mode: Port 2 Bit 1in Bus Mode: CPU address bit 1















Pin 42 : P50 or RDPort1\:in Port Mode:

in Normal Mode: Port 5 Bit 0 (open drain output)in Special Mode: read port 1 (low active)

in Bus Mode:in Normal Mode: Port 5 Bit 0 (open drain output)


23

in Special Mode: read port 1 (low active)Pin 43 : P51 or WRPort1\:

in Port Mode:in Normal Mode: Port 5 Bit 1 (open drain output)in Special Mode: write port 1 (low active)

in Bus Mode:in Normal Mode: Port 5 Bit 1 (open drain output)in Special Mode: write port 1 (low active)



in Bus Mode:in Normal Mode: Port 5 Bit 2 (open drain output)in Special Mode: read port 2 (low active)

Pin 45 : P53 or WRPort2\:in Port Mode:

in Normal Mode: Port 5 Bit 3 (open drain output)in Special Mode: write port 2 (low active)




in Bus Mode:in Normal Mode: Port 5 Bit 4 (open drain output)in Special Mode: read port 3 (low active)

Pin 47 : P55 or WRPort3\:in Port Mode:

in Normal Mode: Port 5 Bit 5 (open drain output)in Special Mode: write port 3 (low active)


Pin 48 : P70 or Memory Bank Address 0:in Port Mode:

in Normal Mode: Port 7 Bit 0in Special Mode: Memory Bank Address 0

in Bus Mode:in Normal Mode: Port 7 Bit 0in Special Mode: Memory Bank Address 0
















Pin 54 : P76 or inverted CPU R/W\:in Port Mode:

in Normal Mode: Port 7 Bit 6in Special Mode: inverted CPU R/W\,i.e.: low active at read

in Bus Mode:in Normal Mode: Port 7 Bit 6in Special Mode: inverted CPU R/W\,i.e.: low active at read

Pin 55 : P77 or Power-down Control:in Port Mode:

in Normal Mode: Port 7 Bit 7in Special Mode: Power-down Control ExternalMemory (high active)

in Bus Mode:in Normal Mode: Port 7 Bit 7in Special Mode: Power-down Control ExternalMemory (high active)

Pin 56 : P80: Port 8 Bit 0Pin 57 : P81: Port 8 Bit 1Pin 58 : P82: Port 8 Bit 2Pin 59 : P83: Port 8 Bit 3Pin 60 : P87/INT:

Port 8 Bit 7 and interrupt input(interrupt controller source 7)

Pin 61 : P60: Port 6 Bit 0Pin 62 : P61: Port 6 Bit 1Pin 63 : P62: Port 6 Bit 2Pin 64 : P63: Port 6 Bit 3Pin 65 : P64: Port 6 Bit 4Pin 66 : P65: Port 6 Bit 5Pin 67 : P66: Port 6 Bit 6Pin 68 : P67: Port 6 Bit 7


24

FEATURES Fast access time: 55ns Low Power “CMOS” Consumption:

Active Current: 30 mAStandby Current 100 µA

Programming voltage: 12.75V Electronic signature for Automated programming Programming times of around 24 sec. (Presto II algo-

rithm)

DESCRIPTIONSThe M27C2001 is a high speed 2 Megabit UV erasableand electrically programmable EPROM ideally suited formicroprocessor systems requiring large programs. It is or-ganised as 262, 144 by 8 bits.The Window Ceramic Frit-Seal Dual-in-Line and LeadlessChip Carrier packages have transparent lids which allowthe user to expose the chip to ultraviolet light to erase thebit pattern. A new pattern can then be written to the devi-ce by following the programming procedure.For applications where the content is programmed onlyone time and erasure is not required, the M27C2001 isoffered in both Plastic Leaded Chip Carrier and PlasticThin Small Outline packages.

A0 - A17 address ›nputsQ0 - Q7 data outputsE chip enableG output enableP programVpp program supplyVcc supply voltage

Vss ground

SIGNAL NAMES

Figure 1. Logic Diagram

VCC

VSS

A0-A17

P

18 8

Q0-Q7

E

G

⇐ ⇔

Vpp

M27C2001

M27C20012 Megabit (256 kx8) UV EPROM

FDIP32W (F)

32

1


25

DEVICE OPERATIONThe modes of operations of the M27C2001 are listed in theOperating Modes table. A single power supply is requiredin the read mode. All inputs are TTL levels except for Vppand 12V on A9 for Electronic Signature.

Read ModeThe M27C2001 has two control functions, both of whichmust be logically active in order to obtain data at the out-puts. Chip Enable (E) is the power control and should beused for device selection. Output Enable (%) is the outputcontrol and should be used to gate data to the output pins,independent of device selection. Assuming that the addres-ses are stable, the address access time (tAVQV) is equal tothe delay from E to output (tELQV). Data is available at theou~put after a delay of tGLQV from the falling edge of G, as-suming that E has been low and the addresses have beenstable for at least tAVQV-tGLQV.

Standby ModeThe M27C2001 has a standby mode which reduces the ac-tive current from 30mA to 100µA. The M27C2001 is placedin the standby mode by applying a CMOS high signal to theE input. When in the standby mode, the outputs are in a

high impedance state, independent of the G input.

Two Line Output ControlBecause EPROMs are usually used in larger memory ar-rays, this product features a 2 line control function whichaccommodates the use of multiple memory connection.The two line control function allows:a- the lowest possible memory power dissipation,b- complete assurance that output bus contention will notoccur.For the most efficient use of these two control lines, E sho-uld be decoded and used as the primary device selectingfunction, while G should be made a common connection toall devices in the array and connected to the READ linefrom the system control bus. This ensures that all deselec-ted memory devices are in their low power standby modeand that the output pins are only active when data is requ-ired from a particular memory device.

System ConsiderationThe power switching characteristics of Advanced CMOSEPROMs require careful decoupling of the devices. Thesupply current, Ice, has three seg- ments that are of inte-rest to the system designer : the standby current level, theactive current level, and transient current peaks that areproduced by the falling and rising edges of E. The magni-tude of the transient current peaks is dependent on the ca-pacitive and inductive loading of the device at the output.The associated transient voltage peaks can be suppressedby complying with the two line outputcontrol and by properly selected decoupling ca- pacitors. Itis recommended that a 0.1µF ceramic capacitor be used onevery device between Vee and Vss. This should be a highfrequency capacitor of low inherent inductance and shouldbe placed as close to the device as possible. In addition, a4.7µF bulk electrolytic capacitor should be used betweenVee and Vss for every eight devices. The bulk capacitorshould be located near the power supply connection po-int.The purpose of the bulk capacitor is to overcome thevoltage drop caused by the inductive effects of PCB traces.

1

2

3

4

5

6

7

28

27

26

25

24

23

22

VPP

A16

A15

A12

A7

A6

A5

U

A13

A8

A9

A11

G

A10

E

8

21

A4

Q7

9

20

A3

Q6

10

19

A2

Q5

11

18

A1

Q4

12

17

A0

Q3

13

32

Q0

VCC

14

31

Q1

P

15

30

Q2

A17

16

29

Vss

A14

A10M27C2001

Pin Connections


26

ABSOLUTE MAXIMUM RATINGS

TA ambient operating temperature 40 to 125 oCTBIAS temperature under b›as 50 to 125 oC

Tstg storage temperature 65 to 150 oCVIO

(2) input or output voltage (except A9) 2 to 7 VvCC supply voltage 2 to 7 VvA9

(2) A9 voltage 2 to 13.5 VVPP program supply voltage 2 to 14 V

SYMBOL PARAMETER VALUE Unit

1 Except for the rating “Operating Temperature Range”,stresses above those listed in the Table "Absolute Ma-ximum Ratings'” may cause permanent damage to thedevice. These are stress ratings only and operation ofthe device at these or any other conditions above tho-se indicated in the Operating sections of this specifica-tion is not implied. Exposure to Absolute Maximum Ra-ting conditions for extended periods may affect device

reliability. Refer also to the SGS-THOMSON SUREProgram and other relevant quality documents.

2. Minimum DC voltage on Input or Output is 0.5V withpossible undershoot to 2.0V for a period less than20ns. Maximum DC voltage on Output is Vcc+0.5Vwith possible overshoot to Vcc + 2V for a period lessthan 20ns.

AC MEASUREMENT CONDITIONS

HIGH SPEED STANDARD

Input Rise and Fall Times ≤10ns ≤20ns

Iput Pulse Voltage 0 to 3 V 0.4 V to 2.4 V

Input and Output Timing Ref. Voltages 1.5 V 0.8 V and 2 V

OPERATING MODES

Mode E G P A9 VPP Q0-Q7

Read VIL VIL x x VCC or VSS Data Out

Output disable VIL VIL x x VCC or VSS Hi-Z

Program VIL VIL VIL Pulse x VPP Data In

Verify VIL VIL VIH x VPP Data Out

Program Inhibit VIH x x x VPP Hi-Z

Standby VIH x x x VCC or VSS Hi-Z

Electronic Signature VIL VIL VIH VID VCC Codes


27

DESCRIPTIONThe TL77xxA family of integrated-circuit supply-voltage supervisors is specifically designed for use as reset con-trollers in microcomputer and microprocessor systems. The supply-voltage supervisor monitors the supply for under-voltage conditions at the SENSE input. During power up, the RESET output becomes active (low) when VCC attainsa value approachi ng 3.6 V. At this point (assuming that SENSE is above VIT+), the delay timer function activates atime delay, after which outputs RESET and RESET go inactive (high and low, respectively).When an undervoltage condition occurs during normal operation, outputs RESET and RESET go active. To ensurethat a complete reset occurs, the reset outputs remain active for a time delay after the voltage at the SENSE inputexceeds the positive-going threshold value. The time delay is determined by the value of the external capacitor CT:

td = 1.3 x 104 x CT, where CT is in farads (F) and td is in seconds (s).

During power down (assuming that SENSE is below VIT-), the outputs remain active until the VCC falls below a max-

imum of 2 V. After this, the outputs are undefined.An external capacitor (typically 0.1 µF for the TL77xxAC and TL77xxAI) must be connected to REF to reduce theinfluence of fast transients in the supply voltage.The TL77xxAC series is characterized for operation from OoC to 70oC. The TL77xxAI series is characterized for oper-ation from -40oC to 85oC.

TL7702A, TL7705A, TL7709A, TL7712A, TL7715ASupply-Voltage Supervisors

1

2

3

4

REF

RESIN

CT

GND

U8 VCC

7 SENSE

6 RESET

5 RESET

D OR P PACKAGE(Top view) Power-On Reset Generator

Automatic Reset Generation After VoltageDrop

Wide Supply-Voltage Range Precision Voltage Sensor Temperature-Compensated Valtage

Reference True and Complement Reset Outputs Externally Adjustable Pulse Duration

PACKAGED DEV‹CESSMALL PLASTIC

OUTLINE DIP(D) (P)

TL7702ACD TL7702ACP TL7702ACYTL7705ACD TL7705ACP TL7705ACYTL7709ACD TL7709ACP TL7709ACYTL7712ACD TL7712ACP TL7712ACYTL7715ACD TL7715ACP TL7715ACY

TL7702AID TL7702AIP –TL7705AID TL7705AIP –TL7709AID TL7709AIP –TL7712AID TL7712AIP –TL7715AID TL7715AIP –

TACHIPFORM

(Y)

AVAILABLE OPTIONS

0oC to 70oC

-40oC to 85oC

The D package is available taped and reeled. Add the suffix R to thedevice type (e.g., TL7702ACDR). Chip forms are tested at 25oC


28

FUNCTIONAL BLOCK DIAGRAMThe functional block diagram is shown for illustrative purposes only; the actual circuit includes a trimming network toadjust the reference voltage and sense-comparator trip point


29

SPECIFICATIONS

Outline Dimensions

TPU30 , TPU3040, TPU3050Teletext Processor


30

PIN CONNECTIONS AND SHORT DESCRIPTIONS

Pin No. Pin No. Pin No. Signal Name Type SymbolPLCC44 PDIP40 PSDIP52

TPU3040 TPU3035 TPU3040TPU3040 TPU3050


31

Pin No. Pin No. Pin No. Signal Name Type SymbolPLCC44 PDIP40 PSDIP52

TPU3040 TPU3035 TPU3040TPU3040 TPU3050


32

PIN DESCRIPTIONS


33

TPU3050 in 52 pin PSDIP package

TPU3040 in 44 pin PLCC packageTPU3040 in 40 pin PDIP package


34

K6T4008C1B Family512Kx8 bit Low Power CMOS Static RAM

FEATURES• Process Technology: TFT• Organization: 512Kx8• Power Supply Voltage: 4.5~5.5V• Low Data Retention Voltage: 2V(Min)• Three state output and TTL Compatible• Package Type: 32-DIP-600, 32-SOP-525

32-TSOP2-400F/R

GENERAL DESCRIPTIONThe K6T4008C1B families are fabricated bySAMSUNG’s advanced CMOS process technology.The families support various operating temperatureranges and various package types for user flexibili-ty of system design. The family also support lowdata retention voltage for battery back-up operationwith low data retention current.

PRODUCT FAMILY


35


36


37


38

FUNCTIONAL DESCRIPTIONThe AS7C1024 and AS7C31024 are high performanceCMOS 1.048.576-bit Static Random Access Memory(SRAM) devices organized as 131.072 words x 8 bits. it isdesigned for memory applications where fast data access,low power, and simple interfacing are desired.Equal address access and cycle times (tAA, tRC, tWC) of10/12/15/20 ns with output enable access times (tOE) of5/6/8/10 ns are ideal for high performance applications.Active high and low chip enables CE1, CE2) permit easymemory expansion with multiple-bank systems.When CE1 is high or CE2 is low the devices enter stand-by mode. If inputs are still toggling, the device will con-sume ISB power. If the bus is static, then full standbypower is reached (ISB1 orISB2). For example, theAS7C31024 is guaranteed not to exceed 0.33mW undernominal full standby conditions. All devices in this familywill retain data when VCC is reduced as low as 2.0V.

A write cycle is accomplished by asserting write enable(WE) and both chip enables (CE1, CE2). Data on theinput pins I/00-I/07 is written on the rising edge of WE (write cycle I) or the active-to-inactive edge of CE1 or CE2(write cycle 2). To avoid bus contention, external devicesshould drive I/O pins only after outputs have been dis-abled with output enable (OE) or write enable (WE).A read cycle is accomplished by asserting output enable(OE) and both chip enables (CE1, CE2), with write enable(WE) high. The chips drive I/O pins with the data word ref-erenced by the input address. When either chip enable isinactive, output enable is inactive, or write enable isactive, output drivers stay in high-impetiance mode.

ABSOLUTE MAXIMUM RATING

TRUTH TABLE

Parameter Symbol Min Max Unit

AS7C1024 Vt1 -0.50 +7.0 VVoltage on VCC relative to GND

AS7C31024 Vt1 -0.50 +5.0 V

Voltage on any pin relative to GND Vt2 -0.50 VCC+0.50 V

Power dissipation PD - 1.0 W

Storage temperature (plastic) Tstg -65 +150 oC

Ambient temperature with Vcc applied Tbias -55 +125 oC

DC current into outputs (low) Iout - 20 mA

Stresses greater than those listed under Absolute Maximurn Ratings may cause permanent: damage to the device. This is a stress rating onlyand functional operation of the device al these or any other conditions outside those indicated in the operational sections of this specification isnot implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

CE1 CE2 WE OE Data Mode

H X X X High Z Standby (ISB, ISB1)

X L X X High Z Standby (ISB, ISB1)

L H H H High Z Output disable (ICC)

L H H L Oout Read (ICC)

L H L X Din Write (ICC)

Key: X= Don’t Care, L= Low, H= High


39

FEATURES• AS7C1024 (5V version)• AS7C31024 (3.3V version)• Industrial and commercial temperatures• Organization: 131.072 words x 8 bits• High speed

– 10/12/15/20 ns address access time– 5/6/8/10ns output enable access time

• Low power consumption: ACTIVE– 660 mW (AS7C1024) / max @ 12 ns– 216 mW (AS7C31024) / max @ 12 ns

• Low power consumption: STANDBY– 2.75 mW (AS7C1024) / max CMOS– 1.8 mW (AS7C31024) / max CMOS

• 2.0V data retention• Easy memory expansion with CE1, CE2, OE inputs• TTL/LVTTL-compatible, three-state I/O• 32 pin JEDEC standard packages

– 300 mil SOJ– 400 mil SOJ– 8 x20mm TSOP I– 8 x13.4 mm sTSOP I

• ESD protection ≥ 2000 volts• Latch-up current ≥ 200 mA

AS7C1024 - AS7C310245V/3.3V 128Kx8 CMOS SRAM

LOGIC BLOCK DIAGRAM

SELECTION GUIDE

PIN ARRANGEMENT

AS7C1024-10 AS7C1024-12 AS7C1024-15 AS7C1024-20

AS7C31024-10 AS7C31024-12 AS7C31024-15 AS7C31024-20 Unit

Maximum address access time 10 12 15 20 ns

Maximum output enable access time 5 6 8 10 ns

Maximum operating current AS7C1024 1580 120 95 80 mA

AS7C31024 80 60 50 45 mA

Maximum CMOS standby current AS7C1024 0.5 0.5 0.5 0.5 mA

AS7C31024 0.5 0.5 0.5 0.5 mA


40

Parameter Device Symbol Min Nominal Max Unit

Supply voltageAS7C1024 VCC 4.5 5.0 5.5 V

AS7C31024 VCC 3.0 3.3 3.6 V

Input voltageAS7C1024 VIH 2.2 - VCC + 0.5 V

AS7C31024 VIH 2.0 - VCC + 0.5 V

VIL† -0.5 - 0.8 V

Ambient commercial TA 0 - 70 oC

temperature industrial TA -40 - 85 oC

RECOMMENDED OPERATING CONDITIONS

DC OPERATING CHARACTERISTICS (Over the operating range)1

CAPACITANCE (f = 1MHz, Ta = 25 oC, VCC = NOMINAL)2

-10 -12 -15 -20Parameter Sym Test conditions Device Min Max Min Max Min Max Min Max Unit

I ILI I VCC = Max, Vin = GND to VCC - 1 - 1 - 1 - 1 µA

I ILI I VCC = Max, CE1 = VIH or - 1 - 1 - 1 - 1 µACE2 = VIL, Vout = GND to VCC

ICC VCC = Max, CE1 = VIL AS7C1024 - 150 - 120 - 95 - 80mACE2 = VIH, f = fMax, IOUT=0 mA AS7C31024 - 80 - 60 - 50 - 45

VCC = Max, CE1 ≥ VIH and / or AS7C1024 - 45 - 35 - 25 - 25 mAISB CE2 ≤ VIL, VIN = VIH or VIL,

AS7C31024 - 45 - 35 - 25 - 25f = fMax, IOUT=0 mA

VCC = Max, CE1 ≥ VCC –0.2V AS7C1024 - 0.5 - 0.5 - 0.5 - 0.5 mAISB1 VIN ≤ GND +0.2V or

AS7C31024 - 0.5 - 0.5 - 0.5 - 0.5VIN ≥ VCC +0.2V, f= 0Output VOL IOL = 8mA, VCC = Min - 0.4 - 0.4 - 0.4 - 0.4 Vvoltage VOH IOH = –4 mA, VCC = Min 2.4 - 2.4 - 2.4 - 2.4 - V

InputleakagecurrentOutputleakagecurrentOperating power supplycurrent

Standby power supplycurrent

Parameter Symbol Signals Test Conditions Max Unit

Input capacitance CIN A, CE1, CE2, WE, OE Vin = 0V 5 pF

I/O capacitance CI/O I/O Vin = Vout = 0V 7 pF


41

DC OPERATING CHARACTERISTICS (Over the operating range)1

-10 -12 -15 -20

Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes

Read cycle time tRC 10 - 12 - 15 - 20 - ns

Address access time tAA - 10 - 12 - 15 - 20 ns 3

Chip enable (CE1) access time tACE1 - 10 - 12 - 15 - 20 ns 3,12

Chip enable (CE2) access time tACE2 - 10 - 12 - 15 - 20 ns 3,12

Output enable (OE) access time tOE - 3 - 3 - 4 - 5 ns

Output hold from address change tOH 2 - 3 - 3 - 3 - ns 5

CE1 Low to output in low Z tCLZ1 3 - 3 - 3 - 3 - ns 4,5,12

CE2 High to output in low Z tCLZ2 3 - 3 - 3 - 3 - ns 4,5,12

CE1 Low to output in high Z tCHZ1 - 3 - 3 - 4 - 5 ns 4,5,12

CE2 Low to output in high Z tCHZ2 - 3 - 3 - 4 - 5 ns 4,5,12

OE Low to output in low Z tOLZ 0 - 0 - 0 - 0 - ns 4,5

OE High to output in high Z tOHZ - 3 - 3 - 4 - 5 ns 4,5

Power up time tPU 0 - 0 - 0 - 0 - ns 4,5,12

Power down time tPD - 10 - 12 - 15 - 20 ns 4,5,12


42

Symbol DescriptionA0 – A10 Address Inputs (2K product)

I/O0 - I/O3 Data Input/OutputRAS Row Address StrobeCAS Column Address StrobeWE Write EnableOE Output Enable

VCC 3.3V Power SupplyVSS GroundNC No Connection

Features• Organization: 4,194,304 words X 4 bits• Part Identification

- A42L2604 (2K Ref.)- A42L2604-L (2K Ref. with self-refresh)

• Single 3.3V power supply/built-in VBB generator• Low power consumption

- Operating: 120mA (-50 max)- Standby: 1mA (TTL), 0.2mA (CMOS),

250mA (Self-refresh current)• High speed

- 50/60 ns RAS access time- 25/30 ns column address access time- 15/17 ns CAS access time- 20/25 ns EDO Page Mode Cycle Time

• Fast Page Mode with Extended Data Out• Refresh Cycle

• Read-modify-write,RAS -only, CAS -before-RAS ,Hidden refresh capability

• TTL-compatible, three-state I/O• JEDEC standard packages

- 300mil, 24/26-pin SOJ- 300mil, 24/26-pin TSOP type II package

General DescriptionThe A42L2604 is a new generation randomly accessedmemory for graphics, organized in a 4,194,304-word by4-bit configuration. This product can execute Write andRead operation via CAS pin.The A42L2604 offers an accelerated Fast Page Modecycle with a feature called Extended Data Out (EDO).This allow random access of up to 2048(2K Ref.) wordswithin a row at a 50/40 MHz EDO cycle, making theA42L2604 ideally suited for graphics, digital signalprocessing and high performance computing systems.

Part No. Refresh cycle Refresh intervalNormal L-ver

A42L2604 2K 32ms 128ms

• SOJ • TSOP

1

2

3

4

5

6

22

21

19

18

17

16

Vcc

I/O0

I/O1

WE

RAS

NC

U

OE

A9

A8

A7

A6

A5

8

15

A10

A4

9

14

A0

VCC

10A1

11A2

12A3

13

26

VCC

VCC

25 I/O3

24 I/O2

23 CAS

A42L

2604

S

Pin Connections

Pin Descriptions

1

2

3

4

5

6

22

21

19

18

17

16

Vcc

I/O0

I/O1

WE

RAS

NC

O

OE

A9

A8

A7

A6

A5

8

15

A10

A4

9

14

A0

VCC

10A1

11A2

12A3

13

26

VCC

VCC

25 I/O3

24 I/O2

23 CAS

A42L

2604

V

A42L2604 SeriesPreliminary 4M X 4 CMOS Dynamic Ram With Edo Page Mode


43

Functional Description

The A42L2604 reads and writes data by multiplexing an22-bit address into a 11-bit(2K) row and column address.RAS and CAS are used to strobe the row address and thecolumn address, respectively.A Read cycle is performed by holding the WE signal highduring RAS/ CAS operation. A Write cycle is executed byholding the WE signal low during RAS / CAS operation;the input data is latched by the falling edge of WE orCAS, whichever occurs later. The data inputs and outputsare routed through 4 common I/O pins, with RAS, CAS,WE and OE controlling the in direction.EDO Page Mode operation all 2048(2K) columns within aselected row to be randomly accessed at a high data rate.A EDO Page Mode cycle is initiated with a row addresslatched by RAS followed by a column address latched byCAS. While holding RAS low, CAS can be toggled tostrobe changing column addresses, thus achieving short-er cycle times.The A42L2604 offers an accelerated Fast Page Modecycle through a feature called Extended Data Out, whichkeeps the output drivers on during the CAS prechargetime (tcp). Since data can be output after CAS goes high,the user is not required to wait for valid data to appearbefore starting the next access cycle. Data-out will remainvalid as long as RAS and OE are low, and WE is high;this is the only characteristic which differentiatesExtended Data Out operation from a standard Read orFast Page Read.A memory cycle is terminated by returning both RAS andCAS high. Memory cell data will retain its correct state by

maintaining power and accessing all 2048(2K) combina-tions of the 11-bit(2K) row addresses, regardless ofsequence, at least once every 32ms through any RAScycle (Read, Write) or RAS Refresh cycle ( RAS -only,CBR, or Hidden). The CBR Refresh cycle automaticallycontrols the row addresses by invoking the refreshcounter and controller.

Power-OnThe initial application of the VCC supply requires a 200 µswait followed by a minimum of any eight initializationcycles containing a RAS clock. During Power-On, theVCC current is dependent on the input levels of RAS andCAS. It is recommended that RAS and CAS track withVCC or be held at a valid VIH during Power-On to avoidcurrent surges.

Symbol Description -50 -60 Unit

tRAC Maximum RAS Access Time 50 60 ns

tAA Maximum Column Address Access Time 30 35 ns

tCAC Maximum CAS Access Time 15 17 ns

tOEA Maximum Output Enable ( OE) Access Time 13 15 ns

tRC Minimum Read or Write Cycle Time 84 104 ns

tPC Minimum EDO Cycle Time 20 25 ns

Selection Guide


44

Block Diagram

Symbol Description Min. Typ. Max. Unit

VCC Power Supply 3.0 3.3 3.6 V

VSS Input High Voltage 0 0 0 V

VIH Input High Voltage 2.0 - VCC + 0.3 V

VIL Input Low Voltage -1.0 - 0.8 V

Recommended Operating Conditions (Ta = 0°C to +70°C)


45

Function RAS CAS WE OE Address I/Os

Standby H H X X X High-Z

Read: Word L L H L Row/Col. Data Out

Read L L H L Row/Col. Data Out

Write: Word (Early) L L L X Row/Col. Data In

Write (Early) L L L X Row/Col. Data In

Read-Write L L H→L L→H Row/Col. Data Out → Data In

EDO-Page-Mode Read: Hi-Z

-First cycle L H→L L X Row/Col. Data In

-Subsequent Cycles L H→L L X Col. Data In

EDO-Page-Mode Write(Early)

-First cycle L H→L H→L L→H Row/Col. Data Out → Data In

-Subsequent Cycles L H→L H→L L→H Col. Data Out → Data In

Hidden Refresh Read L→H→L L H L Row/Col. Data Out

Hidden Refresh Write L→H→L L L X Row/Col. Data In → High-Z

RAS-Only Refresh L H X X Row High-Z

CBR Refresh H→L L X X X High-Z

Self Refresh (L-ver only) H→L L H X X High-Z

Truth Table


46

DESCRIPTIONThis specification covers a range of 16K bits I2C bus EEP-ROM products, the ST24/25C16 and the ST24/25W16. Inthe text, products are referred to as ST24/25x16 where“X” is: “C” for Standard version and “W” for hardwareWrite Control version.

The ST24/25x16 are 16K bit electrically erasable pro-grammable memories (EEPROM), organized as 8 blocksof 256x8 bits. These are manufactured in SGS-THOMSON’s Hi-Endurance Advanced CMOS technologywhich guarantees an endurance of one millionerase/write cycles with a data retention of 10 years. TheST25x16 operates with a power supply value as low as2.5V. Both Plastic Dual-in-Line and Plastic Small Outlinepackages are available.

The memories are compatible with the I2C standard, twowire serial interface which uses a bi-directional data busserial clock. The memories carry a built-in 4 bit, uniquedevice identification. The memories behave as slavedevices in the I2C protocol with all memory operationssynchronized by the serial clock. Read and write opera-tions are initiated by a START condition generated by thebus master. The START condition is followed by a streamof 4 bits (identification code 1010), 3 block select bits,plus one read/write bit and terminated by an acknowl-edge bit.When writing data to the memory it responds to

FEATURES 1million erase / write cycles, with 40 years data retention Single supply voltage:

-4.5V to 5.5V for ST24x16 versions- 2.5V to 5.5V for ST25x16 versions

Hardware write control versions: ST24W16 and ST25W16 Two wire serial interface, fully I2C bus compatible Byte and multibyte write (up to 8 bytes) for the ST24C16 Page write (up to 16 bytes) Byte, random and sequential read modes Self timed programming cycle Automatic address incrementing Enhanced ESD/Latch up performances

PSIDIP8 (B)0.25 mm Frame

SO14 (ML)

SOB (M)

8

1 1

14

8

1

ST24C16, ST25C16Serial 16K (2Kx8) EEPROM


47

PRE write protect enablePB0, PB1 protect block selectSDA serial data address input/outputSCL serial clockMODE Multybyte/page write mode (C version)WC write control (W version)Vcc supply voltage

Vss ground

SIGNAL NAMES

1

2

3

4

PRE

PB0

PB1

VSS

VCC

SDA

VSS

PB0-PB1

PRE

2

SCL

MODE/WC*

U8 VCC

7 MODE/WC

6 SCL

5 SDA

ST24x16ST25x16

DIP Pin Connections

Logic Diagram

Note: WC signal is only available for ST24/25W16 prod-ucts.

⇐

the 8 bits received by asserting an acknowledge bit duringthe 9th bit time. When data is read by the bus master, itacknowledges the receipt of the data bytes in the sameway. Data transfers are terminated with a STOP condition.

Data in the 4 upper blocks of the memory may be writeprotected. The protected area is programma-ble to starton any 16 byte boundary. The block in which the protec-tion starts is selected by the input pins PB0, PBI.Protection is enabled by setting a Protect Flag bit whenthe PRE input pin is driven High.

Power On Reset: VCC lock out write protect. In order toprevent data corruption and inadvertent write operationsduring power up, a Power On Reset (POR) circuit isimplemented. Until the VCC voltage has reached the PORthreshold value, the internal reset is active: all operationsare disabled and the device will not respond to any com-mand. In the same way, when VCC drops down from theoperating voltage to below the POR threshold value, alloperations are disabled and the device will not respond toany command. A stable VCC must be applied beforeapplying any logic signal.

ST24x16ST25x16


48

5 V supply voltage, low power consumption Active carrier generation by FPLL principle (frequency-

phase-locked-loop) for true synchronous demodulation Very linear video demodulation, good pulse response

and excellent intermodulation figures VCO circuit is operating on picture carrier frequency,

the VCO frequency is switchable for the L` mode Alignment free AFC without external reference circuit,

polarity of the AFC curve is switchable VIF AGC for negative modulated signals (peak sync.

detection) and for positive modulation (peak white/blacklevel detector)

Tuner AGC with adjustable take over point Alignment free quasi parallel sound (QPS) mixer for

FM/NICAM sound IF signals Intercarrier output signals is gain controlled (necessary

for digital sound processing) Complete alignment-free AM demodulator with gain

controlled AF output Separate SIF-AGC with average detection Two independent SIF inputs Parallel operation of the AM demodulator and QPS mi-

xer (for NICAM L stereo sound) Package and relevant pinning is compatible with t h e

single standard version TDA4472, which simplifies thedesign of an universal IF module

The TDA4470B is an integrated bipolar circuit for multis-tandard video/sound IF (VIF/SIF) signal processing inTV/VCR and multimed‹a applications. The circuit proces-ses all TV video IF signals with negative modulation (e.g.,

B/G standard), positive modulation (e.g., L standard) andthe AM, FM/NICAM sound IF signals.

DESCRIPTION

FEATURES

Pin Symbol Function1, 2 Vi,SIF1 SIF1 input (symmetrical)

3 Vsw Input selector switch4, 9,16 GND Ground

5 CAGC SIF-AGC (time constant) 6, 7 Vi,VIF VIF input (symmetrical)

8 CAGC VIF-AGC (time constant) 10 Rtop Take over point, tuner AGC11 Itun Tuner AGC output current 12 V0,vid Video output 13 VSW Standard switch14 VSW L’ switch 15 Cbi Black level capacitor 17 Cref Internal reference voltage18 LF Loop filter 19 VSW AFC switch

20.21 VVCO VCO circuit 22 VAFC AFC output 23 VS Supply voltage 24 V0-FM Intercarrier output 25 V0-AM AF output - AM sound 26 Rcomp Offset compensation

27, 28 Vi, SIF2 SIF2 input (symmetrical)

PINNING

1

2

3

4

5

6

7

28

27

26

25

24

23

22

Vi,SIF1

Vi,SIF1

Vsw

GNDCAGC

Vi,VIF1

Vi,VIF1

U

Pin Description

Vi,SIF2

Vi,SIF2

Rcomp

V0, AM

V0, AM

VS

VAFC

8 21CAGC VVCO

9 20GND VVCO

10 19Rtop VSW

11 18Itun LF

12 17V0, vid. Cref

13 16VSW GND14 15VSW CBL

TDA4470B

TDA4470BMultistandard Video-If and Quasi Parallel Sand Processing


49

Offsetcomp.

(optional)

Loopfilter

FPLL

AGC(VIF)

AGC(SIF)

TUNERAGC

Supply

Standard

AFC

ControlVCO+

phase shift

26

6

7

CAGC

CBL

Tuner

SIF 2

SIF 1

CAGC

SIF inputswitch

Take overpoint

8

15

11

10

27

28

3

1

2

5

18

VIF amp.

Video det.

SIF amp.

FM detCRef

VS

AM det. 4, 9, 16

25

24

17

23

13

12

22

19

14

AFC

AFCswitch

Video

StandardSwitch

AF(AM)

Intercarrier(FM / NICAM)

VIF

0O

90O

20

VCO

L’ switch

21

Block Diagram for TDA4470-B


50

Vision IF AmplifierThe video IF signal (VIF) is fed through a SAW filter to the differential input (Pin 6-7) of the VIFamplifier. This amplifier consists of three AC-coupled amplifier stages. Each differential ampli-fier is gain controlled by the automatic gain control (VIF-AGC). The output signal of the VIFamplifier is applied to the FPLL carrier generation and the video demodulator.

Tuner-and VIF-AGCAt Pin 8, the VIF-AGC charges/discharges the AGC capacitor to generate a control voltage forsetting the gain of the VIF amplifier and tuner in order to keep the video output signal at a cons-tant level. Therefore, in the case of all negative modulated signals (e.g., B/G standard) the sync.level of the demodulated video signal is the criterion for a fast charge/discharge of the AGC ca-pacitor. For positive modulation (e.g., L standard) the peak white level of video signal controlsthe charge current. In order to reduce reaction time for positive modulation, where a large timeconstant is needed, an additional black level detector controls the discharge current in the eventof decreasing VIF input signal. The control voltage (AGC voltage at Pin 8) is transferred to aninternal control signal, and is fed to the tuner AGC to generate the tuner AGC current at Pin 11(open collector output). The take over point of the tuner AGC can be adjusted at Pin 10 by apotentiometer or an external de voltage (from interface circuit or microprocessor).

FPLL,VCO and AFCThe FPLL circuit (frequency phase locked loop) consists of a frequency and phase detector togenerate the control voltage for the VCO tuning. In the locked mode, the VCO is controlled bythe phase detector and in unlocked mode, the frequency detector is superimposed. The VCOoperates with an external resonance circuit (L and C parallel) and is controlled by internal vari-caps. The VCO control voltage is also converted to a current and represents the AFC outputsignal at Pin 22. At the AFC switch (Pin 19) three operating conditions of the AFC are possib-le: AFC curve “rising” or “falling” and AFC “off’.

A practicable VCO alignment of the external coil is the adjustment to zero AFC output currentat Pin 22. At center frequency the AFC output current is equal to zero. Furthermore. at Pin 14.the VCO center frequency can be switched for setting to the required L’ value (L’ standard).

The optional potentiometer at Pin 26 allows an offset compensation of the VCO phase for imp-roved sound quality (fine adjustment). Without a potentiometer (open circuit at Pin 26). this off-set compensation is not active.

The oscillator signal passes a phase shifter and supplies the in-phase signal (0o) and the quad-rature signal (90o)of the generated picture carrier.

Video Demodulation and Amplifier The video IF signal, which is applied from the gain controlled IF amplifier, is multiplied with theinphase component of the VCO signal. The video demodulator is designed for low distortionand large bandwidth. The demodulator output signal passes an integrated low pass filter for at-tenuation of the residual vision carrier and is fed to the video amplifier. The video amplifier isrealized by an operational amplifier with internal feedback and 8 MHz bandwidth (-3 dB). A stan-dard dependent de level shift in this stage delivers the same sync. level for positive and nega-tive modulation. An additional noise clipping is provided. The video signal is fed to VlF-AGC andto the video output buffer. This amplifier with a 6 dB gain offers easy adaption of the sound trap.For nominal video IF modulation the video output signal at Pin 12 is 2 Vpp.

Sound IF Amplifier and SIF-AGCThe SIF amplifier is nearly identical with the 3-stage VIF amplifier. Only the first amplifier stageexists twice and is switchable by a control voltage at Pin 3. Therefore with a minimal externalexpense it is possible to switch between two different SAW filters. Both SIF inputs features ex-

CIRCUIT DESCRIPTION


51

cellent cross-talk attenuation and an input impedance which is independent from the switchingcondition.

The SIF-AGC is related to the average level of AM- or FM-carrier and controls the SIF amplifi-er to provide a constant SIF signal to the AM demodulator and QPS mixer.

AM DemodulatorThe alignment-free AM demodulator is realized by a synchronous detector. The modulated SIFsignal from the SIF amplifier output is multiplied in phase with the limited SIF signal (AM is re-moved). The AF signal of the demodulator output is fed to the output amplifier and to the SIF-AGC. For all TV standards with negative video modulation (eg., B/G standard). the AF outputsignal (Pin 25) is switched off by the standard switch.

Quasi-Parallel-Sound (QPS) MixerThe QPS mixer i~ realized by a multiplier. The signal (FM or NICAM carrier) is converted to theintercarrier frequency by the regenerated picture carrier frequency by the regenerated picturecarrier (quadrature signal) which is provided from the VCO. The intercarrier signal is fed via anoutput amplifier to Pin 24.

Standard Switch

To have equal polarity of the video output signal the polarity can be switched in the demo-dulation stage in accordance with the TV standard. Additional a standard dependent de le-vel shift in the video amplifier delivers the same sync. level. In parallel to this, the correctVIF-AGC is selected for positive or negative modulated VIF signals. In the case of negati-ve modulation (e.g., B/G standard) the AM output signal is switched off. For positive mo-dulation (L standard) the AM demodulator and QPS mixer is active. This condition allowsa parallel operation of the AM sound signal and the NICAM-L stereo sound.

L’Switch

With a control voltage at Pin 14 the VCO frequency can be switched for setting to the re-quired L’ value (L’ standard). Also a fine adjustment of the L’-VCO center frequency is pos-sible via a potentiometer. The L’ switch is only active for positive modulated video IF-sig-nals (standard switch in L mode).

AFC Switch

The AFC output signal at Pin 22 can be controlled by a switching voltage at Pin 19. It ispossible to select an AFC output signal with a rising-or falling AFC curve and to switch offthe AFC.

VCR Mode

For the VCR mode in a TV set (external video source selected), it is recommendable toswitch off the IF circuit. With an external switching voltage at Pin 6 or 7, the IF amplifiersare switched off and all signal output levels at Pins 12, 24, and 25 are according to the in-ternal de voltage.

Internal Voltage Stabilizer

The internal bandgap reference ensures constant performance independent of supply vol-tage and temperature.


52

SPECIFICATIONS

Outline Dimensions

MSP34x1GMultistandart Sound Processor (Virtual Dolby)

68-Pin Plastic Leaded Chip Carrier Package (not intended for new designs)((PPLLCCCC6688))Weight approximately 4.8 gDimensions in mm

64-Pin Plastic Shrink Dual-Inline Package((PPSSDDIIPP6644))Weight approximately 9 gDimensions in mm

52-Pin Plastic Shrink Dual-Inline Package((PPSSDDIIPP5522))Weight approximately 5.5 gDimensions in mm


53

80-Pin Plastic Quad Flat Pack((PPQQFFPP8800))Weight approximately 1.61 gDimensions in mm

64-Pin Plastic Low-Profile Quad Flat Pack((PPLLQQFFPP6644))Weight approximately 3.5 gDimensions in mm


54


Pin No. Pin Name Type Connection Short Descriptio›nPLCC PSDIP PSDIP PQFP PLQFP (if not used)

68-pin 64-pin 52-pin 80-pin 64-pin


55




56




57

PIN DESCRIPTIONS


58


59

64-pin PSDIP package

52-pin PSDIP package


60

GENERAL DESCRIPTIONThe TDA 6920 switches 7 video input sources to 5 outputs. Each output can beswitched to only one input, but one input can be switched to all outputs.The C-input may be combined with one CVBS input as Y for Y+C (S-VHS) operation.Y+C operation is selected by bus.

FEATURES• Fast I2C-BUS controlled (max. 400 kHz)• Cascadable (2 bus addresses)• 7 CVBS inputs, 5 outputs 3 inputs with clamp disable by bus• 1 input selectable as Y-input (S-VHS)• 1 additional C-input (S-VHS)• Y+C operation for S-VHS selected by bus• Fully ESD protected• -60 dB max. crosstalk at 5 MHz (P-DSO-28 only)• Low operating voltage of 7.5 V• 5V operation is possible with reduced output signals of max. 2 V pp• 15 MHz minimum bandwidth• Noise insensitive clamping inputs• low impedance off condition separate for each output Application • Television sets• Satellite receivers• Video mixing desks

TDA6920Scart Switch

Package

FUNCTIONAL DESCRIPTION

The main function of the IC is to switch 7 input videosources to 5 outputs.Each output can be switched to only one input.It is possible to have the same input connected to sev-eral outputs.3 of the inputs can be used as non-clamping-input,switching is controlled by bus.The clamping function of the other 4 inputs can beswitched off by external resistor divider.All switching possibilities are controlled by the I2C-BUS.All outputs can be switched to low impedance off con-dition by the I2C-BUS.Driving 75 W load requires external transistors.The recommended coupling capacitor at each input is

47 nF.Each clamping input requires a 75 W (max. 500 W)termination resistor.Operation without or with a termination resistor greaterthan 500 W causes mal-functionof the new high performance clamping circuit.Unused input‘s should be directly grounded.6 x 8 bits are necessary to determine one completeconfiguration change (1 addressbyte, 5 databytes).Minimum configuration change for 1 output needs 2 x8 bit (1 addressbyte,1 databyte).Power on reset state: all 5 outputs switched to input 1,all inputs clamped, Y+C off.


61

Symbol Pin Function

P-DIP-18 P-DIP-28

GND - 1 Signal + power supply ground

IN1 2 2 CVBS input 1









V ref3 - 11 Reference Voltage for external use


GND 9 13 Power supply ground


SCL 10 15 I2C-Bus clock

SDA 11 16 I2C-Bus data

Address 12 17 Address selection

OUT5 13 18 CVBS output 5









VCC 18 27 Positive power supply voltage

C 1 28S eparate color adding input for input 1

PIN DEFINITION AND FUNCTION

1

2

3

4

5

6

7

24

23

22

21

20

19

18

Gnd

In1

Gnd

In2

Gnd

In3

Gnd

Out2

Gnd

Out3

Gnd

Out4

Gnd

Out5

8

17

In4

Address

9

16

Gnd

SDA

10

15

In5

SCL

11Gnd

12In6

13

28

Gnd

C

14

27

In7

Vcc

26 Out1

25 Gnd

TDA6920

Pin Configuration

1

2

3

4

5

6

7

14

13

12

11

10

C

In1

In2

In3

In4

In5

In6

Out4

Out5

Address

SDA

SCL

8In7

9Gnd

18 Vcc

17 Out1

16 Out2

15 Out3

TDA6920


62

PIN DESCRIPTION


63



64

BLOCK DIAGRAM


TDA7264, TDA7264A25+25W Stereo Amplifier with Mute/St-By

DESCRIPTION


66

Pin Connection (Top view)

THERMAL DATA



67

ELECTRICAL CHARACTERISTICS (Refer to the test circuit, VS + 20V; RL = 8W; Rs =50W; f = 1KHz;Tamb = 25°C, unless otherwise specified.)


68

GENERAL DESCRIPTIONThe TDA7050 is a low voltage audio amplifier for small radios with headphones (such as watch, pen and pocketradios) in mono (bridge-tied load) or stereo applications.

FEATURES• Limited to battery supply application only (typ. 3 and 4 V)• Operates with supply voltage down to 1.6 V• No external components required• Very low quiescent current• Fixed integrated gain of 26 dB, floating differential input• Flexibility in use - mono BTL as well as stereo• Small dimension of encapsulation (see package design example)

Supply voltage range Vp 1.6 to 6.0VTotal guiescent current (at Vp = 3V) Itot typ. 3.2 mA

Bridge tied load application (BTL)Output power at RL = 32Ω

Vp = 3V; dtot = 10% Po TYP. 140 mWD.C. output offset voltage between the outputs ∆V max 70 mVnoise output voltage (r.m.s. value)

at f = 1 kHz; Rs = 5Ω Vno(rms) typ. 140µV

Stereo applicationsOutput power at RL = 32Ω

dtot =10%; Vp = 3V Po typ. 35 mWdtot =10%; Vp = 4.5V Po typ. 75mW

Channel separation at Rs = 0Ω; f = 1 kHz α typ. 40 dBnoise output voltage (r.m.s. value)

at f = 1 kHz; Rs = 5Ω Vno(rms) typ. 100µV

QUICK REFERENCE DATA

PACKAGE OUTLINE8 -lead DIL; plastic (SOT97); SOT97-1; 1996 July 23.

TDA7050Low voltage mono/stereo power amplifier


69

Fig. 2 Output power across the load impedance (RL) as a function of supply voltage (VP) in BTL applica-

tion. Measurements were made at f = 1 kHz; dtot = 10%; Tamb = 25 oC

Fig. 3 Output power across the load impedance (RL) as a function of supply voltage (VP) in stereo appli-

cation. Measurements were made at f = 1 kHz; dtot = 10%; Tamb = 25 oC


70

PARAMETER SYMBOL MIN. TYP. MAX. UNITSupply voltage Vp 1.6 – 6.0 V

Total guiescent current Itot – 3.2. 4 mA

Bridge tied load application (BTL); see Fig.4Output power; note 1

Vp = 3.0V; dtot = 10% Po – 140 – mW

Vp = 4.5V; dtot = 10% (RL = 64Ω) Po – 150 – mW

Voltage gain Gv – 32 – dB

Noise output voltage (r.m.s. value)

Rs = 5Ω; f = 1 kHz; Vno(rms) – 140 – µV

Rs = 0Ω; f = 500 kHz; B = 5 kHz Vno(rms) – tbf – µV

D.C. output offset voltage (at Rs = 5Ω) ∆V – – 70 mV

input impedance (at Rs = ∞) Zi – – – MΩ

input bias current Ii – 40 – nA

Stereo applications; see Fig 5Output power; note 1

Vp = 3.0V; dtot = 10% Po – 35 – mW

Vp = 4.5V; dtot = 10% Po – 75 – mW

Voltage gain Gv 24.5 26 27.5 dB

Noise output voltage (r.m.s. value)

Rs = 5Ω; f = 1 kHz; Vno(rms) – 100 – µV

Rs = 0Ω; f = 500 kHz; B = 5 kHz Vno(rms) – tbf – µV

Channel separation

Rs = 0Ω; f = 1 kHz α 30 40 – dB

input impedance (at Rs = ∞) Zi 2 – – MΩ

input bias current Ii – 20 – nA

CHARACTERISTICSVp = 3V; f = 1 kHz; RL = 32 Ω; Tamb = 25 oC; unless otherwise specified

Note1.Output power is measured directly at the output pins of the IC. It is shown as a function of the supply voltage in

Fig. 2 (BTL application) and Fig. 3 (stereo application).


71

SDA9488X - SDA9588XPTP Processor

Pin Configuration

Pinning


72

Pin Configuration


73

Block Diagram


74

Pin No. Pin Name Type Connection Short DescriptionPQFP (‹f not used)80-pin

1 B1/CB1IN IN VREF Blue1/Cb1 Analog Component Input

2 G1/Y1IN IN VREF Green1/Y1 Analog Component Input

3 R1/CR1IN IN VREF Red1/Cr1 Analog Component Input

4 B2/CB21N IN VREF Blue2/Cb2 Analog Component Input

5 G2N21N IN VREF Green2/Y2 Analog Component Input

6 R2/CR21N IN VREF Red2/Cr2 Analog Component Input

7 ASGF X Analog Shield GNDF8 FFRSTWIN IN LV or GNDD FIFO Reset Write Input**

9 VSUPCAP OUT X Digital Decoupling Circuitry Supply Voltage

10 VSUPD V SUPPLYD X Supply Voltage, Digital Circuitry

11 GNDD, SUPPLYD X Ground, Digital Circuitry

12 GNDCAP OUT X Digital Decoupling Circuitry GND

13 SCL IN/OUT X I2C Bus Clock

NC = not connectedLV = if not used, leave vacantX = obligatory; connect as described in circuit diagramSUPPLYA = 4.75...5.25 V, SUPPLYD = 3.15...3.45 V

VPC323xDMulti standard Video Decoder


80-Pin Plastic Quad Flat Package(PQFP80)Weight approximately 1.61 gDimensions in mm

SPECIFICATIONS

Outline Dimensions


75


14 SDA IN/OUT X 12C Bus Data

15 RESQ IN X Reset Input, Active Low

16 TEST IN GNDD Test Pin, connect to GNDD17 VGAV IN GNDD VGAV Input

18 YCOEQ IN GNDD Y/C Output Enable Input, Active Low

19 FFIE OUT LV FIFO Input Enable

20 FFWE OUT LV FIFO Write Enable

21 FFRSTW OUT LV FIFO Reset Write/Read

22 FFRE OUT LV FIFO Read Enable

23 FFOE OUT LV FIFO Output Enable

24 CLK20 IN/OUT LV Main Clock Output 20.25 MHz

25 GNDPA OUT X Pad Decoupling Circuitry GND

26 VSUPPA OUT X Pad Decoupling Circuitry Supply Voltage

27 LLC2 OUT LV Double Clock Output

28 LLC1 IN/OUT LV Clock Output

29 VSUPLLC SUPPLYD X Supply Voltage, LLC Circuitry

30 GNDLLC SUPPLYD X Ground, LLC Circuitry

31 Y7 OUT GNDY Picture Bus Luma (MSB)

32 Y6 OUT GNDY Picture Bus Luma



35 GNDY SUPPLYD X Ground, Luma Output Circuitry

36 VSUPY SUPPLYD X Supply Voltage, Luma Output Circuitry




40 YO OUT GNDY Picture Bus Luma (LSB)

41 C7 OUT GNDC Picture Bus Chroma (MSB)

42 C6 OUT GNDC Picture Bus Chroma



45 VSUPC SUPPLYD X Supply Voltage, Chroma Output Circuitry

46 GNDSC SUPPLYD X Ground, Chroma Output Circuitry



49 C1 OUT GNDC Picture Bus Chroma (LSB)

50 CO OUT LV Interlace Output

51 VSUPSY SUPPLYD X Ground, Sync Pad Circuitry

52 VSUPSY SUPPLYD X Supply Voltage, Sync Pad Circuitry

53 INTLC OUT LV Interlace Output

54 AVO OUT LV Active Video Output

55 FSY/HC/HSYA OUT LV Front Sync/Horizontal Clamp Pulse/Front-

End Sync/Horizontal Sync Output**

56 MSY/HS IN/OUT LV Main Sync/Horizontal Sync Output

57 VS OUT LV Vertical Sync Pulse

58 FPDAT/VSYA IN/OUT LV Front-End/Back-End Data/Front-End

VerticalSync Output**


76


59 VSTBY SUPPLYA X Standby Supply Voltage

60 CLK5 OUT LV CCU 5 MHz Clock Output

62 XTAL1 IN X Analog Crystal Input

63 XTAL2 OUT X Analog Crystal Output

64 ASGF X Analog Shield GNDF65 GNDF SUPPLYA X Ground, Analog Front-End

66 VRT OUTPUT X Reference Voltage Top, Analog

67 I2CSEL IN X I2C BUS Address Select

68 ISGND SUPPLYA X Signal Ground for Analog Input, connect to

GNDF

69 VSUPF SUPPLYA X Supply Voltage, Analog Front-End

70 VOUT OUT LV Analog Video Output

71 CIN IN LV* Chroma I Analog Video 5 Input

72 VIN1 IN VRT* Video 1 Analog Input

73 VIN2 IN VRT Video 2 Analog Input




77

Pin 24 - Main Clock Output CLK20This is the 20.25 MHz main clock output.Pin 25 - Ground, Analog Pad Circuitry GNDPAPin 26 - Supply Voltage, Analog Pad Circuitry VSUPPAThis pin is connected with 47 nF/1.5 nF to GNDPA,Pin 27 - Double Output Clock, LLC2Pin 28 - Output Clock, LLC1This is the clock reference for the luma, chroma, andstatus outputs.Pin 29 - Supply Voltage, LLC Circuitry VSUPLLCThis pin is connected with 68 nF to GNDLLCPin 30 - Ground, LLC Circuitry GNDLLCPins 31 to 34, 37 to 40 - Luma Outputs Y7 - Y0These output pins carry the digital luminance data. Theoutputs are clocked with the LLC1 clock. In ITUR656mode, the Y/C data is multiplexed and clocked withLLC2 clock.Pin 35- Ground, Luma Output Circuitry GNDYThis pin is connected with 68 nF to GNDYPin 36 - Supply Voltage, Luma Output Circuitry VSUPYPins 41 to 44, 47 to 50 - Chroma Outputs C7-C0These outputs carry the digital C, Cb chrominance data.The outputs are clocked with the LL1 clock. The C, Cbdata is sampled at half the clock rate and multiplexed.The Cr Cb multiplex is reset for each TV line. In ITUR656mode, the chroma outputs can be tri-stated.Pin 45 - Supply Voltage, Chroma Output CircuitryVSUPCThis pin is connected with 68 nF to GNDCPin 46 - Ground, Chroma Output Circuitry GNDCPin 51 - Ground, Sync Pad Circuitry GNDSYPin 52 - Supply Voltage, Sync Pad Circuitry VSUPSYThis pin is connected with 47 nF/1.5 nF to GNDSYPin 53 - Interlace Output, INTLCThis pin supplies the interlace information, 0 indicates firstfield, 1 indicates second field.Pin 54 - Active Video Output, AVOThis pin indicates the active video output data. The signalis clocked with the LLC1 clock.Pin 55 - Front Sync/Horizontal Clamp Pulse/Front-EndHorizontal Sync Output, FSY/HC/HSYAThis signal can be useda) to clamp an external video signal, that is synchronousto the input signal. The timing is programmable orb) to synchronize an external video horizontally, that isasynchronous to the input video and stored in an externalmemory. The timing is fixed.In DIGIT3000 mode, this pin supplies the front sync infor-mation.Pin 56 - Main Sync/Horizontal Sync Pulse MSY/HS

This pin supplies the horizontal sync pulse informationin line-locked mode. In DIGIT3000 mode, this pin is themain sync input.Pin 57 - Vertical Sync Pulse, VSThis pin supplies the vertical sync signal.Pin 58 - Front-End/Back-End Data/Front-End VerticalSync Output FPDAT/VSYAIn DIGIT3000 mode, this pin interfaces to the DDP 331xback-end processor. The information for the deflection dri-ves and for the white drive control, i. e. the beam currentlimiter, is transmitted by this pin.In LLC mode, this signal can be used to synchronize anexternal video vertically, that is asynchronous to the inputvideo and stored in an external memory. The timing isfixed.If not used, this pin is connected with 10kΩ to VSUPSYPin 59 - Standby Supply Voltage VSTDBYIn standby mode, only the clock oscillator is active, GNDFshould be ground reference. Please activate RESQ beforepowering-up other suppliesPin 60 - CCU 5 MHz Clock Output CLK5This pin provides a clock frequency for the TV micro-con-troller, e.g. a CCU 3000 controller. It is also used by theDDP 331x display controller as a standby clock.Pins 62 and 63 - XTAL1 Crystal Input and XTAL2 CrystalOutputThese pins are connected to an 20.25 MHz crystal oscilla-tor which is digitally tuned by integrated shunt capaci-tances. The CLK20 and CLK5 clock signals are derivedfrom this oscillator. An external clock can be fed intoXTAL1. In this case, clock frequency adjustment must beswitched off.Pin 65 - Ground, Analog Front-End GNDFPin 66 - Reference Voltage Top VRTVia this pin, the reference voltage for the A/D convertersis decoupled. The pin is connected with 10 µF/47 nF tothe Signal Ground Pin.Pin 67 - I2C Bus address select I2CSELThis pin determines the 12C bus address of the IC.Pin 68 - Signal GND for Analog Input ISGNDThis is the high quality ground reference for thevideo input signals.Pin 69 - Supply Voltage, Analog Front-End VSUPFThis pin is connected with 220 nF/1.5 nF/390 pF to GNDFPin 70 - Analog Video Output, VOUTThe analog video signal that is selected for the main(luma, CVBS) ADC is output at this pin. An emitter fol-lower is required at this pin.Pin 71 - Chroma Input CINThis pin is connected to the S-VHS chroma signal. Aresistive divider is used to bias the input signal to the

middle of the converter input range. CIN can only be con-nected to the chroma (Video 2) A/D converter. The signalmust be AC-coupled.Pins 72-75 - Video Input 1-4These are the analog video inputs. A CVBS or S-VHSluma signal is converted using the luma (Video 1) ADconverter. The VIN1 input can also be switched to thechroma (Video 2) ADC. The input signal must be AC-cou-pled .Pin 76 - Supply Voltage, Analog Component InputsFront-End VSUPAIThis pin is connected with 220 nF/1.5 nF/390 pF toGNDAIPin 77 - Ground, Analog Component Inputs Front-End

GNDAIPin 78 - Reference Voltage Top VREFVia this pin, the reference voltage for the analog compo-nent A/D converters is decoupled. The pin is connectedwith 10 µF/47 nF to the Analog Component Signal GroundPin.Pin 79 - Fast Blank Input FB1INThis pin is connected to the analog fast blank signal. Itcontrols the insertion of the RGB1/YCrCb1 signals. Theinput signal must be DC-coupled.Pin 80 - Signal GND for Analog Component InputsAISGNDThis is the high quality ground reference for the compo-nent input signals.


78

I2CSEL I2C Add.

GNDF 88/89 hexVRT 8C/8D hexVSUPF 8E/8F hex

VPC 323xD I2C address select


Analog Video Front-EndThis block provides the analog interfaces to all videoinputs and mainly carries out analog-to-digital conversionfor the following digital video processing. A block diagramis given in Fig. 2-1.Most of the functional blocks in the front-end are digitallycontrolled (clamping, AGC, and clock-DCO). The controlloops are closed by the Fast Processor (‘FP’) embeddedin the decoder.

2.1.1. Input SelectorUp to five analog inputs can be connected. Four inputsare for composite video or S-VHS luma signal. Theseinputs are clamped to the sync back porch and are ampli-fied by a variable gain amplifier. One input is for connec-tion of S-VHS carrier chrominance signal. This input is

internally biased and has a fixed gain amplifier. A secondS-VHS chroma signal can be connected to video-inputVIN1.

ClampingThe composite video input signals are AC coupled to theIC. The clamping voltage is stored on the coupling capaci-tors and is generated by digitally controlled currentsources. The clamping level is the back porch of the videosignal. S-VHS chroma is also AC coupled. The input pinis internally biased to the center of the ADC input range.

Automatic Gain ControlA digitally working automatic gain control adjusts the mag-nitude of the selected baseband by +6/-4.5 dB in 64 loga-rithmic steps to the optimal range of the ADC.The gain of the video input stage including the ADC is213 steps/V with the AGC set to 0 dB.


79

Analog-to-Digital ConvertersTwo ADCs are provided to digitize the input signals. Eachconverter runs with 20.25 MHz and has 8 bit resolution.An integrated bandgap circuit generates the required ref-erence voltages for the converters. The two ADCs are ofa 2-stage subranging type.

Digitally Controlled Clock OscillatorThe clock generation is also a part of the analog frontend. The crystal oscillator is controlled digitally by thecontrol processor; the clock frequency can be adjustedwithin ±150 ppm.

Analog Video OutputThe input signal of the Luma ADC is available at the ana-log video output pin. The signal at this pin must bebuffered by a source follower. The output voltage is 2 V,thus the signal can be used to drive a 75 Ω line.The magnitude is adjusted with an AGC in 8 steps togeth-er with the main AGC.


80

ADAPTIVE COMB FILTERThe 4H adaptive comb filter is used for high-quality lumi-nance/chrominance separation for PAL or NTSC compos-ite video signals. The comb filter improves the luminanceresolution (bandwidth) and reduces interferences likecross-luminance and cross-color. The adaptive algorithmeliminates most of the mentioned errors without introduc-ing new artifacts or noise.A block diagram of the comb filter is shown in Fig. 2-2.The filter uses four line delays to process the informationof three video lines. To have a fixed phase relationship ofthe color subcarrier in the three channels, the systemclock (20.25 MHz) is fractionally locked to the color sub-carrier. This allows the processing of all color standardsand substandards using a single crystal frequency.The CVBS signal in the three channels is filtered at thesubcarrier frequency by a set of bandpass/notch filters.The output of the three channels is used by the adaptionlogic to select the weighting that is used to reconstruct theluminance/chrominance signal from the 4 bandpass/notchfilter signals. By using soft mixing of the 4 signals switch-ing artifacts of the adaption algorithm are completely sup-pressed.The comb filter uses the middle line as reference, there-fore, the comb filter delay is two lines. If the comb filter isswitched off, the delay lines are used to pass theluma/chroma signals from the A/D converters to theluma/chroma outputs. Thus, the processing delay isalways two lines.In order to obtain the best-suited picture quality, the userhas the possibility to influence the behavior of the adap-tion algorithm going from moderate combing to strongcombing. Therefore, the following three parameters maybe adjusted:- HDG (horizontal difference gain)- VDG (vertical difference gain)- DDR (diagonal dot reducer)

HDG typically defines the comb strength on horizontaledges. It determines the amount of the remaining cross-luminance and the sharpness on edges respectively. AsHDG increases, the comb strength, e. g. cross luminancereduction and sharpness, increases.VDG typically determines the comb filter behavior on verti-cal edges. As VDG increases, the comb styength, e. g.the amount of hanging dots, decreases.After selecting the combfilter performance in horizontaland vertical direction, the diagonal picture performancemay further be optimized by adjusting DDR. As DDRincreases, the dot crawl on diagonal colored edges isreduced.To enhance the vertical resolution of the picture, the VPCprovides a vertical peaking circuitry. The filter gain isadjustable between 0 – +6 dB and a coring filter sup-presses small amplitudes to reduce noise artifacts. In rela-tion to the comb filter, this vertical peaking widely con-tributes to an optimal two-dimensional resolution homo-geneity.

COLOR DOCEDERIn this block, the standard luma/chroma separation andmulti-standard color demodulation is carried out. The colordemodulation uses an asynchronous clock, thus allowinga unified architecture for all color standards.A block diagram of the color decoder is shown in Fig. 2-4.The luma as well as the chroma processing, is shownhere. The color decoder also provides several specialmodes, e.g. wide band chroma format which is intendedfor S-VHS wide bandwidth chroma. Also, filter settings areavailable for processing a PAL+ helper signal.If the adaptive comb filter is used for luma chroma sepa-ration, the color decoder uses the S-VHS mode process-ing. The output of the color decoder is YCrCb in a 4:2:2format.


81

If-CompensationWith off-air or mistuned reception, any attenuation at high-er frequencies or asymmetry around the color subcarrieris compensated. Four different settings of the If-compen-sation are possible:- flat (no compensation)- 6 dBloctave- 12 dB/octave- 10 dB/MHzThe last setting gives a very large boost to high frequen-cies. It is provided for SECAM signals that are decodedusing a SAW filter specified originally for the

DemodulatorThe entire signal (which might still contain luma) is quad-rature - mixed to the baseband. The mixing frequency isequal to the subcarrier for PAL and NTSC, thus achievingthe chroma demodulation. For SECAM, the mixing fre-

quency is 4.286 MHz giving the quadrature basebandcomponents of the FM modulated chroma. After themixer, a lowpass filter selects the chroma components; adownsampling stage converts the color difference signalsto a multiplexed half rate data stream.The subcarrier frequency in the demodulator is gener-ated by direct digital synthesis; therefore, substandardssuch as PAL 3.58 or NTSC 4.43 can also be demodulat-ed.

Chrominance FilterThe demodulation is followed by a lowpass filter for thecolor difference signals for PAL/NTSC. SECAM requires amodified lowpass function with bell filter characteristic. Atthe output of the lowpass filter, all luma information iseliminated.The lowpass filters are calculated in time multiplex for thetwo color signals. Three bandwidth settings (narrow, nor-mal, broad) are available for each standard. For PAL-INTSC, a wide band chroma filter can be selected. Thisfilter is intended for high bandwidth chroma signals, e.g. anonstandard wide bandwidth S-VHS signal.

Frequency response of chroma IF-compensation


82

Frequency DemodulatorThe frequency demodulator for demodulating the SECAMsignal is implemented as a CORDIC-structure. It calcu-lates the phase and magnitude of the quadrature compo-nents by coordinate rotation.The phase output of the CORDIC processor is differentiat-ed to obtain the demodulated frequency. After the deem-phasis filter, the Dr and Db signals are scaled to standardCrCb amplitudes and fed to the crossover-switch .

Burst Detection/Saturation ControlIn the PAL/NTSC system the burst is the reference for thecolor signal. The phase and magnitude outputs of theCORDIC are gated with the color key and used for con-trolling the phase-locked loop (APC) of the demodulatorand the automatic color control (ACC) in PAL / NTSC.The ACC has a control range of +30 ... -6 dB.Color saturation is adjustable independently of the colorstandard. In PAL/NTSC it is used as reference for theACC. In SECAM the necessary gains are calculated auto-matically.For SECAM decoding, the frequency of the burst is mea-sured. Thus, the current chroma carrier frequency can beidentified and is used to control the SECAM processing.The burst measurements also control the color killer oper-ation; they are used for automatic standard detection aswell.

Color Killer OperationThe color killer uses the burst-phasel burst-frequencymeasurement to identify a PAL/NTSC or SECAM color

signal. For PAL / NTSC, the color is switched off (killed)as long as the color subcarrier PLL is not locked. ForSECAM, the killer is controlled by the toggle of theburst frequency. The burst amplitude measurement isused to switch off the color if the burst amplitude is belowa programmable threshold. Thus, color will be killed forvery noisy signals. The color amplitude killer has a pro-grammable hysteresis.

Automatic Standard RecognitionThe burst-frequency measurement is also used for auto-matic standard recognition (together with the status ofhorizontal and vertical locking) thus allowing a completelyindependent search of the line and color standard of theinput signal. The following standards can be distin-guished:PAL B,G,H,I; NTSC M; SECAM; NTSC 44; PAL M;PAL N; PAL 60For a preselection of allowed standards, the recognitioncan be enabled/disabled via I2C bus for each standardseparately.If at least one standard is enabled, the VPC 323xDchecks regularly the horizontal and vertical locking of theinput signal and the state of the color killer. If an errorexists for several adjacent fields a new standard search isstarted. Depending on the measured line number andburst frequency the current standard is selected.For error handling, the recognition algorithm delivers thefollowing status information:- search active (busy)- search terminated, but failed- found standard is disabled- vertical standard invalid

Frequency response of chroma filters


83

PAL Compensation / 1-H Comb FilterThe color decoder uses one fully integrated delay line.Only active video is stored.The delay line application depends on the color standard:- NTSC: 1-H comb filter or color compensation- PAL: color compensation- SECAM: crossoverswitch

In the NTSC compensated mode, the colorsignal is averaged for two adjacent lines. Thus,cross-color distortion and chroma noise is reduced. Inthe NTSC 1-H comb filter mode, the delay line is in thecomposite signal path, thus allowing reduction of cross-color components, as well as cross-luminance. The lossof vertical resolution in the luminance channel is com-pensated by adding the vertical detail signal withremoved color information. If the 4H adaptive comb filteris used, the 1-H NTSC comb filter has to be deselected.

NTSC color decoding options

PAL color decoding options

SECAM color decoding


84

Luminance Notch FilterIf a composite video signal is applied, the color infer-mation is suppressed by a programmable notch filter. Theposition of the filter center frequency depends on the sub-carrier frequency for PAL/NTSC. For SECAM, the notch isdirectly controlled by the chroma carrier frequency. Thisconsiderably reduces the cross-luminance. The frequencyresponses for all three systems are shown in Fig. 2-9.

Skew FilteringThe system clock is free-running and not locked to the TVline frequency. Therefore, the ADC sampling pattern isnot orthogonal. The decoded YCrCb signals are convert-ed to an orthogonal sampling raster by the skew filters,which are part of the scaler block.The skew filters are controlled by a skew parameter andallow the application of a group delay to the input signalswithout introducing waveform or frequency response dis-tortion.The amount of phase shift of this filter is controlled by thehorizontal PLL1. The accuracy of the filters is 1/32 clocksfor luminance and 1/4 clocks for chroma. Thus the 4:2:2YCrCb data is in an orthogonal pixel format even in thecase of nonstandard input signals such as VCR.

COMPONENT INTERFACE PROCESSOR CIPThis block (see Fig. 2-10) contains all the necessary cir-cuitry dedicated to external analog components(YCrCb_cip) such as RGB or YCrCb signals from DVDplayers, or other RGB sources with Fast Blank for realtime insertion on the main picture (YCrCb_main).

Component Analog Front-EndVPC323xD provides two analog RGB/YCrCb input ports,one with Fast Blank capability and one without. Analogcomponent signals contain high-frequency components(e. g. OSD) and/or high-frequency clock residues. Thus, itis recommended to implement analog anti-alias low-passfilters on each input, including FB (e. g. -3 dB at 5...6MHz). While all signals are coupled by 220 nF clampingcapacitors, the Fast Blank input requires DC coupling.The selected signal channel is further converted into adigital form by three high-quality ADCs running at 20.25MHz with a resolution of 8 bit. The FB input is digitizedwith a resolution of 6 bit.Note: The VPC 323xD is synchronized always by themain CVBS/Y ADC input. In component mode, the syncsignal has to be fed to this input accordingly.

MatrixThe RGB signals are converted to the YCrCb format bya matrix operation:

Y = 0.299R + 0.587G + 0.114B(R-Y)= 0.701R - 0.587G - 0.114B

(B-Y)=-0.299R - 0.587G + 0.886BIn case of YCrCb input the matrix is bypassed.

Component YCrCb ControlThe VPC 323xD supports the following picture adjustmentparameters on the component signal:-0≤ contrast ≤63/32- –128 ≤ brightness ≤ 127- 0 ≤ saturation Cr ≤ 63/32- 0 ≤ saturation Cb ≤ 63/32- –20 ≤ tint ≤ 20 degrees

Fig. 2-9: Frequency responses of the lumanotch filter for PAL, NTSC, SECAM


85

Table 2-1 shows the settings to-achieve exact levelmatching between YCrCb_cip and YCrCb_main channel.

Table 2-1: Standard picture settings

Note: R, G, B, Cr, Cb, = 0.7 Vpp, Y(+ sync) 1 Vpp

SoftmixerAfter an automatic delay matching, the component sig-nals and the upsampled main video signal are gatheredonto a unique YC,Cb channel by means of a versatile4:4:4 softmixer (see also Fig. 2-10).The softmixer circuit consists of a Fast Blank (FB) pro-cessing block supplying a mixing factor k (0...64) to a highquality signal mixer achieving the output function:YCrCb_mix=( k*YCrCb_main+ (64-k)*YCrCb_cip )/64The softmixer supports several basic modes that areselected via I2C bus.

Static Switch ModeIn its simplest and most common application the soft-mixer is used as a static switch between YCrCb_mainand YCrCb_cip. This is for instance the adequate way tohandle a DVD component signal.The factor k is clamped to 0 or 64, hence selectingYCrCb_main or the component input YCrCb_cip.

Static Mixer ModeThe signal YCrCb_main and the component signalYCrCb_cip may also be statically mixed. In this environ-ment, k is manually controlled via I2C registers FBGAINand FBOFFS according to the following expression:

k = FBGAIN*(31-FBOFFS) + 32All the necessary limitation and rounding operation are-built-in to fit the range: 0 ≤ k ≤ 64.In the static mixer mode as well as in the previously men-tioned static switch mode, the softmixer operates indepen-dently of the analog Fast Blank input.

Dynamic Mixer ModeIn the dynamic mixer mode, the mixer is controlled by theFast Blank signal. The VPC 323xD provides a linear mix-ing coefficient

k=kl = FBGAIN*(FB-FBOFFS) + 32(FB is the digitized Fast Blank), and a non-linear mixingcoefficient knl=F(kl), which results from a further non-lin-ear processing of kl.While the linear mixing coefficient is used to insert a full-screen video signal, the non-linear coefficient is well-suit-ed to insert Fast Blank related signals like text.The non-linear mixing reduces disturbing effects likeover/undershoots at critical Fast Blank edges.

Input contrast brightness satCr satCb

format

RGB 27 68 29 23YCrCb 27 68 40 40

Y/C processing

Componentprocessing

VIDEO

RGB/YCrCb

Fig. 2-10: Block diagram of the component mixer

YCrCb mainYCrCb -mix

mixer

YCrCb-cip


86

GENERAL DESCRIPTIONThe OKI MSM54V12222A is a high performance 3M bits,256K X 12 bits, Field Memory especially de-signed forhigh-speed serial access applications such as HDTVs,conventional NTSC TVs, VTRs, digital movies and Multi-media systems. MSM54V12222A is a FRAM for wide orlow end use as general com-modity TVs and VTRs, exclu-sively. MSM54V12222A is not designed for the other useor high end use as medical systems, professional graph-ics systems require long time picture storage, data stor-age systems and others. More than twoMSM54V12222As can be cascaded directly without anydelay devices among the MSM54V12222As. ( Cascadingof MSM54V12222A provides larger storage depth or alonger delay.)Each of the 12-bits planes has separate serial write andread ports that employ independent control clocks to sup-port asynchronous read and write operations. Differentclock rates are also supported that allow alternate datarates between write and read data streams.The MSM54V12222A provides high speed FIFO, First-InFirst-Out, operation without external refreshing:MSM54V12222A refreshes its DRAM storage cells auto-matically, so that it appears fully static to the users.Moreover, fully static type memory cells and decoders forserial access enable the serial access operation refreshfree, so that serial read and/or write control clock can behalted high or low for any time as long as the power is on.Internal conflicts of any memory access and refreshingoperation are prevented by special arbitration logic.

The MSM54V12222A's function is simple like that of adigital delay device whose delay-bit-length is easily set byreset timing. The delay length, number of read delayclocks between write and read, is determined by external-ly controlled write and read reset timings.Additional SRAM serial registers, or line buffers, for theinitial access of 256X12 bits enable high speed first-bit-access with no clock delay just after the write or readreset timings.In addition to cascade capability, MSM54V12222A haswrite mask function or input enable function (IE), andread- data skipping function or output enablefunction(OE). The differences between write enable (WE)and input enable (IE), and between read enable (RE) andoutput enable (OE) are that WE and RE can stop serialwrite/read address increments but IE and OE can not stopthe increment when write/read clocking is continuouslyapplied to MSM54V12222A. The input enable (IE) func-tion allows the user towrite into selected locations of the memory only, leavingthe rest of the memory contents unchanged. This facili-tates data processing as "picture in picture" on a TVscreen simply.The MSM54V12222A is similar in operation and function-ality to OKI 1M bits Field memory MSM51V4222C and 2Mbits Field memory MSM51V8222A. ThreeMSM51V4222Cs or one MSM51V4222C plus oneMSM51V8222A can be replaced simply by oneMSM54V12222A.

FEATURES• Signale power supply : 3.3V±0.3V• 512 Rows X 512 Column X 12 bits• Fast FIFO (First-In First-Out) Operation• High Speed Asynchronous Serial Access• Read/Write Cycle Time 30 ns/40 ns• Access Time 30 ns/35 ns• Direct Cascading Capability• Write Mask Function (Input Enable Control)

• Data Skipping Function (Output Enable Cotrol)• Self Refresh (No refresh control is required)• Packageoptions:44Pin 400mil plastic TSOP (Type II ) (TSOP II 44-P-400-0.80-K) (Product:MSM54V12222A-xxTS-K)40Pin 400mil Plastic SOJ (SOJ40-P-400-1.27)(Product:MSM54V12222A-xxJS)xx indicates speed rank.

MSM54V12222AOKI Semiconductor, 262,214 Words x 12 bits FIELD MEMORY

Product Families


87

Pin Configuration (top view)


88

Block Diagram


89

INTRODUCTIONThe DDP 3310B is a single-chip digital Display andDeflection Processor designed for high-quality back-endapplications in 100 / 120-Hz TV sets with 4:3- or 16:9 pic-ture tubes. The IC can be combined with members of theDIGIT 3000 IC family (VPC 32xx,TPU 3040), or it can beused with third-party products.The IC contains the entire digital video component anddeflection processing and all analog interface compo-nents.

Main FeaturesVideo processing

– linear horizontal scaling (0.25 … 4)– non-linear horizontal scaling “panoramavision”– dynamic peaking– soft limiter (gamma correction)– color transient improvement– programmable RGB matrix– picture frame generator– two analog RGB/Fast-Blank inputs

Deflection processing

– scan velocity modulation output– high-performance H/V deflection– EHT compensation for vertical / East/West– soft start/stop of H-Drive– vertical angle and bow– differential vertical output– vertical zoom via deflection– horizontal and vertical protection circuit– adjustable horizontal frequency for VGA/SVGA dis-play

Miscellaneous– selectable 4:1:1 / 4:2:2 YCrCb input

– selectable 27 / 32-MHz line-locked clock input– crystal oscillator for horizontal protection– automatic picture tube adjustment (cutoff, white-drive)– single 5-V power supply– hardware for simple 50/60-Hz to 100/ 120-Hz conversion

(display frequency doubling)– two I2C-controlled PWM outputs– beam current limiter

DDP3310BDigital Deflection and RGB Processor

Hori-zontalScaler

Y FeaturesC Features

DigitalRGB

Matrix

3 x DAC(10 Bit)

Tube-Control

AnalogRGB

Switch

ScanVelocity

Modulation

DACs

DisplayFrequencyDoubling

H / VDeflectionSecurity

Unit

PictureFrame

Generator

ClockGen.

I2CInter-face

PWMMeasure-

mentADC

YCrCb4:2:2/4:1:1

Line-LockedClock27/32 MHz

SDA/SCL

PWM1 & 2

SenseInput

2H / 2V(1H/1V)

HFlyback

RGBOut

2xRGB/FBIn

SVM

H DriveV & E/W

FIFOControlling


90


91

FEATURES High bandwidth and high slew rate Black-current measurement output for Automatic

Black-current Stabilization (ABS) Two cathode outputs; one for DC currents, and one

for transient currents A feedback output separated from the cathode outputs Internal protection against positive appearing

Cathode-Ray Tube (CRT) flashover discharges ESD protection Simple application with a variety of colour decoders Differential input with a designed maximum common

mode input capacitance of 3 pF, a maximum differen-tial mode input capacitance of 0.5 pF and a differentialinput voltage temperature drift of 50 µV/K

Defined switch-off behaviour.

GENERAL DESCRIPTIONThe TDA6111Q is a video output amplifier with 16 MHzbandwidth. The device is contained in a single in-line 9-pin medium power (DBSSMPF) package, using high-volt-age DMOS technology, intended to drive the cathode of acolour CRT.

QUICK REFERENCE DATA

vDDH high level supply voltage 0 - 250 VvDDL low levelsupply voltage 0 - 14 WIDDH quiescent high voltage supply current Voc = 0.5VDDH 7.0 9.0 11.0 mAIDDL quiescent low voltage supply current Voc = 0.5VDDH 5.0 6.8 8.0 mAVi input voltage 0 - VDDL V

Voc, Vfb output voltage VDDL - VDDH V

Tstg storage temperature -55 - +150 oC

Tamb operating ambient temperature -20 - +65 oC

SYMBOL PARAMETER CONDITIONS Min. Typ. Max. Unit

Pin Symbol Function1 Vip non - inverting voltage input2 vDDL supply voltage LOW3 vin inverting voltage input4 GND ground, substrate5 Iom black current measurement output6 vDDH supply voltage HIGH7 Vcn cathode transient voltage output8 Voc cathode DC voltage output9 Vfb feedback voltage output

PINNING

1

2

3

4

5

6

7

Vip

vDDL

vin

GND

Iom

vDDH

Vcn

U

8Voc

9Vfb

TDA6111Q

Pin Configuration

TDA6111QVideo Output Amplifier


92

LIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 134). Voltages measured with respect to GND (pin 4); cur-rents as specified in A; unless otherwise specified.

vDDH high level supply voltage 0 250 VvDDL low levelsupply voltage 0 14 WVi input voltage 0 VDDL VVIDM differential mode input voltage -6 +6 VVom measurement output voltage 0 VDDL

Voc cathode output voltage VDDL VDDH VVfb feedback output voltage VDDL VDDH VIin, Iip input current 0 1 mAIcosmL low-non repetitive peak cathode output current flashover discharge = 100µC 0 5 AIcosmH high-non repetitive peak cathode output current flashover discharge = 100nC 0 10 APtot total power dissipation 0 4 WTstg storage temperature -55 +150 oCTj junction temperature -20 +150 oCVes electrostatic handling

human body model (HBM) - >1500 Vmachine model (MM) - >400 V

SYMBOL PARAMETER CONDITIONS Min. Max. Unit

A-Block diagram

supply voltageinput HIGH

fedbackoutput

6 9

7V

MIRROR

FOLLOWERS

Vbias

TDA6111Q

cathodetransientoutput

cathodeDC output

black currentmeasurementoutput

CURRENTSOURCE

MIRROR

5

8

7

MIRROR

Cpar

MIRROR

DIFFERENTIALSTAGE

-

+

3

1

ground(substrate)

4 2

supply voltageinput LOW

invertinginput

non-invertinginput


93

Cathode outputThe cathode output is protected against peak currents (ca-used by positive voltage peaks during high-resistanceflash) of 5 A maximum with a charge content of 100 µC.The cathode is also protected against peak currents(caused by positive voltage peaks during low-resistanceflash) of 10 A maximum with a charge content of 100 nC.

Flashover protectionThe TDA6111Q incorporates protection diodes againstCRT flashover discharges that clamp the cathode outputpin to the VDDH pin. The DC supply voltage at the VDDH Pinhas to be within the operating range of 180 to 210 V to en-sure that the Absolute Maximum Rating for VDDH of 250 Vwill not be exceeded during flashover. To limit the diodecurrent, an external 680 R carbon high-voltage resistor inseries with the cathode output and a 2 kV spark gap are ne-eded (for this resistor-value, the CRT has to be connectedto the main PCB). This addition produces an increase in therise and fall times of approximately 5 ns and a decrease inthe overshoot of approximately 4%.

VDDH to GND must be decoupled:

1. With a capacitor >20 nF with good HF behaviour (e.g. foil). This capacitance must be

placed as close as possible to pins 6 and 4, but definitely within 5 mm.

2. With a capacitor >10 CIF on the picture tube base print (common for three output stages).

VDDL to GND must be decoupled:1. With a capacitor >20 nF with good HF behaviour

(e.g. ceramic). This capacitance must be placed asclose as possible to pins 2 and 4, but definitely wit-hin 10 mm.

Switch-off behaviourThe switch-off behaviour of the TDA6111Q is defined:when the bias current becomes zero, at VDDL (pin 2) lowerthan approximately 5 V, all the output pins(pins 7, 8 and 9) will be high.


94

1

2

3

4

5

6

7

14

13

12

11

10

9

8

DTC

PCS

RZI

SRC

OCI

FC2

SYN

U


VCC

OUT

GND

PVC

FC1

REF

N.C./PMO

Pin Symbol Function

1 OTC Off Time Circuit

2 PCS Primary Current Simulation

3 RZI Regulation and Zero Crossing Input

4 SRC Soft-Start and Regulation Capacitor

5 OCI Opto Coupler Input

6 FC2 Fault Comparator 2

7 SYN Synchronization Input

8 N.C./PMO Not Connected (TDA16846)

9 REF Reference Voltage and Current

10 FC1 Fault Comparator 1

11 PVC Primary Voltage Check

12 GND Ground

13 OUT Output

14 VCC Supply Voltage

TDA16846Controller For Switch Mode Power Supplies

The TDA16846 is suited for TV-, VCR-sets and SAT receivers. It also can be good used in PC monitors.The TDA 16847 is identical with TDA16846 but has an additional power measurement output (pin 8) which can be useda Temporary High Power Circuit.

Pin Definitions and Functions


95

-+

+

-+

+-

++

-

-+

+-

+-

+-

+- -

TDA16846 Block Diagrams

SYN

R7

R3

D4

KSY

R4

R6 D5

1V

9REF

N.C.

FC2

8

6

VCC

PVC

11

PrimaryVoltageCheck

3.5V

1.2V

G4

FC2

1

PVA

1.5V

G1

ED2

Error-Flipflop

1

S

RQ

R6x1/3

Fold Back Point Correction

5V

5V

5V3.5V

1

3

4

5

2

14

12

CS1

R2D2

D3

∞

30kΩ

15kΩControl Voltage

Limit

RSTC/RSTF

Off TimeComparator

ErorAmplifier

Buffer forControl Voltage

On TimeComparator

R8

75kΩ

OTC

RZI

OCI

PCS

VCC

GND

SRC

∞

∞

R1

20kΩ

5V

1.5V

16V 15.8V

1) The input with the lower voltage becomes operative

<25mV

ED1

D1StartupDiode

I1

&

∞

OvervoltageComparator

∞

∞

∞ ∞

∞

∞

∞

+

+

–

–

S

RG2

Zero CrossingSignal

Q

Supply VoltageComparator

G3

1V

10

FC1

OutputDriver

&OUT

13


96

ELECTRICAL CHARACTERISTICSAbsolute maximum ratings

All voltages listed are referenced to ground (0V, Vss) except where noted.

Supply Voltage at Pin 14 Vcc -0.3 17 V -

Voltage at Pin 1, 4, 5, 6, 7, 9, 10 - -0.3 6 V -

Voltage at Pin 2, 8, 11 - -0.3 17 V -

Voltage at Pin 3 RZI 6 V -

Current into Pin 3 -10 mA V3 < - 0.3V

Current into Pin 9 REF -1 - mA -

Current into Pin 13 OUT 100 mA V13 > - Vcc-100 mA V13 < - 0V

ESD Protection - - 2 kV MIIL STD 883C

methot 3015.6,

100 PF, 1500Ω

Storage Temperature Tstg -65 125 oC -

Operating Junction Temperature Tj - 125 oC -

Thermal Resistance RthJA - 110 K/W P-DIP-14-3

Junction-Ambient

Soldering Temperature - - 260 oC -

Soldering Time - - 10 s -

Parameter Symbol Limit Values Unit Remarks

Min. Typ.

Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.


97

Short Description of the Pin Functions

Pin Functions

1 A parallel RC-circuit between this pin and ground determines the ringing suppression time and the standby-frequency.

2 A capacitor between this pin and ground and a resistor between this pin and the positive terminal of the primary elcap quantifies the max. possible output power of the SMPS.

3 This is the input of the error amplifier and the zero crossing input. The output of a voltage divider between the control winding and ground is connected to this input. If the pulses at pin 3 exceed a 5 V threshold, the control voltage at pin 4 is lowered.

4 This is the pin for the control voltage. A capacitor has to be connected between this pin and ground. The value of this capacitor determines the duration of the softstart and the speed of the control.

5 If an opto coupler for the control is used, it's output has to be connected between this pin and ground. The voltage divider at pin 3 has then to be changed, so that the pulses at pin 3 are below 5 V.

6 Fault comparator 2: If a voltage > 1.2 V is applied to this pin, the SMPS stops.

7 If fixed frequency mode is wanted, a parallel RC circuit has to be connected between this pin and ground. The RC-value determines the frequency. If synchronized mode is wanted,sync pulses have to be fed into this pin.

8 Not connected (TDA16846). / This is the power measurement output of the Temporary High Power Circuit. A capacitor and a RC-circuit has to be connected between this pin and ground.

9 Output for reference voltage (5 V). With a resistor between this pin and ground the fault comparator 2 (pin 6) is enabled.

10 Fault comparator i: If a voltage > 1 V is applied to this pin, the SMPS stops.

11 This is the input of the primary voltage check. The voltage at the anode of the primary elcap has to be fed to this pin via a voltage divider. If the voltage of this pin falls below 1 V, the SMPS is switched off. A second function of this pin is the primary voltage depen-dent fold back point correction (only active in free running mode).

12 Common ground.

13 Output signal. This pin has to be connected across a serial resistor with the gate of the power transistor.

14 Connection for supply voltage and startup capacitor. After startup the supply voltage is produced by the control winding of the transformer and rectified by an external diode.


98

ORDER SCHEMATIC

Pin Connection

PART NUMBERS CTR-RANKING

TCDT1100/TCDT1100G >40%

TCDT1101/TCDT1101G 40 to 80%

TCDT1102/TCDT1102G 63 to 125%

TCDT1103/TCDT1103G 100 to 2000%

Suffix: G = Leadform 10.16 mm

FEATURESAccording to VDE 0884:• Rated impulse voltage (transient overvoltage)

VIOTM = 6 kV peak• Isolation test voltage (partial discharge test voltage)

Vpd = 1.6 kV• Rated isolation voltage (RMS includes DC)

VlOWM = 600 VRMS (848 V peak)• Rated recurring peak voltage (repetitive)

VIoRM = 600 VRMS• Creepage current resistance according to

VDE 0303/1EC 112Comparative Tracking Index: CTI = 275

• Thickness through insulation ≥ 0.75 mm

• Further approvals:BS 415, BS 7002, SETI: IEC 950,UL 1577: File No: E 76222

• Base not connected• CTR offered in 4 groups• Isolation materials according to UL94-VO• Pollution degree 2 (DIN/VDE 0110 / resp. IEC 664)• Climatic classification

55/100/21 (IEC 68 part 1)• Special construction:

Therefore extra low coupling capacity of typical0.2 pF, high Common Mode Rejection

• Low temperature coefficient of CTR

n.c C

6 5 4

E

A (+) C (–) n.c.

1 2 3

TCDT1100(G) SeriesOptocoupler with Phototransistor Output


99


Input (Emitter)Parameters Test Conditions Symbol Value Unit

Reverse voltage VR 5 V

Forward current IF 60 mA

Forward surge current tp ≤ 10µs IFSM 3 A

Power dissipation Tamb ≤ 25 oC Pv 100 mW

Junction temperature Tj 125 oC

Output (Detector)Parameters Test Conditions Symbol Value Unit

Collector emitter voltage VCEO 32 V

Emitter collector voltage VECO 7 V

Collector current IC 50 mA

Collector peak current tp/T = 0.5, tp ≤ 10ms ICM 100 mA

Power dissipation Tamb ≤ 25 oC Pv 150 mW

Junction temperature Tj 125 oC

CouplerParameters Test Conditions Symbol Value Unit

Isolation test voltage (RMS) VIO 3.75 kV

Total power dissipation Tamb ≤ 25 oC Ptot 250 mW

Ambient temperature range Tamb -55 to +100 oC

Storage temperature range Tstg -55 to +125 oC

Soldering temperature 2 mm from case t ≤ 10 s Tsd 260 oC


100

L4931 SeriesVery Low Drop Voltage Regulators With Inhibit

Schemat›c Diagram

• VERYLOW DROPOUT VOLTAGE (0.4V)• VERYLOW QUIESCENT CURRENT

(TYP. 50 µA IN OFF MODE, 600µA IN ONMODE)

• OUTPUT CURRENT UP TO 250 mA• LOGIC-CONTROLLED ELECTRONIC

SHUTDOWN• OUTPUT VOLTAGES OF 1.25; 1.5; 2.5; 2.7;

3; 3.3; 3.5; 4; 4.5; 4.7; 5; 5.2; 5.5; 6; 8; 12V• INTERNAL CURRENT AND THERMAL LIMIT• ONLY 2.2µF FOR STABILITY• AVAILABLEIN ± 1% (AB) OR 2% (C)

SELECTIONAT 25 oC• SUPPLY VOLTAGE REJECTION:

70db TYP. FOR 5V VERSION• TEMPERATURE RANGE: -40 TO 125 oC

DESCRIPTIONThe L4931 series are very Low Drop regulatorsavailable in TO-220, SO-8, DPAK, PPAK and TO-92 packages and in a wide range of output volt-ages.The very Low Drop voltage (0.4V) and the verylow quiescent current make them particularly suit-

able for Low Noise, Low Power applications andspecially in battery powered systems.In PPAK and SO-8 packages a Shutdown LogicControl function is available TTL compatible. Thismeans that when the device is used as a localregulator, it is possible to put a part of the boardin standby, decreasing the total power consump-tion. It requires only a 2.2 µF capacitor for stabilityallowing space and cost saving.


101

Connection Diagram (top view)


THERMAL DATA


102

L7800 SeriesPositive Voltage Regulators

BLOCK DIAGRAM

• OUTPUT CURRENT UP TO 1.5 A• OUTPUT VOLTAGESOF 5; 5.2; 6; 8; 8.5;

12; 15; 18; 24V• THERMAL OVERLOAD PROTECTION• SHORTCIRCUIT PROTECTION• OUTPUT TRANSITION SOA PROTECTION

DESCRIPTIONThe L7800 series of three-terminal positive regulators isavailable in TO-220 ISOWATT220 TO-3 and D2PAKpackages and several fixed output voltages, making ituseful in a wide range of applications.These regulatorscan provide local on-card regulation, eliminating the dis-tribution problems associated with single point regula-tion.Each type employs internal current limiting, thermal shut-down and safe area protection, making it essentiallyindestructible. If adequate heat sinking is provided, theycan deliver over 1A output current. Although designedprimarily as fixed voltage regulators, these devices canbe used with external components to obtain adjustablevoltages and currents.


103


104


105


106


107


108

STV9379AVertical Deflection Booster

Pin Connection

PACKAGEFEATURES• Power Amplifier• Flyback Generator• Thermal Protection• Output Current up to 2.6 App• Flyback Voltage up to 90V (on pin 5)• Suitable for DC Coupling Application

DESCRIPTIONDesigned for monitors and high performanceTVs, the STV9379A vertical deflection boosterdelivers flyback voltages close to 90V.The STV9379A operates with supplies up to42V and provides up to 2.6 APP output current

to drive the yoke.The STV9379A is inserted in HEPTAWATTpackage.


109

Block Diagram


110

ELECTRICAL CHARACTERISTICS V S =42V, T A =25°C, unless otherwise specified

APPLICATION CIRCUITS


111

APPLICATION CIRCUITS (CONTINUED)


112

M54HCT86 - M74HCT86Quad Exclusive or Gate

DESCRIPTION


INPUT AND OUTPUT EQUIVALENT CIRCUIT


113


PIN DESCRIPTION

TRUTH TABLE IEC LOGIC SYMBOL

SCHEMATIC CIRCUIT (Per Gate)


114

GENERAL DESCRIPTIONEnhanced performance, new generation, high voltage, high-speed switching npn transistor in a plastic full-pack enve-lope intended for use in horizontal deflection circuits of colour television receivers and p.c. monitors. Featuresexcepti-onal tolerance to base drive and collector current load variations resulting in a very low worst case dissipation.

QUICK REFERENCE DATA Symbol Parameter Conditions Typ. Max. Unit

Pin Description1 base

2 collector

3 emitter

case isolated

PINNING - SOT399 PIN CONFIGURATION SYMBOL

VCESM collector - emitter voltage peak value VBE = 0V – 1500 VVCEO collector - emitter voltage (open base) – 800 VIC collector current (DC) – 12 AICM collector current peak value – 30 AIB Base current (DC) – 8 AIBM Base current peak value – 12 mA-IBM Reverse base current peak value1 – 7 APtot Total power dissipation Ths ≤ 25 oC – 45 WTstg Storage temperature -55 150 oCTj Junction temperature – 150 oC

LIMITING VALUESLimiting values in accordance with the Absolute Maximum Rating System (IEC 134)

Symbol Parameter Conditions Typ. Max. Unit

THERMAL RESISTANCES

Rth j-hs Junction to heatsink with heatsink compound – 2.8 K/WRth j-a Junction to ambient in free air 35 – K/W

Symbol Parameter Conditions Typ. Max. Unit

BU4525AXSilicon Diffused Power Transistor

VCESM collector - emitter voltage peak value VBE = 0V – 1500 VVCEO collector - emitter voltage (open base) – 800 VIC collector current (DC) – 12 AICM collector current peak value – 30 APtot total power dissipation Ths ≤ 25 oC – 45 WVCEsat collector - emitter saturation voltage Ic = 9 A; IB = 2.25 A – 3.0 VICsat collector saturation current f = 16kHz 9.0 – A

f = 70kHz 7.0 – Atf fall time Icsat = 9.0 A; f = 16kHz 0.4 0.55 µs

Icsat = 7.0 A; f = 70kHz 0.15 – µs

1 Turn-off current.


115

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITVisol Repetitive peak voltage from R.H.≤ 65%; clean and dustfree – 2500 V

all three terminals to externalheatsink

Cisol Capaticance from T2 to f= 1 MHz – 22 – pFexternal heatsink

ISOLATION LIMITING VALUE & CHARACTERISTICSThs = 25 oC; unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITIces Collector cut-off current 2 VBE = 0 V; VCE = VCESMmax – – 1.0 mAIces VBE = 0 V; VCE = VCESMmax

2 – – 2.0 mATj = 125 oC

IEBO Emitter cut-off current VEB = 6.0 V; IC = OA – – 100 µABVEBO Emitter -base breakdown voltage IB =1 mA 7.5 13.5 – VVCEOsust Collector-emitter sustaining voltage IB = 0A; Ic = 100 mA; 800 – – V

L = 25 mHVCEsat Collector-emitter saturation voltages IC = 9.0 A; IB = 2.25 A – – 3.0 VVBEsat Base-emitter saturation voltages IC = 9.0 A; IB = 2.25 A 0.88 0.97 1.06 VhFE DC current gain IC = 1.0A; VCE = 5 V – 12 –

IC = 9.0 A; VCE = 5 V 4.2 5.8 7.6

STATIC CHARACTERISTICSThs = 25 oC; unless otherwise specified

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNITCc Collector capacitance IE = 0A; VCB = 10V; f = 1 MHz 145 – pF

Switching times (16 kHz line ICsat = 9.0 A;IB1= 1.8 Adeflection circuit) (IB2=-4.5 A)

ts Turn-off storage time 3.7 4.5 µs

tf Turn-off fall time 0.4 0.55 µsSwitching times (70 kHz line ICsat = 7.0 A;IB1= 1.4 Adeflection circuit) (IB2=-4.5 A)

ts Turn-off storage time 2 – µs

tf Turn-off fall time 0.15 – µs

DYNAMIC CHARACTERISTICSThs = 25 oC; unless otherwise specified


116


117


118

BD533/5/7 - BD534/6/8Complementary Silicon Power Transistors


• BD534, BD535, BD536, BD537 AND BD538ARE SGS-THOMSON PREFERRED SALESTYPES

DESCRIPTIONThe BD533, BD535, and BD537 are siliconepitaxial-base NPN power transistors in JedecTO-220 plastic package, intented for use inmedium power linear and switching applica-tions.The complementary PNP types are BD534,BD536, and BD538 respectively.


119

THERMAL DATA

ELECTRICAL CHARACTERISTICS (Tcase =25°C, unless otherwise specified)


120

BDX53B - BDX54B - BDX53C - BDX54CComplementary Silicon Power Darlington Transistors


INTERNAL SCHEMATIC DIAGRAM

• STMicroelectronics PREFERREDSALESTYPES

APPLICATIONS• AUDIO AMPLIFIERS• LINEARAND SWITCHING INDUSTRIAL

EQUIPMENT

DESCRIPTIONThe BDX53B and BDX53C are silicon Epitaxial-BaseNPN power transistors in monolithic Darlington config-uration mounted in Jedec TO-220 plastic package.They are intented for use in hammer drivers, audioamplifiers and other medium power linear and switch-ing applications.The complementary PNP types are BDX54B andBDX54C respectively.


121

THERMAL DATA

ELECTRICAL CHARACTERISTICS (Tcase =25°C, unless otherwise specified)


122

• New revolutionary high voltage technology• Ultra low gate charge• Periodic avalanche rated• Extreme dv/dt rated• Ultra low effective capacitances• Improved noise immunity

Parameter Symbol Value UnitContinuous drain current ID A

TC = 25 oC 7.3

TC = 100 oC 4.6

Pulsed drain current, tp limited by Tjmax ID puls 14.6

Avalanche energy, single pulse EAS 230 mJ

ID = 5.5A, VDD = 50V

Avalanche energy, repetitive tAR limited by Tjmax(1) EAR 0.5

ID = 7.3A, VDD = 50V

Avalanche current, repetitive tAR limited by Tjmax IAR 7.3 A

Reverse diode dv/dt dv/dt 6 V/ns

IS = 7.3 A, VDS<VDD, di/dt = 100 A/µs, Tjmax=150oC

Gate source voltage VGS ±20 V

Power dissipation Ptot 50 W

TC = 25 oC

Operating and storage temperature Tj, Tstg -55 ...+150 oC

Type Package Marking Ordering Code

SPP07N60C2 P-TO220-3-1 07N60C2 Q67040-S4309

SPB07N60C2 P-TO263-3-2 07N60C2 Q67040-S4310

VDS 600 V

RDS(on) 0.6 Ω

ID 7.3 A

MAXIMUM RATINGSat Tj = 25 oC; unless otherwise specified

D,2

S, 3 P-T0263-3-2

P-T0220-3-1

G, 1

Product Summary

SPP07N60C2 / SPB07N60C*Cool MOS Power Transistor


123

ParameterSymbol

ValueUnitat Tj = 25 oC; unless otherwise specified min. typ. max.

ELECTRICAL CHARACTERISTICS

Thermal resistance, junction - case RthJC – – 1.5 K/W

Thermal resistance, junction - ambient, Leaded RthJA – – 62

SMD version, device on PCB RthJA@ min. footprint – – 62@ 6 cm

2cooling area (2) – 35 –

Linear derating factor – – 0.66 W/KSoldering temperature Tsold – – 260 oC

Thermal Characteristics

Drain-source breakdown voltage V(BR)DSS 600 – – VVGS = 0V, ID = 0.25 mA

Drain-source avalanche breakdown voltage V(BR)DS – 700 –VGS = 0V, ID = 0.25 mA

Gate threshold voltage, VGS = VDS VGS(th) 3.5 4.5 5.5ID = 350 µA

Zero gate voltage drain current, VDS = VDSS IDSS µAVGS = 600V, VGS = 0V, Tj = 25 oC – 0.1 1VGS = 60V, VGS = 0V, Tj = 150 oC – – 100

Gate-source leakage current IGSS – – 100 nAVGS = 20V, VDS = 0V

Drain Source on-state resistance RDS(on) ΩVGS = 10V, ID = 4.6A, Tj = 25 oC – 0.54 0.6VGS = 10V, ID = 7.3A, Tj = 150 oC – 1.57 1.74

Gate input resistance RG – 0.8 –f= 1MHz, open drain

Static Characteristics

1 Repetitve avalanche causes additional power losses that can be calculated asPAV=EAR*f.

2 Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6 cm2 (one layer, 70µm thick) copper area for drainconnection. PCB is vertical without blown air.


124

• Adjustable output voltage: Vref to 36V

• Sink current capability: 1 to 100mA

• Typical output impedance: 0.22Ω

• 1% and 2% voltage precision

The TL431 is a programmable shunt voltage referencewith guaranteed temperature stability over the entire tem-perature range of operation.

The output voltage may be set to any value between Vref(approximately 2.5V) and 36V with two external resistors.

The TL431 operates with a wide current range from 1 to100mA with a typical dynamic impedance of 0.22Ω

FEATURES

PIN CONNECTIONS


DESCRIPTION

TO92

(Top view)Cathode Anode Reference

1 2 3

Symbol Parameters Value unit

VKA Cathode to Anode Voltage 37 V

IK Continuous Cathode Current Range -100 to +150 mA

Iref Reference Input Current Range -0.05 to +10 mAToper Operating Free-air Temperature Range TL431C/AC 0 to +70 oC

TL431I/A/ -40 to +85

Tstg Storage Temperature Range -65 to +150 oC

OPERATING CONDITIONS

Symbol Parameters Value unit

VKA Cathode to Anode Voltage Vref V

IK Cathode Current 1 to 100 mA

TL431Programmable Voltage Reference


125

BY229 SeriesRectifier diodes fast, soft recovery

PIN DESCRIPTION

1 cathode

2 anode

tab cathode

PINNINIG SOD59 (TO220AC)

QUICK REFERENCE DATASYMBOLFEATURES • Low forward volt drop • Fast switching• Soft recovery characteristic • High thermal cycling performance• Low thermal resistance

GENERAL DESCRIPTIONGlass-passivated double diffusedrectifier diodes featuring low forwardvoltage drop, fast reverse recoveryand soft recovery characteristic. Thedevices are intended for use in TVreceivers, monitors and switchedmode power supplies.The BY229 series is supplied in theconventional leaded SOD59(TO220AC) package.

VR = 200 V/ 400 V/ 600 V/800 VIF(AV) = 8 AIFSM ≤ 60 Atrr ≤ 135 ns

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

BY229 -200 -400 -600 -800VRSM Peak non-repetitive reverse - 200 400 600 800 V

voltage

VRRM Peak repetitive reverse voltage - 200 400 600 800 V

VRWM Crest working reverse voltage - 150 300 500 600 V

VR Continuous reverse voltage - 150 300 500 600 V

IF(AV) Average forward current1 square wave; - 8 Aδ = 0.5;Tmb ≤ 122 °Csinusoidal; - 7 Aa = 1.57;Tmb ≤ 125 °C

IF(RMS) RMS forward current - 11 A

IFRM Repetitive peak forward current t = 25 µs; δ = 0.5; - 16 ATmb ≤ 122 °C

IFSM Non-repetitive peak forward t = 10 ms - 60 Acurrent. t = 8.3 ms - 66 A

sinusoidal;Tj = 150 °C prior tosurge; withreapplied VRWM(max)

I2t I2t for fusing t = 10 ms - 18 A2s

Tstg Storage temperature -40 150 °C

Tj Operating junction temperature - 150 °C

LIMITING VALUESLimiting values in accordance with the Absolute Maximum System (IEC 134).


126

TSOP52Photo Module for High Data Rates PMC Remote Control Systems

DESCRIPTIONThe TSOP52.. – series are miniaturized SMD–IRReceiver Modules for infrared remote control systems.PIN diode and preamplifier are assembled on lead frame,the epoxy package is designed as IR filter.The demodulated output signal can directly be decodedby a microprocessor. TSOP52.. is the standard IR remotecontrol SMD–Receiver series, supporting all major trans-mission codes.

FEATURES• Photo detector and preamplifier in one package• Internal filter for PCM frequency• Continuous data transmission possible• TTL and CMOS compatibility• Output active low

• Low power consumption• High immunity against ambient light• Suitable burst length ≥10 cycles/burst• Taping available for topview and sideview

assembly

Available types for different carrier frequencies

Type fo Type fo

TSOP5230 30 kHz TSOP5233 33 kHz

TSOP5236 36 kHz TSOP5237 36.7 kHz

TSOP5238 38 kHz TSOP5240 40 kHz

TSOP5256 56 kHz

BLOCK DIAGRAM


127


BASIC CHARACTERISTICS

Application Circuit


128

BYW72-76Fast Silicon Mesa Rectifiers


APPLICATIONS

FEATURES

ELECTRICAL CHARACTERISTICS

MAXIMUM THERMAL RESISTANCE

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