documenti

I - 1© 2000 IXYS All rights reserved

Integrated Circuits

Integrated Circuits

The Smart Power ICs and Chip-sets manufactured by IXYSare designed to interface with the company's family of PowerMOSFET and IGBT products in order to provide improvedperformance for a broad range of power conversion and motorcontrol applications.

IXYS has focussed on two main areas:

High/Low Side Driver Integrated Circuits which complementIXYS Power MOSFET and IGBT that offer with either openor closed loop protection of the power devices, such as theIXBD 4410 Series.

PWM Regulator and Controller circuits optimized forspecialized power supplies and motor control applications.The device satisfying this need would the IXMS 150 andIXDP 610.

ContentsType Description Page

IXHQ100 Negative Voltage Hot Swap Controller with Active Power Filter 2

IXBD 4410-4411 ISOSMARTTM Half Bridge Driver Chipsets 8

IXDP 610 Bus Compatible Digital PWM Controller 19

IXDP 630 Inverter Interface and Digital Deadtime Generator 19IXDP 631 for 3-Phase PWM Controls

IXC.. Series Non switchable, DC Current Regulators, 2 - 100 mA / 450 V 20Non switchable, AC Current Regulators, 2 - 50 mA / 450 V

IXC. 10M35S Switchable Current Regulator, 10 mA/350 V 24IXC. 10M45S Switchable Current Regulator, 10 mA/450 V

IXC.01N90E Gate Controlled Current Limiter 26

IXMS 150 High Performance Dual 29PWM Microstepping Controller

Other devices included in the IXYS product range are a seriesof High Voltage Current Regulators, a Digital DeadtimeGenerator and a Negative Voltage Hot Swap Controller.

IXYS has an experienced staff of analog, digital and powerdesigners who are teamed together to ensure accuratedefinition of future generations of integrated solutions to satisfythe needs for the power control, power conversion and motioncontrol markets.

Using the advantages and compatibility of CMOS and IXYSHDMOSTM process, IXYS will continue to integrate functions forpower control which are still composed discretely.

I - 2 © 2000 IXYS All rights reserved

The IXHQ100 is a live insertion and removal circuit boardpower manager with a built-in power noise filter. It incorporatesall the active circuitry necessary to protect circuit boards duringlive insertion or removal, (insertion or removal when the systempower is on or active). Additionally, the IXHQ100 incorporatestwo new features. The first is a power active filter for improved -VIN noise suppression and eliminates costly, bulky, and heavypassive power filter components. The second is an Auto-Detect circuit, which senses the loss of either Gnd or -VIN, andeliminates the need for additional staggered Gnd or -VIN pinsand their associated detection components.

The IXHQ100 includes an on board shunt regulator to ensurewide input voltage range operation. The IXHQ100 allowscontinuous load current rise adjustments, presettable maximumcurrent limits, and user variable fault indication turn off times forresetting uPs and other synchronous board level systems. Foradded flexibility, GSNSin pin is available to implement eithercircuit board insertion/removal or -VIN undervoltage detection.

Negative Voltage Hot Swap Controller with Active Power Filter

Features

• Live Insertion and Removal Power Manager• Controlled Ramp-Up of Load Current.• Autodetect of Load Open Circuit or -VIN Disconnection• Operates from –9 V to – (External MOSFET Voltage Limit) V• Fault Indication Output (microprocessor reset).• Board Insertion/Removal Detector Input• Low frequency Power Active Filter• Adjustable Circuit Breaker Interrupt Current• VIN undervoltage with GSNSin input

Applications

• Central Office Switching Hardware• Circuit Boards From -48 V Distributed Power Supplies• Circuit Board Power Manager and Noise Filter• Circuit Board Hot Swap Protector and Manager• Electronic Circuit Breaker

Telecommunications Application with Auto Ground DetectFeatures:• Ground detection without staggered pins • VDD output (+5 V referred to -VIN)• Adjustable overcurrent protection with R4 • Active -VIN filter• Floating reset output • Electronic circuit breaker

IXHQ 100PIIXHQ 100SI

ADVANCED TECHNICAL INFORMATION




Absolute Maximum Ratings

Symbol Definition Max. Rating

VCC-VAGND Voltage applied VCCin to AGND -0.3 V to 16 VAll other pins except VD -0.3 V to VCCin + 0.3 V V

IVDD VDD Load Current 60 mATJM Maximum Junction Temperature 125 oCTJ Operating Temperature Range -40 oC to 85 oCTstg Storage Temperature Range -65 oC to 300 oC

Electrical CharacteristicsUnless otherwise noted, TA = 25 oC; -VIN= 48 V, AGND connected to -VIN, VSHUNToff = 5 V, VCC = 12 V, VGSNSin= 12 V. All voltagemeasurements with respect to AGND. IXHQ100 configured as described in Conditions.

Symbol Parameter Test Conditions Min Typ Max Units

ICC Supply current VCC=12 V, VSHUNToff = VCC, 1.5 3 mAall outputs unloaded.

ICCMAX Maximum shunted TPackage=TMAX 60 mAVCC supply current VCC = 16V

VCCSHUNT VCC shunt regulation ICC forced to 10 mA 12 14 16 Vvoltage VSHUNT = 0 V

VTHSHUNToff SHUNToff input VCC = 15 V, monitor RSTOUT 0.8 1.1 2 Vthreshold voltage

ISHUNToff SHUNToff input -1 1 µAbias current

VTHIVT IVT input VCC = 12 V, monitor RSTOUT 6 8 10 Vthreshold voltage

RiVT IVT input 70 130 180 KΩresistance

VTHGSNS GSNS sense input VCC = 12 V, monitor RSTOUT 4.5 6 7.5 Vthreshold voltage

IGSNSin GSNSin input -5 -2 -1 µAbias current

ICAPin CAPin input bias current -1 1 µA

VVDROP Active filter offset voltage 0.8 1.0 1.2 V

RVDROP VDROP input resistance 70 90 110 kΩ

ISLOPE SLOPE capacitor VOFFTM = 5 V, VGSOURCE = 0 V 120 150 180 µAcharging current VCAPin= 5 V

RSLOPEDCHG SLOPE capacitor VDROP = 5 V, IVT = VCC 130 200 Ωdischarge resistance VSOURCE = 0 V, VCAPin= 5 V

IOFFTM OFFTM capacitor VDROP = 5 V, VSOURCE = 0 V 120 150 180 µAcharging current VCAPin= 5 V

ROFFTMCHG OFFTM capacitor 130 200 Ωdischarge resistance

VTHOFFTM OFFTM input threshold OFFTM input voltage when SLOPE 3.8 4.2 4.5 Vvoltage input voltage starts its ramp

VCL Overcurrent threshold bias voltage 120 150 180 mV

RVCL VCL bias resistance 4 7 10 kΩ

tOC Overcurrent detection VCAPin = 0 V; VOUTsns = 5 V 13 20 µsto GATE output delay VSOURCE input is a step at t = 0s

from 0 V to 200 mV

dvGATE/dt GATE output slew rate CSLOPE= 100 nF 0.5 0.8 1.1 V/ms

VGATE Maximum GATE VCAPin = 0 V; Rload = 10 KΩ 10 11 Voutput voltage VOUTsns = 5 V

Pin Description




Functional Description

The IXHQ100 has three modes of operation:

1. Insertion/Removal modeWhen the circuit board is inserted, the voltage across the load,VLOAD, following the Power MOSFET controlled by the IXHQ100starts at zero potential. VLOAD rises at a slope determined by thevalue of the external capacitor placed between IXHQ100’sSLOPE pin and AGND. When the circuit board is removedwith VIN live, the IXHQ100 first provides a RSTout low andturns off the external Power MOSFET. The RSTout low can beused by the circuitry powered by VLOAD to gracefully shut downthe circuit board system. If power is restored or the circuitboard immediately reinserted, VLOAD will start from zero potentialand ramp up. With appropriate external components, GSNSinpin can work with staggered connectors to provide additionalboard insertion or removal detection.

2. Normal operation modeWith continuous -VIN applied, the IXHQ100 acts as an ActivePower Filter by modulating the voltage drop across the external

Power MOSFET, VDS, so that any noise on -VIN is cancelled byVDS. The direct connection of IXHQ100 AGND to -VIN allowsthe VDROP (internally set to ~750 mV) to set the ~90 % of themaximum peak noise voltage rejected by the IXHQ100. Theinternal VDROP setting of ~750 mV allows 1.35VPP of noiserejection.

3. Fault operation modeWhen the output load current is such that the voltage dropacross the current sense resistor between SOURCE andAGND exceeds VCL, (internally set to ~100 mV,) the GATEoutput is driven low to turn off the external Power MOSFETconnected between the load and --VIN. An external capacitorconnected between OFFTM and AGND determines the offtime, toff, of IXHQ100 after this fault. After toff, IXHQ100 willrestart the turn on sequence of the external Power MOSFETwith a load voltage slope determined by the size of the externalcapacitor connected to SLOPE. Whenever -VIN is interrupted orwhen the external circuit board disconnection is detected,RSTout will go low and the external Power MOSFET is shut offfor another toff period.

IXHQ100 Logic Diagram

Electrical Characteristics (continued)

Symbol Parameter Test Conditions Min Typ Max Units

IGATE GATE pull-up current Gate drive on, VGATE = 0 V -15 -10 mA

IGATE GATE pull-down Gate drive off 10 20 mAcurrent VGATE = 10 V

VDD VDD regulator output 3.3K Resistive load 5 5.5 6.5 VVoltage between VDD output and AGND

IRSTout RSTout drive current VRSTout =10 V during fault condition 15 30 50 mA

tRST RST pulse width 200 500 1000 ns

Vad Auto-Detect threshold Gate drive on; ramp VOUTsns; monitor 10 70 100 mVRST until it pulses.


IXHQ 100PIIXHQ 100SIADVANCED TECHNICAL INFORMATION

Frequency - Hz

1e+2 1e+3 1e+4 1e+5 1e+6

Rip

ple

Atte

nuat

ion

- db

0

5

10

15

20

25

30

35

40

45

50

55

60

Test Circuit for Ripple Attentuaion

Ripple Attenuation




Telecommunication Application- Active -VIN filter- Remote On/Off switch

Avionic Application- Arcless card insertion - Remote On/Off switch- Ground noise acitve filter - Electronic circuit breaker

Mobile Application- Arcless card insertion - Electronic circuit breaker- Remote On/Off switch

28V Application- Arcless card insertion - Remote On/Off switch- Ground noise acitve filter - Electronic circuit breaker

Telecommunication Application with -VIN Detection

- -VIN Detection without Staggered Pins- Floating Reset Output- VDD Output (Referred to -VIN)- Adjustable Overcurrent Protection- Active -VIN filter- Electronic Circuit Breaker


IXHQ 100PIIXHQ 100SIADVANCED TECHNICAL INFORMATION

Package Outlines: 16 PIN PDIPPackage Outlines: 16 PIN TSSOP

Part Package Type GradeNumber

IXHQ100PI 14 PIN PDIP IndustrialIXHQ100SI 14 PIN TSSOP Industrial

Ordering Information


ISOSMARTTM Half Bridge Driver Chipset

IXYS reserves the right to change limits, test conditions and dimensions.

Type Description Package Temperature Range

IXBD4410PI Full-Feature Low-Side Driver 16-Pin P-DIP -40 to +85°CIXBD4411PI Full-Feature High-Side Driver 16-Pin P-DIP -40 to +85°C

IXBD4410SI Full-Feature Low-Side Driver 16-Pin SO -40 to +85°CIXBD4411SI Full-Feature High-Side Driver 16-Pin SO -40 to +85°C

The IXBD4410/IXBD4411 ISOSMARTchipset is designed to control the gates oftwo Power MOSFETs or Power IGBTsthat are connected in a half-bridge(phase-leg) configuration for drivingmultiple-phase motors, or used inapplications that require half-bridge powercircuits. The IXBD4410/IXBD4411 is afull-feature chipset consisting of two 16-Pin DIP or SO devices interfaced andisolated by two small-signal ferrite pulsetransformers. The small-signal trans-formers provide greater than 1200Visolation.

Even with commutating noise ambientsgreater than ±50 V/ns and up to 1200 Vpotentials, this chipset establishes error-free two-way communications betweenthe system ground-reference IXBD4410

and the inverter output-referenceIXBD4411. They incorporate undervoltageVDD or VEE lockout and overcurrent ordesaturation shutdown to protect theIGBT or Power MOSFET devices fromdamage.

The chipset provides the necessary gatedrive signals to fully control the grounded-source low-side power device as well asthe floating-source high-side powerdevice. Additionally, the IXBD4410/4411chipset provides a negative-going, off-state gate drive signal for improved turn-off of IGBTs or Power MOSFETs and asystem logic-compatible status fault out-put FLT to indicate overcurrent or desa-turation, and undervoltage VDD or VEE.During a status fault, both chipset keeptheir respective gate drive outputs off; atVEE.

540 V-

Features

1200 V or greater low-to-high sideisolation.

Drives Power Systems Operating onup to 575 V AC mains

dv/dt immunity of greater than±50V/ns

Proprietary low-to-high side leveltranslation and communication

On-chip negative gate-drive supply toensure Power MOSFET or IGBTturn-off and to prevent gate noiseinterference

5 V logic compatible HCMOS inputswith hysteresis

Available in either the 16-Pin DIP orthe 16-Pin wide-body, small-outlineplastic package

20 ns switching time with 1000 pFload; 100 ns switching time with10,000 pF load

100 ns propagation delay time 2 A peak output drive capability Self shut-down of output in response

to over-current or short-circuit Under-voltage and over-voltage VDD

lockout protection Protection from cross conduction of

the half bridge Logic compatible fault indication from

both low and high-side driver

Applications

1- or 3-Phase Motor Controls Switch Mode Power Supplies

(SMPS) Uninterruptible Power Supplies

(UPS) Induction Heating and Welding

Systems Switching Amplifiers General Power Conversion Circuits

FULL FEATURED ISOSMARTTM DRIVER CHIP-SET


Symbol Definition Maximum Ratings

VDD/VEE Supply Voltage -0.5 ... 24 VVin Input Voltage (INH, INL) -0.5...VDD +0.5 V

Iin Input Current (INL, INH, IM) ±10 AIo (rev) Peak Reverse Output Current (OUT) 2 A

PD Maximum Power Dissipation 600 mW

TA Operating Ambient Temperature -40 ... 85 °CTJM Maximum Junction Temperature 150 °CTstg Storage Temperature Range -55 ... 150 °CTL Lead Soldering Temperature for 10 s 300 °C

Recommended Operating Conditions

VDD/VEE Supply Voltage 10 ... 20 VVDD/LG 10 ... 16.5 VLGh/LGl Maximum Common Mode dv/dt ±50 V/ns

Symbol Definition/Condition Characteristic Values(TA = 25°C, VDD = 15 V, unless otherwise specified)

min. typ. max.

INL, INH Inputs (referred to LG)

Vt+ Positive-Going Threshold 3.65 VVt- Negative-Going Threshold 1 VVih Input Hysteresis 1 VIin Input Leakage Current/Vin=VDD or LG -1 1 µACin Input Capacitance 10 pF

Open Drain Fault Output (referred to LG)

Voh HI Output/Rpu = 10 kΩ to VDD VDD-0.05 VVol LO Output/Io = 4 mA 0.3 0.5 V

OUT Output (referred to LG)

Voh HI Output/Io = -5 mA VDD-0.05 VVol LO Output/Io = 5 mA VEE+0.05 VRo Output HI Res./Io = -0.1 A 3 5 ΩRo Output LO Res./Io = 0.1 A 3 4 ΩIpk Peak Output Current/CL = 10 nF 1.5 2 A

IM Input (referred to KG)

Vt+ Positive-Going Threshold 0.24 0.3 0.45 VCin Input Capacitance 10 pFRs Shorting Device Output Resistance 50 75 100 Ω

VEE Supply (referred to LG)

VEE Output Voltage/Io = 1 mA, Co = 1 µF -5 -6.5 -7.5 VIout Output Current/Vout = 0.70 • VEE -20 -25 mAfinv Inverting Frequency 600 kHzVEEF Undervoltage Fault Indication -3 -4.8 V

Dimensions in inch (1" = 25.4 mm) 16-Pin SO

Cross view

16-Pin Plastic DIP

IXBD4410IXBD4411


Fig. 1a: IXBD4410/4411 Switching time test circuit Fig. 1b: Output signal waveform

IXBD4410IXBD4411

Symbol Definition/Condition Characteristic Values(TA = 25°C, VDD = 15 V, unless otherwise specified)

min. typ. max.

VDD Undervoltage Lockout

Vuv Drop Out 9.5 10.5 11.5 VVuh Hysteresis 0.1 0.15 0.3 V

Quiescent Power Supply Current

IDD VDD Current/Vin=VDD or LG, Io = 0 20 mA

INL and INH Inputs (Fig. 1a - 1c)

td(on) Turn-on delay time; CL =1nF 110 175 ns4410

tr Rise time; CL =10 nF 70 100 nsCL =1 nF 15 20 ns

td(off) Turn-off delay time CL =1nF 70 150 ns4410

tf Fall time CL =10nF 70 150 nsCL =1nF 15 20 ns

tdlh(off) 4410/4412Turn-on delay time vs.

4411 CL =1nF 60 150 nsTurn-off delay time

tdlh(on) 4410Turn-on delay time vs.

4411 CL =1nF 60 150 nsTurn-off delay time

Fault Output Delay for any Fault Conditions (4410/4411)

tFLT FLT Delay/Rpu = 2 kΩ CL = 20 pF 200 300 ns

Overcurrent Protection Delay

toc Driver-Off delay time CL = 1 nF 200 300 ns


IXBD4410IXBD4411

Chipset OverviewThis ISOSMARTTM chipset is a pair ofintegrated circuits providing isolated high-and low-side drivers for phase-leg motorcontrols, or any other application whichutilizes a half bridge, 2- or 3-phase driveconfiguration. They consist of two drivecontrol inputs (INL and INH) for twoPower-MOSFET/IGBT gate-drive outputs.Both inputs operate from a commonground and are activated by HCMOScompatible logic levels. The low-sideoutput operates near input ground, whilethe high-side output operates from afloating ground that is nominally thesource connection of the high-sidephase-leg power device. Both outputstypically provide 2 A of transient currentdrive for fast switching of the phase-legpower device.

IXBD4410/IXBD4411The full featured ISOSMARTTM driverchipset incorporates a IXBD4410 as thelow-side driver (Fig. 3) and a IXBD4411as the high-side driver (Fig. 2). Wheninput "INL" is set to a positive logic level,the low-side gate output goes high (turnson); when "INH" is set to a positive logiclevel, the high-side gate drive output goeshigh. The high-side IC is isolated from thelow-side IC by a magnetic barrier, acrosswhich the turn on/off signal is transmittedto the high-side gate drive. The IXBD4411fault signal is also transmitted back to theIXBD4410 driver via these transformers.This isolation only depends on the lowcost communica-tions transformer, whichis designed to withstand 1200 V or more.

There are two magnetic transmissionchannels between the low- and high-sideIC's for bi-directional communication. Onesends a signal from the low-sideIXBD4410 IC up to the high-sideIXBD4411 IC and the other sends asignal back from the high-side to the low-side IC. The signal that is sent up controlsthe IXBD4411 gate-drive output. Thesignal sent from the IXBD4411 back tothe IXBD4410 indicates a high-side faulthas occurred (overcurrent, or under-voltage of the high-side +power supplies).This is detected at the IXBD4410 driverand sets "FLT" pin low, to indicate thehigh-side fault.

The fault signal that is returned from theIXBD4411 is strictly for status only. Anygate-drive shutdown because of a high-side fault is done locally within the high-

VEE

VDD

UVDD

Fig. 2: IXBD4411, high-side driver block diagram

Fig. 3: IXBD4410, low-side driver block diagram

Fig. 4: Logic representation of IXBD4410 FLT signal

UVEE

VDD

VEE

UVDD

UVEE


IXBD4410IXBD4411

side IXBD4411. The IXBD4411 gate-drive will turn-off the power devicewhenever an overcurrent or undervoltage condition arises. The overcurrentsensing is active only while the gatedriver output is "high" (on). Theovercurrent fault condition is latched andis reset on the next INH gate inputpositive transition. The FLT (pin 8) of theIXBD4411 is not used and should begrounded.

The low-side IXBD4410 driver providesan output pin 8 (FLT) to indicate a high-side (IXBD4411) or a low-side(IXBD4410) fault. This output pin is an"open-drain" output. The IXBD4410 low-side driver fault indications are similar tothe IXBD4411 high-side driverindications as outlined above. A"graphic" logic diagram of the chipset'sFLT function is presented in Fig. 4. Notethat this diagram presents the logic ofthis function at the "low-side" IXBD4410driver and is not the actual circuit. Itdescribes the combined logic of the"fault logic" and "hi-side fault sense"blocks in both the IXBD4410 andIXBD4411 as shown in Fig. 2 and 3.

The most efficient method of providingpower for the high-side driver is bybootstrapping. This method is illustratedin the functional drawing on page 4 andin the application example (Fig. 6 and 9)by diode D1 and capacitor C1. Usingthis method, the power is drawn througha high-voltage diode onto a reservoircapacitor whenever the floating high-side ground returns to near the realground of the low-side driver. When thehigh-side gate is turned on and thefloating ground moves towards a higherpotential, the bootstrapping diode back-biases, and the high-side driver drawsits power solely from the reservoircapacitor. Power may also be providedvia any isolated power supply (usuallyan extra secondary on the systemhousekeeping supply switchingtransformer).

Both the IXBD4410 and IXBD4411contain on-board negative chargepumps to provide negative gate drive,which ensures turn-off of the high- orlow-side power device in the presenceof currents induced by power deviceMiller capacitance or from inductiveground transients. These charge pumpsprovide -5 V relative to the local driverground when VDD is at +15 V, and atrated average currents of 25 mA. Thecharge pump requires two externalcapacitors, C7 and C11 in Fig. 6. Thecharge pump frequency is nominally600 kHz. The charge pump clock isturned off whenever the differencebetween the VDD and VEE suppliesexceed 20 V, to prevent exceeding thebreakdown rating of the IC.

Both the IXBD4410 and IXBD4411drivers possess two local grounds each,a common logic ground, and "Kelvin"ground. The Kelvin ground and logicgrounds are first connected directly toeach other, and then to the Kelvin-source of the power device for accurateover-current measurement in thepresence of inductive transients on thepower device source terminal.

Power MOSFET or IGBT overcurrentsensing utilizes an on-chip comparatorwith a typical 300 mV threshold. In atypical application, the current mirror pinof the Power MOSFET or IGBT is con-nected to a grounded, low-value resistor,and to the overcurrent comparator inputon the high- or low-side driver. Thecomparator will respond typically within150 ns to an overcurrent condition toshutdown the driver output. The powerswitches could be protected also bydesaturation detection (see Fig. 6, 7and 9).

To assure maximum protection for thephase-leg power devices, the chipsetincorporates the following PowerMOSFET and IGBT protection circuits:

Power device overcurrent or desa-turation protection. The IXBD4410/4411will turn off the driven devicewithin 150 ns of sensing an outputovercurrent or desaturation condition.

Gate-drive lockout circuitry to preventcross conduction (simultaneousconduction of the low- and high-sidephase-leg power devices), eitherunder normal operating conditions orwhen a fault occurs.

During power-up, the chipset's gate-drive outputs will be low (off), untilthe voltage reaches the under-voltagetrip point.

Under-voltage gate-drive lockout onthe low- and/or high- side driverwhen-ever the respective positivepower supply falls below 9.5 Vtypically.

Under-voltage gate-drive lockout onthe low- and high- side driverwhenever the respective negativepower supply rises above -3 Vtypically.


IXBD4410IXBD4411

Pin DescriptionIXBD4411 (High-Side Driver)

Sym. Pin Description of IXBD 4410/4411

FLT 8 Low/high side fault output. In the IXBD4410,NC this output indicates a fault condition of either device

of the chipset. A "high" indicates no fault, A "low"indicates that either overcurrent,VDD or VEE under-voltage occurred. In case of overcurrent, this outputwill remain active "low" until the next input cycle ofthe respective driver. In case of under-voltage, thisoutput will remain "low" until the proper voltage isrestored. The IXBD4411 does not have a FLToutput,and its pin 8 should be tied to LG

No Connection (IXBD 4411)

IM 9 Current sense or desaturation detection input. Thisinput is active only while the OUT pin is "high" (on).When the OUT pin is "low" (off) this input is pulled toground through a 70 Ω resistor. Any voltage at thispin above the threshold of .3 V typical, will turn theoutput (pin 15) off. This pin is used for power deviceovercurrent protection.

KG 10 Kelvin ground. This ground is used as Kelvinconnection for overcurrent or desaturation sensing.

LG 11 Logic and power ground.

CB 12 Capacitor terminals for negative charge pump (VEE);CA 13 "+" terminal is CB (pin 12).

VEE 14 Negative supply terminal.

OUT 15 Gate drive output. In the IXBD4410 this outputresponds to the INL signal. A "high" at INL will turn iton ("high"), a "low" will turn it off ("low"). In theIXBD4411, this output responds to the transmittedsignal from the companion IXBD4410. A "high" atINH of the IXBD4410 drives will turn it on ("high"). A"low" will turn it off ("low"). This output will turn off("low") also in response to any fault condition.

VDD VDD

NC OUT

NC VEE

T- CA

T+ CB

R- LG

R+ KG

NC IM

Pin DescriptionIXBD4410 (Low-Side Driver)

Sym. Pin Description of IXBD 4410/4411

VDD 1 Positive power supply.16

INL 2 Logic input signal referenced to LG (logic ground).NC In the IXBD4410. A "high" to this pin turns on its gate

drive output and resets its fault logic. A "low" to thispin turns off the gate drive output. In the IXBD4411this pin is not used and should be connected to itsground (LG).


INH 3 Logic input signal referenced to LG (logic ground).NC In the IXBD4410, this signal is transmitted to the

IXBD4411 "high-side" driver through pins 4 and 5 (T-and T+). A "high" to this pin turns on the IXBD4411gate drive output and resets its fault logic. A "low" tothis pin turns off the IXBD4411 gate drive output. Inthe IXBD4411 this pin is not used and should beconnected to its ground (LG).


T- 4 Transmitter output complementary drive signals.T+ 5 Direct drive of the low signal transformer, which is

connected to the receiver of the chipset's companiondevice. In the IXBD4410, this signal transmits the on/off command to its companion IXBD4411. In theIXBD4411, this signal transmits the fault indication toits companion IXBD4410 driver.

R- 6 Receiver input complementary signal. DirectlyR+ 7 connected to the low signal transformer, which is

driven by the chipset's companion device. In theIXBD4410, this input receives the fault indicationfrom its companion IXBD4411 driver. In theIXBD4411, this input receives the on/off commandfrom its companion IXBD4410 driver.


IXBD4410IXBD4411

Application

The IXBD4410/4411 chipset devices arespecifically designed as MOS-gatedtransistor drivers in half-bridge powerconverters, 1- and 3-phase motorcontrols, and UPS applications. Thephase-leg PWM command is normallygenerated by previous (user provided)circuitry. It must be decomposed into twoseparate logic signals, one for the high-side and one for the low-side powertransistors, with appropriate deadtime foreach state transition. The deadtimeinsures non-overlapping conductioneven if the turn-on and turn-off delaytimes of the power devices are unequal.The minimum deadtime should begreater than tdlh. A separate circuit, or anIC device like the IXYS deadtimegenerator IXDP630, can be used toperform this function. The ISOSMART™chipset family of devices do notgenerate deadtime, although there is aninternal lockout that prohibits one deviceform being commanded "on" before theother is commanded "off". This simplifiesstart-up and shutdown protectioncircuitry, preventing logic error duringpower-up from turning on both high-andlow-side transistors simultaneously.

Negative VEE Charge Pump CircuitDesign

The on-chip VEE generator provided inthe IXBD4410/4411 generates a nega-tive power supply, regulated at 20 Vbelow the positive VDD rail. If VDD is +10 V,VEE will be -10 V. If VDD is +15 V, VEE willbe -5 V. This negative drive potential inthe off-state is either desirable orrequired in many instances. Whenswitching a clamped inductive load (Fig.5), the turn-on of Q2 will commutate thefreewheeling diode around Q1. Whetherthis diode is intrinsic (as in a MOSFET)or extrinsic (IGBT or bipolar), its reverserecovery is critical to proper circuitoperation.

At high turn-on di/dt in Q2 and near itsrated voltage, the recovery of D1 canget quite "snappy" (the di/dt in thesecond half of the recovery process,after the diode has begun to recover itsblocking capability, can get very large),creating a very high dv/dt across Q1.This dv/dt is impressed across the Millercapacitance of Q1, forcing a largecurrent to flow out the gate terminal ofthe device. If this current pulse causes a

reduces the voltage required to create afailure, this problem is even more likelyto occur. In an industrial modulepackage (e.g.: a 150 A/1200 V IGBTphase-leg module), the series induc-tance contributed by the long gate leadsand connectors further complicate thedesign.

In a heavily snubbered converter, or in apower supply design with low trans-former leakage inductance, the designproblem is relatively simple and negativedrive is seldom required. However, in amodern snubberless or lightly snubberedconverter design, it is important to keepthe gate drive impedance high enoughduring transistor turnoff to limit thereapplied dv/dt (the transistor is its own'active' snubber). This is alwaysimportant for EMI control, and in thecase of IGBT may be required toachieve the necessary RBSOA. At thesame time, it is mandatory to keep theoff-state gate drive impedance very lowto assure the transistor remain off duringinduced dv/dt (including diode recoverydv/dt). In some instances, it is simply notpossible to satisfy both criteria with 0 Vapplied in the off-state. In these casesthe IXBD4410/4411 with VEE negativebias generator must be used.

The internal VEE generator is a chargepump circuit. Referring to Fig. 6, anexternal charge pump capacitor isrequired between the CA and CB

high enough voltage drop across theoutput impedance of the gate drivecircuit, Rout, Q1 will be turned on.

The Q1 conduction in every instance Q2is turned on (and vice versa), asidefrom degrading efficiency, can lead tocatastrophic failure of both powertransistors. At high temperature, wherethe -6 to -7 mV/°C temperature coeffi-cient of IGBT/MOSFET threshold

Fig. 5: Switching a clamped inductiveload

Fig. 6: IXBD4410/4411 Detailed one phase circuit with dead time generator IXDP 630


terminals (C7, C11), and an outputreservoir capacitor between VEE andGND (C10, C14). A 0.1 µF charge pumpcapacitor (C7, C11) is recommended.The voltage regulation method used inthe IXBD4410/4411 allows a 1 to 2 Vripple frequency depends on the size ofthe VEE output reservoir capacitor (C10,C14) and the average load current. Theminimum recommended output reservoir(C10, C14) is 4.7 µF tantalum, or 10 µF ifaluminium electrolytic construction ischosen. Note that this reservoir capaci-tor is in addition to a good quality highfrequency bypass capacitor (0.1 µF) thatshould be placed from VEE to GND (C9,C13).

A small resistor in series with the chargepump capacitor, (R7, R8) reduces thepeak charging currents of the chargepump. A value or 68 Ω or greater isrecommended, as illustrated in theapplications example in Fig. 6.

Current Sense / Desaturation Detec-tion Circuit

All members of the ISOSMART™ driverfamily provide a very flexible overcurrent/short circuit protection capability thatworks with both standard three-terminalpower transistors, and with 4- and 5-terminal current sensing power devices.Overcurrent detection is accomplishedas illustrated in Fig. 7a (for a currentmirror power device) and Fig. 7b (for astandard three terminal power transis-tor). Desaturation detection is accom-plished with the same internal circuits bymeasuring the voltage across the powertransistor in the on-state with an externalresistor divider (Fig. 7c).

The IM input trip point VTIM, typically300 mV, is referenced to the Kelvinground pin KG.

Current Mirror MOSFET and IGBT allowgood control of peak let-through currentsand excellent short circuit protectionwhen combined with the ISOSMART™driver family of devices. The senseresistor is chosen to develop 300 mV atthe desired peak transistor current,assuming a mirror ration of 1400:1, anda trip point of 30 A is desired:

Rs = 300 mV • 1400/30 A = 14 Ω(use 15 Ω CC).

It is important to realize that Coss per unitarea of the mirror cells is much largerthat Coss per unit area of the bulk of the

Fig. 7: Alternative overcurrent protection circuits

a b c

Desaturation Detectionwith StandardMOSFET/IGBT

With StandardMOSFET/IGBT

With Current Mirror

IM

KGGND

IM

KGGND

IM

KGGND

chip due to periphery effects. Thiscauses a large transient current pulse atthe mirror output whenever the transistorswitches (C • dv/dt currents), which cancause false overcurrent trigger. The RCfilter indicated in Fig. 7a will eliminate thisproblem.

Standard three-terminal MOSFET andIGBT devices (in discrete as well asmodern industrial single transistor andphase-leg modules) can also beprotected from short circuit with theISOSMART™ driver family devices. Indiscrete device designs, where thesource/emitter terminal is available,overcurrent protection with an externalpower resistor can be implemented. Theresistor is placed in series with thedevice emitter, with the full device currentflowing through it (Fig. 7b). The senseresistor is again selected to develop300 mV at the desired peak transistorcurrent, assuming a trip point of 30 A isdesired:

Rs = 300 mV / 30 A = 10 mΩ(use 10 mΩ, noninductivecurrent sense resistor).

It is important to recognize that"noninductive" is a relative term,especially when applied to current senseresistor construction and characteriza-tion. There is always significant seriesinductance inserted with the senseresistor, and L • di/dt voltage transientscan cause false overcurrent trigger.

The RC filter indicated in Figure 7b willeliminate this problem. Choosing the RCpole at the current sense resistor RLzero should exactly compensate forseries inductance. Because the exactvalue is not normally known (and canvary depending on PC layout andcomponent lead dress) this is notnormally a good idea. Usually, the RC

time constant should be two to ten timeslonger than the suspected RL timeconstant.

Desaturation detection as in Figure 7c isprobably the most common method ofshort circuit protection in use today.While not strictly an "overcurrent"detector, if the power transistor gain, andconsequently short circuit let-throughcurrent, is well controlled (as withmodern MOSFET and IGBT) thismethodology offers very effectiveprotection.

The IXBD4410/4411 half-bridge circuitsin Fig. 6 uses desaturation detection. InFig. 6, the voltage across the two powerMOSFET devices (or IGBTs) aremonitored by two sets of voltage-dividernetworks, R10 and R11 for the high-sidegate driver, and R13 and R14 for thelow-side gate driver. The dividers are setto trip the IM input comparators wheneither Power MOSFET device VDS

exceeds a reasonable value, perhaps50 V (usually a value of 10 % of thenominal DC bus voltage works well).R10 or R13 are chosen to tolerate theapplied steady state DC bus voltage atan acceptable power dissipation.Dielectric withstand capability, powerhandling, temperature rise, and PCboard creep and strike spacings, mustall be carefully considered in the designof the voltage-divider networks.

In the off-state, the voltage across thePower MOSFET device may go as highas the DC bus potential. To keep thisnormal condition from setting the internalfault flip-flop of the IXBD4410 or theIXBD4411, an internal CMOS switch isturned on and placed across lM and KGpins shorting them together. Thiseffectively discharges C8 or C12 in Fig.6 and maintains zero potential withrespect to KG at IM.

Rs Rs Rs

IXBD4410IXBD4411


When the command arrives to switch onthe Power MOSFET device, the CMOSswitch shorting IM to KG is turned off.The driven Power MOSFET device isswitched on approximately 100 ns to1 µs later, and with typical loadconditions, its drain-to-source potential,VDS, may take an additional 10 µs ofdelay to collapse to the normal on-statevoltage level. To prevent false triggeringdue to this, C8 or C12 in parallelcombination with R10 and R11, or R13and R14, delays the IM input signal.During this turn-on interval, the voltageacross C8 or C12 will rise until thePower MOSFET device finally comes onand pulls the voltage across C8 or C12back down. If the MOSFET device loadcircuit is shorted, its VDS voltage cannotcollapse at turn-on. In this case, thevoltage across C8 or C12 rises rapidlyuntil it reaches 300 mV, tripping the faultflip-flop and shutting down the driveroutput. At the same time, C8 or C12must be kept small enough that theadded delay does not slow down thedetection of a short circuit event somuch that the Power MOSFET devicefails before the driver realizes that it is introuble. The desaturation detectioncircuit in Fig. 9 functions identically to theone in Fig. 6 as just described. Currentlimit or desaturation detection is latched,and reset on a cycle-by-cycle basis withthe rising edge of the respective inputcommand.

Fig. 8: Typical 3-phase motor control system block diagram

Three Phase Motor Controls

Fig. 8 is a block diagram of a typical 3-phase PWM voltage-source invertermotor control. The power circuit consistsof six power switching transistors withfreewheeling diodes around each of them.The control function may be performeddigitally by a microprocessor, micro-controller, DSP chip, or user custom IC;or it may be performed by a PC board fullof random logic and analog circuits. Inany of these cases, the PWM commandfor all six power transistors is generatedin one circuit, and this circuit is usuallyreferred to system ground potential - thebottom terminal of the power bridge.

The ISOSMART™ family of drivers is theinterface between the world of controllogic and the world of power, 5 V inputlogic commands precisely control actionsat high voltage and current (1200 V and100 A in a typical application). Fig. 6 is adetailed schematic of one phase of three

3-phase motor control, showing theinterconnection of the IXBD4410/4411and its associated circuitry.

PCB Layout Considerations

The IXBD4410/4411 is intended to beused in high voltage, high speed, high dv/dt applications.

To ensure proper operation, great caremust be taken in laying out the printedcircuit board. The layout critical areasinclude the communication links, currentsense, gate drive, and supply bypassing.

The communication path should be asshort as possible. Added inductancedisturbs the frequency response of the

Fig. 9: Lower cost IXBD4412/4413 single phase circuit with deadtime generatorIXDP630

signal path, and these distortions maycause false triggering in the receiver. Thetransformer should be placed betweenthe two ICs with the orientation of one ICreversed (Fig. 10).

Capacitance between the high- and low-side should be minimized. No signal traceshould run underneath the communica-tion path, and high- and low-side tracesshould be separated on the PCB. The dv/dt of the high-side during power stageswitching may cause false logic transi-tions in low-side circuits due to capacitivecoupling.

The low signal pulse transformerprovides the isolation between high-and

IXBD4410IXBD4411


IXBD4410IXBD4411

low-side circuits. For 460 V~ line opera-tion, a spacing of 4 mm is recommendedbetween low- and high-side circuits, anda transformer HIPOT specification of atleast 1500 V~ is required. This creepspacing is usually adequate to controlleakage currents on the PCB with up to1200 V~ applied after 10 to 15 years ofaccumulated dust and particulates in astandard industrial environment. In otherenvironments, or at other line voltages,this spacing should be appropriatelymodified.

The current sense/desaturation detectinput is noise sensitive. The 300 mV trippoint is referred to the KG (Kelvin ground)pin, and the applied signal must be keptas clean as possible, A filter is recom-mended, preferably a monolithic ceramiccapacitor placed as close to the IC aspossible directly between IM and KG. Topreserve maximum noise immunity, theKG pin should first be connected directlyto the LG pin, and the pair then sentdirectly to the power transistor source/emitter terminal, or (if a desaturationdetection circuit is used) to the bottom ofthe divider resistor chain.

All supply pins must be bypassed with alow impedance capacitor (preferablymonolithic ceramic construction) withminimum lead length. The output driverstage draws 2 A (typical) currents duringtransitions at di/dt values in excess of100 A/µs. Supply line inductance willcause supply and ground bounce on thechip that can cause problems (logicoscillations and, in severe cases,possible latch-up failure) without properbypassing. These bypass elements are inaddition to the reservoir capacitorsrequired for the negative Vee supply andthe high-side bootstrapped supply if thesefeatures are used.

Power Circuit Noise Considerations

In a typical transistor inverter, the outputMOSFET may switch on or off with di/dt>500 A/µs. Referring to Fig.11 and

assuming that the MOSFET sourceterminal has a one inch path on the PCBto system ground, a voltage as high as V= 27 nH • 500 A/µs = 13.5 V can bedeveloped. If the MOSFET switched 25A, the transient will last as long as (25/500) µs or 50 ns, which is more than thetypical 6 or 7 ns propagations or of a74HC series gate.

Grounding the gate driver as in option(a) in Fig. 11 solves the MOSFET turnon problem by eliminating LS1 from thesource feedback loop. Now, unfor-tunately, the gate driver will oscillateevery time it is turned on or off. As theIXDP630 output goes "high", the gatedrive output follows (after its propaga-tion delay) and the MOSFET starts to

Fig. 11: Potential layout problems that create functional problems

Fig. 11 illustrates an example layoutproblem. The power circuit consists ofthree power transistors (MOSFETs inthis example). With the ISOSMART™gate driver chipset grounded as in option(b) in Fig. 11, the communication pathfrom the IXDP630 will operate withouterrors. The PC trace induced voltagesare not common with the digital path, sothe input of the gate driver will not see orrespond to them.

Unfortunately, the MOSFET will notoperate properly. The voltage inducedacross LS1 when Q1 is turned on, actsas source degeneration, modifying theturn-on behavior of the MOSFET. If LS1=27 nH, and VCC is 15 V (assuming thegate plateau of the MOSFET is 6 V), thedi/dt at turn-on will be regulated by thedriver/MOSFET/LS1 loop to about 200 A/µs; quite a surprise when your circuitrequires 500 A/µs to operate correctly.

It is possible to make use of this behaviorto create a turn-on or turn-off di/dt limiter(perhaps to snub the upper free wheelingdiode reverse recovery). While possible,this is normally not desirable or practicalwhere two or more transistors arecontrolled. Equalizing the parasiticimpedances of three traces whilepositioning the transistors next to theirheat sink and meeting UL/VDE voltagespacings is just too difficult.

conduct. The voltage transient inducedacross LS1 (V = LS1 • di/dt) raises thelocal ground (point a) until it exceeds Voh

(630) - Vil and the driver (after itspropagation delay) turns the MOSFEToff. Now the MOSFET current falls,V(LS1) drops, point (a) drops to systemground (or slightly below), and the driverdetects a "1" at its input. After itspropagation delay, it again turns theMOSFET on, continuing the oscillation forone more cycle.

To eliminate this problem, a ground leveltransformation circuit must be added, thatrejects this common mode transient. Thesimplest is a de-coupling circuit, alsoillustrated in Fig. 11. The capacitorvoltage on Cd remains constant while thetransient voltage is dropped across Rd

and the driver detects no input transition,eliminating the oscillation. This circuitdoes add significantly to turn-on and turn-off delay time, and cannot be used if thetransient lasts longer than the allowabledelays. Delay times must be consideredin selection of system dead time.

The most complex (and most effective)method of eliminating the effects oftransients between grounds is isolation.Optocouplers and pulse transformers arethe most commonly used isolationtechniques, and work very well in this

Low Side High Side

Fig. 10: Suggested IC Orientation


IXBD4410IXBD4411

case. The IXDP630/631 has beenspecifically designed to directly drive ahigh speed optocoupler like the HewlettPackard HCPL22XX family or theGeneral Instrument 740L60XX optologicfamily. These optos are especially wellsuited to motor control and powerconversion equipment due to their veryhigh common mode dv/dt rejectioncapabilities.

Transformer Considerations

The transformer is the communicationlink and isolation barrier between thehigh- and low-side ICs. The high-sidegate and fault signals are transmittedthrough the transformer while main-taining the proper isolation. The trans-mitter signal is in the form of a squarewave, but the receiver responds only tothe logic edges. This allows for muchsmaller transformer designs, since a10 kHz switching frequency does notrequire a 10 kHz pulse transformer.

The recommended transformer for thisISOSMART™ driver chipset is fabricatedusing a very small ferrite shield bead (seeFig. 12), onto which a six-turn primaryand a two-turn secondary winding of36 AWG magnet wire are made. The twowindings are segment wound to achieveprimary-to-secondary isolation of up to2500 V~. The six-turn primaries areconnected to the respective IXBD4410/4411 transmitter outputs and the two-turnsecondaries are connected to theirrespective receiver inputs.

The nominal electrical specifications ofthe transformer are as follows:

Open circuit inductance(100 kHz; 20 mV): 3 µH

Interwinding capacitance: 2 pF Primary leakage inductance: 0.1 µH Turns ratio: 6:2 Primary-to-secondary

isolation (1 min): 1500 V~ Core permeability (µi): 125

Fig. 12: Ferrite bead dimensions

The recommended ferrite bead is FairRite Products part number 2661000101,which is manufactured by:

Fair-Rite Products Corp.Wallkill, NYPhone: (800) 836-0427Web site: www.fair-rite.com

As seen in the application drawings (Fig.6, 9 and 13) a coupling capacitor (22 nF)and a damping resistor (22 Ω) are addedin series with the primary side of thetransformer. The capacitor will control

the small amount of energy needed totransfer the signal to the companiondriver. The resistor will control thedamping of the signal and limit the peaktransmitter output current. The receiveris designed to operate over a widecommon mode input range. To reducenoise pickup, the receiver has ±250 mVof input hysteresis.

If the signal is being distorted at thetransmitter, the transmitter is probablyrunning into current limit. A decrease inthe coupling capacitance or an increasein the damping resistance should solvethis problem. The receiver operates overa wide input range. The minimumamplitude for one side of the receiver isabout 1 V and a maximum of about 3 V. Itis critical that there be no overshoot onthe transformer secondary wave-form.Each signal should be slightly over-damped. If significant overshoot exists,the received signal may be logicallyinverted. An increase of the dampingresistor will solve this problem.

Fig. 13: Transmitter/Receiver Waveforms


IXYSIXDP610DPWM

Basis system Configuration

Type Package TemperatureRange

°°°°°C

IXDP 610 PI 18-Pin Plastic DIP -40 to 85

Microprocessoror

Microcontroller

SwitchingPowerBridge

Features

Microcomputer bus compatible

Two complementary outputs for directcontrol of switching power bridge

Dynamically programmable pulsewidth ranges from 0 to 100 %

Two modules of operation: 7-bit or 8-bitresolution

Switching frequency range up to300 kHz

Programmable Dead-time Counterprevents switching overlap

Cycle-by-cycle disable input to protectagainst over-current,over-temperture,etc.

Outputs may be disabled undersoftware control

Special locking bit prevents damage tothe power stage in the event of asoftware failure

Bus compatible Digital PWM Controller, IXDP 610

desaturation protection schemas. TheIXDP 610 is capable of operating atPWM frequencies from zero to 300 kHz,the dead-time is programmable fromzero to 14 clock cycles (0 to 11 % of thePWM cycle), which allows operationwith fast power MOSFETs, MOSIGBTs,and bipolar power transistors. A trade-offbetween PWM frequency and reso-lutionis provided by selecting the counterresolution to be 7-bit or 8-bit. The 20 mAoutput drive makes the IXDP 610capable of directly driving opto isolatorsand Smart-power devices. The fastresponse to pulse width commands isachieved by instantaneous change ofthe outputs to correspond to the newcommand. This eliminates the one-cycledelay usually associated with digitalPWM implementations.

The IXDP 610 Digital Pulse WidthModulator (DPWM) is a programmableCMOS LSI device which accepts digitalpulse width data from a microprocessorand generates two complementary non-overlapping pulse width modulatedsignals for direct digital control of aswitching power bridge. The DPWM isdesigned to be operated under the direct

control of a microprocessor andinterfaces easily with most standardmicroprocessor and microcomputerbuses. The PWM waveform generatedby the IXDP 610 results from comparingthe output of the Pulse Width Counter tothe number stored in the Pulse WidthLatch. A programmable "dead-time" isincorporated into the PWM waveform.The Dead-time Logic disables bothoutputs on each transition of theComparator output for the required dead-time interval. The output stage providescomplementary PWM output signalscapable of sinking and sourcing 20 mAat TTL voltage levels. The OutputDisable Logic can be activated either bysoftware or hardware. The facilitatescycle-by-cycle current-limit, short-circuit, overtemperature, and

Type Configuration Package Temperature Range°°°°°C

IXDP 630 PI RC Oscillator 18-Pin Plastic DIP -40 to 85

IXDP 631 PI Crystal Oscillator 18-Pin Plastic DIP -40 to 85

Digital Deadtime Generator, IXDP 630 / 631Features

5 Volt HCMOS logic implementationmaintains low power at high speed

Schmitt trigger inputs and CMOSlogic levels improve noise immunity

Simultaneously injects equaldeadtime in up to three output phases

Replaces 10-12 standard SSI/MSIlogic devices

Allows a wide range of PWMmodulation strategies

Directly drives high speedoptocouplers

This 5 Volt HCMOS integrated circuit isintended primarily for application in three-phase sinusoidally commutated brushlessmotor, induction motor, AC servomotor orUPS PWM modulator control systems. Itinjects the required deadtime to convert asingle phase leg PWM command the twoseparate logic signals required to drive theupper and lower semiconductor switchesin a PWM inverter. It also provides facilitiesfor output disable, fast overcurrent, andfault condition shutdown.In the IXDP 630 the dead time is set by

controlling frequency of the internaloscillator using an external R.C. network.In the IXDP 631 the dead time is achievedby use of an external crystal oscillator. Analternative programming means for boththe IXDP 630/631 is by an externallyprovided clock signal.Because of its flexibility, the IXDP 630/631is easily utilized in a variety of brushed DC,trapezoidally commutated brushless DC,hybrid and VR step, or other more exoticPWM motor drive power and control circuitdesigns.


High Voltage CurrentRegulators

The IXYS IXC series of high voltagecurrent regulators consists of non-switchable, 2-terminal, AC and DCcurrent regulators.

Features• Extremely stable current characteris-

tics (±50 ppm/K)• Minimum of 450 V breakdown• Easily configured for bidirectional

current sourcing• 40 W continuous dissipation• International standard packages

JEDEC TO-220 and TO-252

Applications• PABX current sources• Telephone line terminations in PABXs

and modems• Highly stable voltage sources• Surge limiters and voltage protection

(DC and AC)• Instantaneously reacting resetable

fuses• Waveform synthesizers• Soft start-up circuits

Non-switchable regulators

This is a family of extremely stable, highvoltage current regulators with the typicaloutput characteristic shown in Figure 1.The temperature stability is based on athreshold compensation technique anduses IXYS' most recently developed highvoltage process. The complete family willbe capable of providing other intermediatecurrent levels which can be programmedon-chip during the manufacturing phase.

Specific applications are current sourcingin PABX applications, telephone lineterminations, surge protection andvoltage supply protection. Two devices ina back-to-back configuration will givebidirectional operation. Specificbidirectional applications would be seriessurge protection and soft start-upapplications from AC mains.

IXC Series VAK = 450/350 VIA(P) = 2 - 100 mARDYN = 9 - 900 kΩΩΩΩΩ

TO-252 AA(IXCY)

TO-220 AB(IXCP)

Current Regulator Nomenclature

Parts can be ordered by using the followingnomenclature:

IXCY10M45A (Example)

IX IXYSC Current Regulator

Package styleP TO-220 ABY TO-252 (D-PAK)

10 Current Rating,10 = 10 mA

M Current LevelA = Amps, M = mA,U = µA

45 Voltage rating45 = 450 V

(Blank) DC Non-switchableA AC non-switchable

Preliminary Data Sheet

Fig. 1 Current Regulator OutputCharacteristics

AC non-switchable regulators

This family consists of two DC currentregulators connected internally in seriesto regulate the current to a specifiedvalue in both directions. Its outputcharacteristics in quadrants 1 and 3 arethe same as shown in Figure 1 so thatthe current regulation is also the same inboth directions.

Fig. 2 Block diagram for the non-switchable regulator

4

1

3

4

123


IXC Series

TO-220 AB Outline


VAK Drain Source Voltage 450/350 V

PD Power Dissipation IXC_02M to IXC_50M 25 W(TC = 25°C) IXC_60M & IXC_100M 40 W

IRM Maximum Reverse Current 1 A

TJ Junction Operating Temperature -55 to +150 °CTstg Storage Temperature -55 to +150 °CTL Temperature for soldering (max. 10 s) 260 °C

MD Mounting torque with screw M3 (TO-220) 0.45/4 Nm/lb.in.with screw M3.5 (TO-220) 0.55/5 Nm/lb.in.

Symbol Definition/Condition Characteristic Values(TJ = 25°C, unless otherwise specified)

min. typ. max.

BVAK* Breakdown __M45 ID = 1.5 IA(P) 450 Vvoltage __M35 ID = 1.5 IA(P) 350 V

IA(P) Plateau 02M__ VAK = 10 V 1.9 2.0 2.5 mACurrent 10M__ 9.0 10 11.8 mA

20M__ 18 20 22 mA30M__ 28 30 35 mA

40M__ 36 40 44 mA50M__ 45 50 55 mA60M__ 56 60 64 mA

100M__ 88 100 110 mA

∆∆∆∆∆IA(P)/∆∆∆∆∆T Plateau Current Shift VAK= 10 V ±50 ppm/Kwith Temperature

∆∆∆∆∆VAK/∆∆∆∆∆ IA(p) Dynamic 02M__ VAK = 10 V 800 900 kΩResistance 10M__ 160 180 kΩ

20M__ 78 85 kΩ30M__ 40 45 kΩ40M__ 32 35 kΩ50M__ 19 21 kΩ60M__ 15 17 kΩ

100M__ 8 9 kΩ

VF Diode forward voltage drop; IF = 50mA 1.8 V

RthJC Thermal Resistance junction-to-case IXC_02M to IXC_50M 5.0 K/WIXC_60M & IXC_100M 3.1 K/W

RthJA Thermal Resistance junction-to-ambient TO-220 80 K/WTO-252 100 K/W

* Pulse test to limit power dissipation to within device capability.

Non-Switchable DC Current Regulators

TO-252 AA Outline

Dim. Millimeter InchesMin. Max. Min. Max.

A 2.19 2.38 0.086 0.094A1 0.89 1.14 0.035 0.045

A2 0 0.13 0 0.005b 0.64 0.89 0.025 0.035

b1 0.76 1.14 0.030 0.045b2 5.21 5.46 0.205 0.215

c 0.46 0.58 0.018 0.023c1 0.46 0.58 0.018 0.023

D 5.97 6.22 0.235 0.245D1 4.32 5.21 0.170 0.205

E 6.35 6.73 0.250 0.265E1 4.32 5.21 0.170 0.205

e 2.28 BSC 0.090 BSCe1 4.57 BSC 0.180 BSC

H 9.40 10.42 0.370 0.410L 0.51 1.02 0.020 0.040

L1 0.64 1.02 0.025 0.040L2 0.89 1.27 0.035 0.050L3 2.54 2.92 0.100 0.115


A 12.70 13.97 0.500 0.550B 14.73 16.00 0.580 0.630

C 9.91 10.66 0.390 0.420D 3.54 4.08 0.139 0.161

E 5.85 6.85 0.230 0.270F 2.54 3.18 0.100 0.125

G 1.15 1.65 0.045 0.065H 2.79 5.84 0.110 0.230

J 0.64 1.01 0.025 0.040K 2.54 BSC 0.100 BSC

M 4.32 4.82 0.170 0.190N 1.14 1.39 0.045 0.055

Q 0.35 0.56 0.014 0.022R 2.29 2.79 0.090 0.110

Pin connections

1 = No connection2, 4 = Positive terminal A3 = Negative terminal K

Product Marking

TO-220 types - full part numberTO-252 - last 7 alpha-numeric characters ofthe part number, e.g. CY02M45


Pin connections

1 = Terminal K12, 4 = Terminal A1, 23 = Terminal K2

Non-Switchable AC Current Regulators

Fig. 3. Equivalent circuit for theAC current regulators.

Product Marking

TO-220 types - full part numberTO-252 - last 8 alpha-numeric characters ofthe part number, e.g. CY02M45A

VKK - Volts-50 0 50

I K -

mill

iam

pere

s

-0.04

-0.03

-0.02

-0.01

0.00

0.01

0.02

0.03

0.04

Fig. 4. Output Characteristics for theIXCP30M45A current regulator.


VAK Drain Source Voltage 450/350 V

PD Power Dissipation TC = 25°C) 25 W

TJ Junction Operating Temperature -55 to +150 °CTstg Storage Temperature -55 to +150 °CTL Temperature for soldering (max. 10 s) 260 °C


Symbol Definition/Condition Characteristic Values(TJ = 25°C, unless otherwise specified)

min. typ. max.

BVAK* Breakdown __M45A ID = 1.5 IA(P) 450 Vvoltage at __M35A ID = 1.5 IA(P) 350 V

IA(P) Plateau 02M__ 1.8 2.0 2.5 mACurrent 10M__ VAK = 10 V 9.0 10 11.8 mA

20M__ 18 20 22 mA30M__ 28 30 35 mA

40M__ 36 40 44 mA50M__ 45 50 55 mA

∆∆∆∆∆IA(P)/∆∆∆∆∆T Plateau Current Shift VAK= 10 V ±50 ppm/Kwith Temperature

∆∆∆∆∆VAK/∆∆∆∆∆ IA(p) Dynamic 02M__ VAK = 10 V 800 900 kΩResistance 10M__ 160 180 kΩ

20M__ 78 85 kΩ30M__ 40 45 kΩ40M__ 32 35 kΩ50M__ 19 21 kΩ

VF Diode forward voltage drop; IF = 50mA 1.8 V

RthJC Thermal Resistance junction-to-case 5 K/WRthJA Thermal Resistance junction-to-ambient:TO-220 80 K/W

TO-252 100 K/W

* Pulse test to limit power dissipation to within device capability.Device ratings and characteristics are per chip.

IXC__A Series


Application Examples

DC and AC Overvoltage Suppression

The regulator can be used as a voltagesurge suppressor. The device is againconnected in series with the lead (Fig. 5)and would normally operate at a currentlevel lower than the plateau (Fig. 6a).

Testing & Handling Recommendations

• For initial assessment of the partswhere the customer may test thedevice characteristics in free airwithout heat sinking, the continuouspower dissipation should be keptwithin 1.5 W at ambient of 25°C. (RthJA

= 80 K/W for TO-220, and RthJA =100 K/W for TO-252)

• Normal electrostatic handlingprecautions for MOS devices shouldbe adhered to.

Soft Start-Up CircuitsHere the regulator characteristic willclamp initial current surges which canoccur when power is initially applied to aload. The device, with its 450 V capabilitycould, for example, be used with a DCpower supply or with AC mains to limitthe initial high inrush of current into lampfilaments, thereby increasing the filamentlife several times. It could, therefore, beused effectively in lighting displays and inthe transportation lighting industries.

Fig. 9. Normal fusing links inseries with each board

Fig.8. Low cost current regulatorsinstead of fuses

Fig. 6b. Incoming surge/output surgeacross load

Fig. 6a. DC surge suppression

Instantaneous "Fuse"

Another application would be protectionagainst sudden voltage droops onvoltage supply lines to logic cards incomputing systems, resulting from onecomponent suddenly shorting to ground.Normal fusing networks will drawconsiderable current during the time ittakes for the fuse to clear. This couldcause a sufficient dip in power railvoltage to cause malfunctions of theother logic cards, even with fast-blowfuses (Fig. 8). The current regulator inseries with the logic card restricts thecurrent to its own operating level (Fig. 9).Therefore the voltage supply does notbecome overloaded and the regulatorremains intact.

Fig. 7. Simple voltage source withhigh stability

IXC Series

Fig. 5. DC surge suppression

Any incoming voltage surge (Fig. 6b)less than the breakdown voltage of theregulator will be clamped by the IXCPregulator to voltage less than the plateaucurrent times the effective resistance ofthe load.

Highly Stable Voltage Sources

Another obvious application would be touse the current regulator as a source of ahighly stable current to produce a usablevoltage reference (Fig. 7). This would beeffectively independent of temperatureand a low cost approach. A high voltagereference is also possible, thanks to theirhigh breakdown voltages.

R = 100 Ω Vout = 3.5 V nominalR = 50 Ω Vout = 1.75 V nominalR = 25 Ω Vout = 0.875 V nominal

The current regulator thus provides an"instantaneous fusing" function. Whenthe logic component is replaced, theregulator resumes its normal functioningmode.

The obvious advantages to having thisregulator as fuse substitute are:

• Prevents a "dip" in the power supplyduring a fault condition

• Regulator remains intact

• Can be easily tied in with logic toindicate a "down state" board


Switchable CurrentRegulators

Symbol Test Condition Maximum Ratings

VAKR TJ = 25°C to 150°C 10M35S 350 V10M45S 450 V

VAGR TJ = 25°C to 150°C 10M35S 350 VVAGR 10M45S 450 V

VGK ±20 V

ID TC = 25°C -0.3 A

PD TC = 25°C 40 W

TJ -55 ... +150 °CTstg -55 ... +150 °CTL Temperature for Soldering (max. 10 s) 260 °C


Symbol Test Condition Characteristic Values(TJ = 25°C unless otherwise specified)

min. typ. max.

VAKR RK = 300 Ω, (Fig. 4) 10M35S 350 V10M45S 450 V

IA(P) VD = 10 V; RK = 300 Ω; (Fig. 5) 7 10 15 mA

VG(off) ID = 100 µA; VD = 300 V 10M35S -5 VID = 100 µA; VD = 400 V 10M45S -5 VFig. 4

IAV VD= 300 V; VGK = -10 V 10M35S 25 µAVD= 400 V; VGK = -10 V 10M45S 25 µAFig. 4

∆∆∆∆∆VAK/∆∆∆∆∆ IA(p Dynamic resistance; VD= 10 V 10 kΩRK = 300 Ω; (Fig. 4)

RthJC Thermal Resistance junction-to-case 3.1 K/WRthJA Thermal Resistance junction-to-ambient TO-220 80 K/W

TO-252 100 K/W

Pin connections

1 = G, Control terminal;2 and 4 = A (+) Positive terminal3 = K (-), Negative terminal

Features

• Minimum of 350/450 V breakdown• Resistor programmable current source• 40 W continuous dissipation• International standard packages

JEDEC TO-220 and TO-252• On/Off switchable current source

Applications

• Start-up circuits for SMPS• Highly stable voltage sources• Surge limiters and voltage protection• Instantaneously reacting resetable

fuses• Soft start-up circuits

98704B (05/00)

IXCP 10M35SIXCY 10M35SIXCP 10M45SIXCY 10M45S

VAK = 350/450 VIA(P) = 2 - 100 mARDYN = 9 - 900 kΩΩΩΩΩ

TO-252 AA(IXCY)

TO-220 AB(IXCP)

4

1

3

4

12

3

I

I - 25IXYS MOSFETS and IGBTs are covered by one or more of the following U.S. patents: 4,835,592 4,881,106 5,017,508 5,049,961 5,187,117 5,486,7154,850,072 4,931,844 5,034,796 5,063,307 5,237,481 5,381,025

VGS - Volts-3 .5 -3 . 0 -2 .5 -2 .0 -1 . 5 -1 . 0

0 . 1

1

1 0

1 0 0

1 0 0 0

Series Resistor RX - Ohms1 0 1 0 0 1 0 0 0 1 0 0 0 0

1

1 0

1 0 0

Fig. 3. Current regulator controlled by VG Fig. 4. Plateau current versus appliedinput voltage

Fig. 1 Resistor RK in series withnegative pin to achieve differentcurrent levels

IXCP 10M35S IXCY 10M35SIXCP 10M45S IXCY 10M45S

A (+)

G

RK

K (-)

ID(p)

VD

G

ID(p)A (+)

K (-)VGK

VD

ID(P)

mA

Fig. 2. Plateau current versus externalresistance

ID(P)

mA

TO-220 AB Outline

TO-252 AA Outline


A 2.19 2.38 0.086 0.094A1 0.89 1.14 0.035 0.045

A2 0 0.13 0 0.005b 0.64 0.89 0.025 0.035

b1 0.76 1.14 0.030 0.045b2 5.21 5.46 0.205 0.215

c 0.46 0.58 0.018 0.023c1 0.46 0.58 0.018 0.023

D 5.97 6.22 0.235 0.245D1 4.32 5.21 0.170 0.205

E 6.35 6.73 0.250 0.265E1 4.32 5.21 0.170 0.205

e 2.28 BSC 0.090 BSCe1 4.57 BSC 0.180 BSC

H 9.40 10.42 0.370 0.410L 0.51 1.02 0.020 0.040

L1 0.64 1.02 0.025 0.040L2 0.89 1.27 0.035 0.050L3 2.54 2.92 0.100 0.115


A 12.70 13.97 0.500 0.550B 14.73 16.00 0.580 0.630

C 9.91 10.66 0.390 0.420D 3.54 4.08 0.139 0.161

E 5.85 6.85 0.230 0.270F 2.54 3.18 0.100 0.125

G 1.15 1.65 0.045 0.065H 2.79 5.84 0.110 0.230

J 0.64 1.01 0.025 0.040K 2.54 BSC 0.100 BSC

M 4.32 4.82 0.170 0.190N 1.14 1.39 0.045 0.055

Q 0.35 0.56 0.014 0.022R 2.29 2.79 0.090 0.110


Symbol Test Conditions Maximum Ratings

VDSS TJ = 25°C to 150°C 900 V

VDGR TJ = 25°C to 150°C; RGS = 1 MΩ 900 V

VGS Continuous ±20 V

VGSM Transient ±30 V

PD TC = 25°C 40 W

TJ -55 ... +150 °C

TJM 150 °C

Tstg -55 ... +150 °C

TL 1.6 mm (0.062 in.) from case for 10 s 300 °C

Md Mounting torque with 3.5mm screw TO-220 0.55/5 Nm/lb.in.

Weight TO-252 = 1 g, TO-220 = 4 g

Symbol Test Conditions Characteristic Values(TJ = 25°C, unless otherwise specified)

min. typ. max.

VDSS VGS = 0 V, ID = 25 µA 900 V

VGS(th) VDS = VGS, ID = 25 µA 2.5 5 V

IGSS VGS = ±20 V, VDS = 0 ±50 nA

IDSS VDS = VDSS; VGS = 0 V 10 µA

RDS(on) VGS = 10 V, ID = 50 mA 80 ΩPulse test, t ≤ 300 µs, duty cycle d ≤ 2 %

IDP Plateau Current; VDS = 10 V, VGS = 10V 100 130 mAPulse test, t ≤ 300 µs, duty cycle d ≤ 2 %

Gate ControlledCurrent LimiterN-Channel, Enhancement Mode

D

S

Features

• High output resistance in thesaturated mode of operation

• Rugged HDMOSTM process• Stable peak drain current limit• High voltage current regulator• International standard packages

Applications

• Current regulation• Over current and over voltage

protection for sensitive loads• Linear regulator

G = Gate, D = Drain,S = Source, TAB = Drain

98701 (4/25/2000)

IXCP 01N90EIXCY 01N90E

VDSS = 900 VID(limit) = 250 mARDS(on) = 80 ΩΩΩΩΩ

G

TO-220 (IXCP)

GD

S

TAB

TO-252 (IXCY)

G

S

TAB


I

I - 27IXYS MOSFETS and IGBTs are covered by one or more of the following U.S. patents: 4,835,592 4,881,106 5,017,508 5,049,961 5,187,117 5,486,7154,850,072 4,931,844 5,034,796 5,063,307 5,237,481 5,381,025

Symbol Test Conditions Characteristic Values(TJ = 25°C, unless otherwise specified)

min. typ. max.

gfs VDS = 20 V; ID = 100 mA, pulse test 40 mS

Ciss 133 pF

Coss VGS = 0 V, VDS = 25 V, f = 1 MHz 24 pF

Crss 6.6 pF

td(on) 15 ns

tr VDS = 500 V, ID = 50 mA 137 ns

td(off) VGS = 10 V, RG = 50 Ω (External) 11 ns

tf 131 ns

Qg(on) 7.5 nC

Qgs VGS = 10 V, VDS = 500 V, ID = 50 mA 2.2 nC

Qgd 3.0 nC

∆∆∆∆∆IA(P)/∆∆∆∆∆T Plateau Current Shift VDS= 10 V, VGS= 10 V ±50 ppm/Kwith Temperature

∆∆∆∆∆VAK/∆∆∆∆∆ IA(p) Dynamic Resistance VDS = 10 V, VGS= 10 V 125 kΩ

VF IF = 50mA 1.8 V

RthJC 3.1 K/W

RthCA TO-220 80 K/WTO-252 100 K/W


TO-220 AB Outline

TO-252 AA Outline


A 2.19 2.38 0.086 0.094A1 0.89 1.14 0.035 0.045

A2 0 0.13 0 0.005b 0.64 0.89 0.025 0.035

b1 0.76 1.14 0.030 0.045b2 5.21 5.46 0.205 0.215

c 0.46 0.58 0.018 0.023c1 0.46 0.58 0.018 0.023

D 5.97 6.22 0.235 0.245D1 4.32 5.21 0.170 0.205

E 6.35 6.73 0.250 0.265E1 4.32 5.21 0.170 0.205

e 2.28 BSC 0.090 BSCe1 4.57 BSC 0.180 BSC

H 9.40 10.42 0.370 0.410L 0.51 1.02 0.020 0.040

L1 0.64 1.02 0.025 0.040L2 0.89 1.27 0.035 0.050L3 2.54 2.92 0.100 0.115


A 12.70 13.97 0.500 0.550B 14.73 16.00 0.580 0.630

C 9.91 10.66 0.390 0.420D 3.54 4.08 0.139 0.161

E 5.85 6.85 0.230 0.270F 2.54 3.18 0.100 0.125

G 1.15 1.65 0.045 0.065H 2.79 5.84 0.110 0.230

J 0.64 1.01 0.025 0.040K 2.54 BSC 0.100 BSC

M 4.32 4.82 0.170 0.190N 1.14 1.39 0.045 0.055

Q 0.35 0.56 0.014 0.022R 2.29 2.79 0.090 0.110


Temperature - oC-50 -25 0 25 50 75 100 125

80

100

120

140

160

180

VGS = 12V

11V

10V

9V

Figure 1, Output Characteristics at

Figure 4. Drain Current vs, Temperature for a constantgate-source voltage.

Figure 2. Drain Current vs.Gate Voltage

Figure 3. Dynamic Output Resistance RO vs. Drain Current.

0 20 40 60 80 100 120 140 1600K

100K

200K

300K

400K

500K

ID - Milliamperes

TJ = 25oC

Figure 5. Allowable Power Dissipation for various heat sinkingconditions. Note that the junction temperature canbe derated by increasing the ambient temperaturea like amount.

VGS -Volts6 8 10 12 14

I D -

Mill

iam

pere

s

1

10

100

Ambient Temperature - oC

25 50 75 100 125 150

Max

imum

Pow

er D

issi

patio

n - W

atts

0

2

4

6

8

10

12

15

20

30 40 506080100

R(th)JA : 10 K/W

VDS - Volts0 10 20 30 40 50

I D -

Mill

iam

pere

s

0

50

100

150

200

250

14V

13V

12V

11V

10V

9V8V

6V5V

VGS = 15V

7V


RO

ΩID

mA


Type Package Temperature Range°C

IXMS 150 PSI 24-Pin Skinny DIP -40 to 85

Dual Pulse Width Modulation Controller, IXMS 150

Features

Two complete, synchronous PWMs

Wide frequency range: 10 kHz to400 kHz

1 % gain matching between channelswithout external trim

1.6 % gain linearity

Feedforward compensation to removesupply voltage ripple from load current

Only 1 current sense resistor perphase

Onchip overcurrent and short circuitprotection

Undervoltage lockout assures properoperation during power-up and -down

Enable input for external faultprotection

Applications

Full, half, quarter, or microstepping2-phase step motor position controller

Dual DC servo motor torque controller

Solenoid actuator force controller

General 2-channel current-commanded PWM control

The IXMS is a high performancemonolithic 2-channel PWM controller. It isdesigned and intended specifically tocontrol the current in two independentPWM load circuits. Implemented inCMOS, the low-power IXMS 150precisely controls the current in each oftwo separate power drivers (typically H-bridge power circuits) using uniquesampling and signal processingtechniques. Each channel contains anerror amplifier, PWM, feedback amplifier,and protection circuitry. Protectionfeatures include over/excess currentshutdown, min/max duty cycle clamp,undervoltage lockout, dead time insertion,and a shutdown input for over-temperature or other external faultcircuitry. Other features are a commonoscillator, feedforward circuit for motor

supply compensation, and an on-chipnegative bias generator.

The IXMS 150 has been optimized formicrostep control 2-phase step motors.Due to its high accuracy, it allows acontrol system resolution in excess of250 microsteps per step, or 50,000steps per revolution with a 200 stepmotor. This greatly improves positionresolution and accuracy, and virtuallyeliminates low speed velocity ripple andresonance effects at a fraction of thecost of a board-level microsteppingsystem. Other applications that are idealfor the IXMS 150 include control of oneor two DC servo motors, 2-phase ACmotors, and synchronous reluctancemotors in X-Y stage, plotters, printers,paper-handling systems, and robotics.

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