ia-32 & amd64 - d3s – department of distributed and...

116
http://d3s.mff.cuni.cz Crash Dump Analysis 2015/2016 CHARLES UNIVERSITY IN PRAGUE faculty of mathemacs and physics faculty of mathemacs and physics IA-32 & AMD64 IA-32 & AMD64

Upload: truongtu

Post on 26-Jun-2018

218 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

http://d3s.mff.cuni.czCrash Dump Analysis 2015/2016

CHARLES UNIVERSITY IN PRAGUE

faculty of mathematics and physicsfaculty of mathematics and physics

IA-32 & AMD64IA-32 & AMD64

Page 2: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 2IA-32 & AMD64

IA-32 OverviewIA-32 Overview

32bit CISC architectureStarts with 80386

Also known as x86, i386, i586, i686, etc.Strong inheritance from 8086, even 8080

Some RISC characteristics after Pentium (P5, i586)Variable instruction sizeNon-orthogonal instruction setMost instructions can have memory operands

Page 3: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 3IA-32 & AMD64

IA-32 Overview (2)IA-32 Overview (2)

32bit CISC architecture (cont.)Very few GPRs (8)

Actually only 6 or 7 practically usable (ABI dependent)Little-endianImplicit stackComplicated memory management

Several operational modesReal mode (8086), V86 (virtual 8086), 16bit Protected mode (80286), 32bit Protected mode (80386+), SMM, …

Paging and segmentation

Page 4: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 4IA-32 & AMD64

AMD64 OverviewAMD64 Overview

Natural extension of IA-32Originally created by AMD (hence AMD64)

Later also adopted by Intel (as IA-32e, IA-64t, EM64T, Intel 64)

Vendor-neutral names such as x86-64, x64

Many properties of IA-32 apply also to AMD64Key differences

64bit architecture16 GPRs (14 practically usable)Segmentation almost eliminated(except two remaining simplified segments)

Page 5: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 5IA-32 & AMD64

Aside: Little vs. Big EndianAside: Little vs. Big Endian

Memory is usually addressed in bytes (8 bits)Several ways how to store values larger than one byte as a sequence of bytes (byte order)

v = 0xAA884400

Big-Endianbig end firstmost significant byte first

AA 88 44 00

0 1 2 3

Litte-Endianlittle end firstleast significant byte first

00 44 88 AA

0 1 2 3

Page 6: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 6IA-32 & AMD64

Aside: Little vs. Big Endian (2)Aside: Little vs. Big Endian (2)

Caution: Basic element size might varyLittle-Endian example, byte addressing

Basic element size = 16 bitsv = 0xAA884400

4400 AA88

0 1 2 3

44 00 AA 88

0 1 2 3

Page 7: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 7IA-32 & AMD64

Intel ManualsIntel Manuals

Intel 64 and IA-32 Architectures Software Developer's Manual

Volume 1: Basic ArchitectureVolume 2A + 2B: Instruction Set ReferenceVolume 3A + 3B: System Programming Guide

Intel 64 and IA-32 Architectures Optimization Reference Manual

http://www.intel.com/products/processor/manuals

Page 8: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 8IA-32 & AMD64

AMD ManualsAMD Manuals

AMD64 Architecture Programmer's ManualVolume 1: Application ProgrammingVolume 2: System ProgrammingVolume 3: General-Purpose and System Instructions

Software Optimization Guide for AMD64 Processors

http://developer.amd.com/resources/documentation-articles/developer-guides-manuals/

Page 9: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 9IA-32 & AMD64

IA-32 ABIIA-32 ABI

System V Application Binary Interface, Intel386 Architecture Processor Supplement

Authoritative source for GNU/Linux (e.g. the GCC toolchain), *BSD, most UNIXes, etc.We will use a simplified view sufficient for common cases (integer arguments, etc.)

http://www.sco.com/developers/devspecs/abi386-4.pdf

Page 10: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 10IA-32 & AMD64

AMD64 ABIAMD64 ABI

System V Application Binary Interface, AMD64 Architecture Processor Supplement

Authoritative source for GNU/Linux (e.g. the GCC toolchain), *BSD, most UNIXes, etc.We will use a simplified view sufficient for common cases (integer arguments, etc.)

http://www.x86-64.org/documentation/abi.pdf

Page 11: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 11IA-32 & AMD64

IA-32 RegistersIA-32 Registers

AH ALAX

EAX

BH BLBX

EBX

CH CLCX

ECX

DH DLDX

EDX

DIEDI

SIESI

BPEBP

SPESP

FLAGSEFLAGS

CS DS ES SS FS GS

GPRs

return value

IPEIP

frame pointer stack pointer

control registers

segment registers

Page 12: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 12IA-32 & AMD64

IA-32 ABI in a NutshellIA-32 ABI in a Nutshell

Arguments passed on stackIn reverse order (the last argument is pushed first)

Return valueFor simple integer types in EAX

Otherwise on the stack

Implicit stack pointerSome instructions use ESP as implicit register operand

Page 13: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 13IA-32 & AMD64

IA-32 ABI in a Nutshell (2)IA-32 ABI in a Nutshell (2)

Frame pointerUsually (not always) stored in EBP

Volatile (scratch, caller-saved) registersEAX, ECX, EDX

Non-volatile (preserved, callee-saved) registersEBX, EDI, ESI, EBP, ESP

Stack aligned on 4B boundarySome compilers use even larger alignment

Page 14: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 14IA-32 & AMD64

AMD64 RegistersAMD64 RegistersAH AL

AXEAX

RAX

BH BLBX

EBXRBX

CH CLCX

ECXRCX

DH DLDX

EDXRDX

DILDI

EDIRDI

SILSI

ESIRSI

BPLBP

EBPRBP

SPLSP

ESPRSP

Page 15: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 15IA-32 & AMD64

AMD64 Registers (2)AMD64 Registers (2)R8B

R8WR8D

R8

R9BR9W

R9DR9

R10B

R10WR10D

R10

R11B

R11WR11D

R11

R12B

R12WR12D

R12

R13B

R13WR13D

R13

R14B

R14WR14D

R14

R15B

R15WR15D

R15

Page 16: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 16IA-32 & AMD64

AMD64 Registers (3)AMD64 Registers (3)

CS DS ES SS FS GS

FLAGSEFLAGS

RFLAGS

IPEIP

RIP

Page 17: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 17IA-32 & AMD64

AMD64 ABI in a NutshellAMD64 ABI in a Nutshell

First six integer arguments passed in registersRDI, RSI, RDX, RCX, R8, R9

Additional/complex arguments passed on stackIn reverse order (the last argument is pushed first)

Return valueFor simple integer types in RAX

Otherwise on the stack

Implicit stack (RSP) and frame (RBP) pointer

Page 18: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 18IA-32 & AMD64

AMD64 ABI in a Nutshell (2)AMD64 ABI in a Nutshell (2)

Volatile (scratch, caller-saved) registersRAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11

Non-volatile (preserved, callee-saved) registersRBX, RBP, RSP, R12, R13, R14, R15

Stack aligned on 8B boundary, but not 16B aligned on function's entry point

Thus each stack frame is 16B alignedSupport for easy spilling of FPU and SSE registers

Some GCC builds apparently ignore this rule

Page 19: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 19IA-32 & AMD64

AMD64 ABI in a Nutshell (3)AMD64 ABI in a Nutshell (3)

128B red-zone at RSP - 128Optimization

Functions do not need to allocate stack spaceSignal and interrupt handlers must avoid this areaSometimes the red-zone is disabled

gcc -mno-red-zone

Page 20: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 20IA-32 & AMD64

IA-32 Instruction SetIA-32 Instruction Set

Hundreds of instructionsMost of them have several variants (operands as registers, operands as memory addresses, etc.)

Informal classificationGeneral purpose (arithmetic, logic, jumps, etc.)System instructions (altering processor mode)FPU instructionsSIMD and other instructions (MMX, SSE, etc.)

Page 21: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 21IA-32 & AMD64

IA-32 Instruction Set (2)IA-32 Instruction Set (2)

Most general purpose instructions have two operands

register – registerimmediate – registermemory – registerimmediate – memory

INST opl, oprAT&T syntax

opr ← opr INST oplIntel syntax

opl ← opl INST opr

ADDL EAX, EBXEBX ← EBX + EAX

Page 22: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 22IA-32 & AMD64

IA-32 AT&T SyntaxIA-32 AT&T Syntax

Left operand: sourceRight operand: destinationRegister names prefixed by %

%eax

Immediate operands prefixed by $$0x1

Operand size encoded as instruction suffixb (byte, 8 bit), w (word, 16 bit), l (long, 32 bit)movl $0x1, %eax

Page 23: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 23IA-32 & AMD64

IA-32 AT&T Syntax (2)IA-32 AT&T Syntax (2)

Memory operandsUsing implicit segment register

displacement(base, index, scale)base and index are GPRsscale is 1, 2, 4 or 8 (defaults to 1 if not specified)displacement is an immediate offset

Effective address is calculated asEA = displacement + base + index * scale

0x8111f30, 0x8(%ebp), -0x28(%eax), -0x2(%esi, %eax, 2)mov (%esp), %edi

Page 24: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 24IA-32 & AMD64

IA-32 AT&T Syntax (3)IA-32 AT&T Syntax (3)

Memory operands with explicit segment registersegment_register:displacement(base, index, scale)Segmentation is exploited only infrequently in modern OSes

Cannot be turned offMostly used for thread-local storage, current thread pointer in kernel, etc.

movl %gs:0x10, %eax

When accessing memory, the segment base is always applied (added) to the effective address

Also in the case of implicit segment registers

Page 25: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 25IA-32 & AMD64

Common IA-32 InstructionsCommon IA-32 Instructions

Real programs tend to use a limited set of instructions most of the time

NOP, MOV, LEAADD, SUB, INC, DECXOR, AND, ORPUSH, POP, CALL, RETCMP, TESTJMP, JE, JNE, JL, JB, JG, JA

Page 26: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 26IA-32 & AMD64

Common IA-32 Instructions (2)Common IA-32 Instructions (2)

NOPSingle byte instruction, opcode 0x90

There are multibyte variants using prefixesNo operation (actually XCHG EAX, EAX)Important role for optimization and debugging

MOVMove between registersMemory loads and stores

Page 27: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 27IA-32 & AMD64

Common IA-32 Instructions (3)Common IA-32 Instructions (3)

LEAEvaluate effective address of a memory operandFrequently used as a “fused multiply-add” operation

EA = displacement + base + index * scale

leal (%edx, %edx, 8), %eaxEAX ← EDX + 8 * EDX (= 9 * EDX)

Page 28: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 28IA-32 & AMD64

Common IA-32 Instructions (4)Common IA-32 Instructions (4)

ADD, SUB, XOR, AND, ORAddition, subtraction, logical exclusive OR, logical AND, logical ORxorl %ebx, %ebx

INC, DECIncrement, decrementOnly one operandincb %al

Page 29: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 29IA-32 & AMD64

Common IA-32 Instructions (5)Common IA-32 Instructions (5)

PUSHStore register value on stack

pushl %ecx

ESP ← ESP - 4(ESP) ← ECX

POPRestore register value from stack

popl %edx

EDX ← (ESP)ESP ← ESP + 4

Page 30: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 30IA-32 & AMD64

Common IA-32 Instructions (6)Common IA-32 Instructions (6)

CALLCall subroutine (function)

call -0x8da0

ESP ← ESP - 4(ESP) ← EIP + instr_sizeEIP ← EIP - 0x8da0

RETReturn from subroutine (function) call

ret

ESP ← ESP + 4EIP ← (ESP - 4)

Page 31: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 31IA-32 & AMD64

Common IA-32 Instructions (7)Common IA-32 Instructions (7)

CMPCompare two operands

Like SUB, but the result is discardedModifies bits in the EFLAGS registercmpb $0x2f, (%esi)

TESTTest bits

Like AND, but result is discarded and EFLAGS is modifiedtest %eax, %eax

Page 32: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 32IA-32 & AMD64

Common IA-32 Instructions (8)Common IA-32 Instructions (8)

JMPUnconditional jumpSeveral variants

Relative address as immediate operandLong jump

JE, JNE, JL, JB, JA, ...Conditional branches (many mnemonics)Condition: State of bits in EFLAGS

Relative address as immediate operand (±128 B)

Page 33: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 33IA-32 & AMD64

AMD64 Instruction SetAMD64 Instruction Set

Instructions have mostly the same syntax as in IA-32Notable differences

New registers, new aliases, RFLAGSNew operand size q (quad, 64 bits)32bit operand instructions affect the upper 32 bits of registersEffective address can use RIP as a base

cmpq +0x305f9e(%rip),%r13

Page 34: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 34IA-32 & AMD64

IA-32 Function PrologueIA-32 Function Prologue

pushl %ebpmovl %esp, %ebpsubl $imm, %espmovl %ebx, 4(%esp) pushl %edi…

Page 35: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 35IA-32 & AMD64

IA-32 Function EpilogueIA-32 Function Epilogue

popl %edi

movl 4(%esp), %ebx

movl %ebp, %esp

popl %ebp

ret

popl %edi

movl 4(%esp),%ebx

leave

ret

Page 36: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 36IA-32 & AMD64

AMD64 Function PrologueAMD64 Function Prologue

pushq %rbp

movq %rsp, %rbp

subq $imm, %rsp

movq %rdi, -8(%rbp) # save the first argument on stack

pushq %r12 # save the preserved register

...

Page 37: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 37IA-32 & AMD64

AMD64 Function Prologue (2)AMD64 Function Prologue (2)

Sometimes compilers generate code which saves arguments passed in registers into the stack frame

Good for debuggingBad for performance

gcc -msave-argssuncc -Wu,-save_args

Page 38: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 38IA-32 & AMD64

AMD64 Function EpilogueAMD64 Function Epilogue

popq %r13

movq 8(%rsp), %r12

movq %rbp, %rsp

popq %rbp

ret

popq %r13

movq 8(%rsp),%r12

leave

ret

Page 39: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 39IA-32 & AMD64

IA-32 Stack and Code ExampleIA-32 Stack and Code Example

Recall: Functions a(), b(), c() from BasicsCompile using gcc -O1 for IA-32Disassemble and single-step main() and a()Observe the stack

Page 40: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 40IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)a: pushl %ebpa+1: movl %esp,%ebpa+3: subl $0x14,%espa+6: pushl 0x8(%ebp)a+9: call +0x5 <b>a+0xe: addl $0x10,%espa+0x11: leave a+0x12: ret

main: pushl %ebpmain+1: movl %esp,%ebpmain+3: subl $0x8,%espmain+6: andl $0xfffffff0,%espmain+9: subl $0x1c,%espmain+0xc: pushl 0x8(%ebp)main+0xf: call -0x3f <a>main+0x14: leave main+0x15: ret

Page 41: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 41IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

main: pushl %ebpmain+1: movl %esp,%ebpmain+3: subl $0x8,%espmain+6: andl $0xfffffff0,%espmain+9: subl $0x1c,%espmain+0xc: pushl 0x8(%ebp)main+0xf: call -0x3f <a>main+0x14: leave main+0x15: ret

Initial stateNo instructions executedInherited stack pointerfrom main()'s caller

0x8046bf0: _start+0x80

Page 42: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 42IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

main: pushl %ebpmain+1: movl %esp,%ebpmain+3: subl $0x8,%espmain+6: andl $0xfffffff0,%espmain+9: subl $0x1c,%espmain+0xc: pushl 0x8(%ebp)main+0xf: call -0x3f <a>main+0x14: leave main+0x15: ret

Save previous frame pointeron the stack

0x8046bec: 0x8046c040x8046bf0: _start+0x80

Page 43: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 43IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

main: pushl %ebpmain+1: movl %esp,%ebpmain+3: subl $0x8,%espmain+6: andl $0xfffffff0,%espmain+9: subl $0x1c,%espmain+0xc: pushl 0x8(%ebp)main+0xf: call -0x3f <a>main+0x14: leave main+0x15: ret

Establish new fixed framepointer in EBP

It points to where we savedthe previous one

0x8046bec: 0x8046c040x8046bf0: _start+0x80

Page 44: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 44IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

main: pushl %ebpmain+1: movl %esp,%ebpmain+3: subl $0x8,%espmain+6: andl $0xfffffff0,%espmain+9: subl $0x1c,%espmain+0xc: pushl 0x8(%ebp)main+0xf: call -0x3f <a>main+0x14: leave main+0x15: ret

Allocate some spaceon the stack

Will not be used

0x8046be4: _init+0x1a0x8046be8: 0xfeffb7dc0x8046bec: 0x8046c040x8046bf0: _start+0x80

Page 45: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 45IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

main: pushl %ebpmain+1: movl %esp,%ebpmain+3: subl $0x8,%espmain+6: andl $0xfffffff0,%espmain+9: subl $0x1c,%espmain+0xc: pushl 0x8(%ebp)main+0xf: call -0x3f <a>main+0x14: leave main+0x15: ret

Align the stack pointeron 16B boudary

Not required by the ABIPerformance reasons

0x8046be0: 0x8046bec0x8046be4: _init+0x1a0x8046be8: 0xfeffb7dc0x8046bec: 0x8046c040x8046bf0: _start+0x80

Page 46: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 46IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

main: pushl %ebpmain+1: movl %esp,%ebpmain+3: subl $0x8,%espmain+6: andl $0xfffffff0,%espmain+9: subl $0x1c,%espmain+0xc: pushl 0x8(%ebp)main+0xf: call -0x3f <a>main+0x14: leave main+0x15: ret

Allocate some more spaceon the stack

Will not be used

0x8046bc4: _fpstart+0x2c0x8046bc8: 0x29 0x8046bcc: _fp_hw0x8046bd0: 0x133f 0x8046bd4: 0x8050cda0x8046bd8: 0x8060d3c0x8046bdc: 0x8046bcc0x8046be0: 0x8046bec0x8046be4: _init+0x1a0x8046be8: 0xfeffb7dc0x8046bec: 0x8046c040x8046bf0: _start+0x80

Page 47: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 47IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

main: pushl %ebpmain+1: movl %esp,%ebpmain+3: subl $0x8,%espmain+6: andl $0xfffffff0,%espmain+9: subl $0x1c,%espmain+0xc: pushl 0x8(%ebp)main+0xf: call -0x3f <a>main+0x14: leave main+0x15: ret

Copy the incomingargument (argc) to theoutgoing argument (a)

0x8046bc0: 10x8046bc4: _fpstart+0x2c0x8046bc8: 0x29 0x8046bcc: _fp_hw0x8046bd0: 0x133f 0x8046bd4: 0x8050cda0x8046bd8: 0x8060d3c0x8046bdc: 0x8046bcc0x8046be0: 0x8046bec0x8046be4: _init+0x1a0x8046be8: 0xfeffb7dc0x8046bec: 0x8046c040x8046bf0: _start+0x80

Page 48: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 48IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

main: pushl %ebpmain+1: movl %esp,%ebpmain+3: subl $0x8,%espmain+6: andl $0xfffffff0,%espmain+9: subl $0x1c,%espmain+0xc: pushl 0x8(%ebp)main+0xf: call -0x3f <a>main+0x14: leave main+0x15: ret

Call a()

0x8046bbc: main+0x140x8046bc0: 10x8046bc4: _fpstart+0x2c0x8046bc8: 0x29 0x8046bcc: _fp_hw0x8046bd0: 0x133f 0x8046bd4: 0x8050cda0x8046bd8: 0x8060d3c0x8046bdc: 0x8046bcc0x8046be0: 0x8046bec0x8046be4: _init+0x1a0x8046be8: 0xfeffb7dc0x8046bec: 0x8046c040x8046bf0: _start+0x80

Page 49: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 49IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

Save the previous framepointer to the stack

a: pushl %ebpa+1: movl %esp,%ebpa+3: subl $0x14,%espa+6: pushl 0x8(%ebp)a+9: call +0x5 <b>a+0xe: addl $0x10,%espa+0x11: leave a+0x12: ret

0x8046bb8: 0x8046bec0x8046bbc: main+0x140x8046bc0: 10x8046bc4: _fpstart+0x2c0x8046bc8: 0x29 0x8046bcc: _fp_hw0x8046bd0: 0x133f 0x8046bd4: 0x8050cda0x8046bd8: 0x8060d3c0x8046bdc: 0x8046bcc0x8046be0: 0x8046bec0x8046be4: _init+0x1a0x8046be8: 0xfeffb7dc0x8046bec: 0x8046c040x8046bf0: _start+0x80

Page 50: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 50IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

Establish new framepointer in EBP

It points to the addresswhere the previous oneis stored

a: pushl %ebpa+1: movl %esp,%ebpa+3: subl $0x14,%espa+6: pushl 0x8(%ebp)a+9: call +0x5 <b>a+0xe: addl $0x10,%espa+0x11: leave a+0x12: ret

0x8046bb8: 0x8046bec0x8046bbc: main+0x140x8046bc0: 10x8046bc4: _fpstart+0x2c0x8046bc8: 0x29 0x8046bcc: _fp_hw0x8046bd0: 0x133f 0x8046bd4: 0x8050cda0x8046bd8: 0x8060d3c0x8046bdc: 0x8046bcc0x8046be0: 0x8046bec0x8046be4: _init+0x1a0x8046be8: 0xfeffb7dc0x8046bec: 0x8046c040x8046bf0: _start+0x80

Page 51: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 51IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

Allocate some spaceon the stack

Will not be used

a: pushl %ebpa+1: movl %esp,%ebpa+3: subl $0x14,%espa+6: pushl 0x8(%ebp)a+9: call +0x5 <b>a+0xe: addl $0x10,%espa+0x11: leave a+0x12: ret

0x8046ba4: 0x80509e8 0x8046ba8: dbg_desc0x8046bac: 80x8046bb0: 10x8046bb4: 00x8046bb8: 0x8046bec0x8046bbc: main+0x140x8046bc0: 10x8046bc4: _fpstart+0x2c0x8046bc8: 0x29 0x8046bcc: _fp_hw0x8046bd0: 0x133f 0x8046bd4: 0x8050cda0x8046bd8: 0x8060d3c0x8046bdc: 0x8046bcc0x8046be0: 0x8046bec0x8046be4: _init+0x1a0x8046be8: 0xfeffb7dc0x8046bec: 0x8046c040x8046bf0: _start+0x80

Page 52: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 52IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

Copy the incomingargument of a() to theoutgoing argument forb()

a: pushl %ebpa+1: movl %esp,%ebpa+3: subl $0x14,%espa+6: pushl 0x8(%ebp)a+9: call +0x5 <b>a+0xe: addl $0x10,%espa+0x11: leave a+0x12: ret

0x8046ba0: 10x8046ba4: 0x80509e8 0x8046ba8: dbg_desc0x8046bac: 80x8046bb0: 10x8046bb4: 00x8046bb8: 0x8046bec0x8046bbc: main+0x140x8046bc0: 10x8046bc4: _fpstart+0x2c0x8046bc8: 0x29 0x8046bcc: _fp_hw0x8046bd0: 0x133f 0x8046bd4: 0x8050cda0x8046bd8: 0x8060d3c0x8046bdc: 0x8046bcc0x8046be0: 0x8046bec0x8046be4: _init+0x1a0x8046be8: 0xfeffb7dc0x8046bec: 0x8046c040x8046bf0: _start+0x80

Page 53: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 53IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

Call b()

a: pushl %ebpa+1: movl %esp,%ebpa+3: subl $0x14,%espa+6: pushl 0x8(%ebp)a+9: call +0x5 <b>a+0xe: addl $0x10,%espa+0x11: leave a+0x12: ret

0x8046b9c: a+0xe0x8046ba0: 10x8046ba4: 0x80509e8 0x8046ba8: dbg_desc0x8046bac: 80x8046bb0: 10x8046bb4: 00x8046bb8: 0x8046bec0x8046bbc: main+0x140x8046bc0: 10x8046bc4: _fpstart+0x2c0x8046bc8: 0x29 0x8046bcc: _fp_hw0x8046bd0: 0x133f 0x8046bd4: 0x8050cda0x8046bd8: 0x8060d3c0x8046bdc: 0x8046bcc0x8046be0: 0x8046bec0x8046be4: _init+0x1a0x8046be8: 0xfeffb7dc0x8046bec: 0x8046c040x8046bf0: _start+0x80

Page 54: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 54IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

Step through and returnfrom b()

b()'s return value is in EAX

a: pushl %ebpa+1: movl %esp,%ebpa+3: subl $0x14,%espa+6: pushl 0x8(%ebp)a+9: call +0x5 <b>a+0xe: addl $0x10,%espa+0x11: leave a+0x12: ret

0x8046ba0: 10x8046ba4: 0x80509e8 0x8046ba8: dbg_desc0x8046bac: 80x8046bb0: 10x8046bb4: 00x8046bb8: 0x8046bec0x8046bbc: main+0x140x8046bc0: 10x8046bc4: _fpstart+0x2c0x8046bc8: 0x29 0x8046bcc: _fp_hw0x8046bd0: 0x133f 0x8046bd4: 0x8050cda0x8046bd8: 0x8060d3c0x8046bdc: 0x8046bcc0x8046be0: 0x8046bec0x8046be4: _init+0x1a0x8046be8: 0xfeffb7dc0x8046bec: 0x8046c040x8046bf0: _start+0x80

Page 55: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 55IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

Destroy a()'s stack frame

a: pushl %ebpa+1: movl %esp,%ebpa+3: subl $0x14,%espa+6: pushl 0x8(%ebp)a+9: call +0x5 <b>a+0xe: addl $0x10,%espa+0x11: leave a+0x12: ret

0x8046bbc: main+0x140x8046bc0: 10x8046bc4: _fpstart+0x2c0x8046bc8: 0x29 0x8046bcc: _fp_hw0x8046bd0: 0x133f 0x8046bd4: 0x8050cda0x8046bd8: 0x8060d3c0x8046bdc: 0x8046bcc0x8046be0: 0x8046bec0x8046be4: _init+0x1a0x8046be8: 0xfeffb7dc0x8046bec: 0x8046c040x8046bf0: _start+0x80

Page 56: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 56IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

Return back to main()Return value is again in EAX

a: pushl %ebpa+1: movl %esp,%ebpa+3: subl $0x14,%espa+6: pushl 0x8(%ebp)a+9: call +0x5 <b>a+0xe: addl $0x10,%espa+0x11: leave a+0x12: ret

0x8046bc0: 10x8046bc4: _fpstart+0x2c0x8046bc8: 0x29 0x8046bcc: _fp_hw0x8046bd0: 0x133f 0x8046bd4: 0x8050cda0x8046bd8: 0x8060d3c0x8046bdc: 0x8046bcc0x8046be0: 0x8046bec0x8046be4: _init+0x1a0x8046be8: 0xfeffb7dc0x8046bec: 0x8046c040x8046bf0: _start+0x80

Page 57: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 57IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

main: pushl %ebpmain+1: movl %esp,%ebpmain+3: subl $0x8,%espmain+6: andl $0xfffffff0,%espmain+9: subl $0x1c,%espmain+0xc: pushl 0x8(%ebp)main+0xf: call -0x3f <a>main+0x14: leave main+0x15: ret

Destroy main()'s stackframe

0x8046bf0: _start+0x80

Page 58: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 58IA-32 & AMD64

IA-32 Stack and Code Example (2)IA-32 Stack and Code Example (2)

main: pushl %ebpmain+1: movl %esp,%ebpmain+3: subl $0x8,%espmain+6: andl $0xfffffff0,%espmain+9: subl $0x1c,%espmain+0xc: pushl 0x8(%ebp)main+0xf: call -0x3f <a>main+0x14: leave main+0x15: ret

Return from main()

Page 59: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 59IA-32 & AMD64

AMD64 Stack and Code ExampleAMD64 Stack and Code Example

Recall: Functions a(), b(), c() from BasicsCompile using gcc -O1 -m64 for AMD64Disassemble and single-step main() and a()Observe the stack

Page 60: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 60IA-32 & AMD64

AMD64 Stack and Code Example (2)AMD64 Stack and Code Example (2)a: pushq %rbpa+1: movq %rsp,%rbpa+4: movl $0x0,%eaxa+9: call +0x2 <b>a+0xe: leave a+0xf: ret

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: call -0x2c <a>main+9: leave main+0xa: ret

Page 61: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 61IA-32 & AMD64

AMD64 Stack and Code Example (2)AMD64 Stack and Code Example (2)

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: call -0x2c <a>main+9: leave main+0xa: ret

0xfffffd7fffdffbf8: _start+0x6c

Initial stateNo instructionsexecutedInherited stackpointer frommain()'s caller

Page 62: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 62IA-32 & AMD64

AMD64 Stack and Code Example (2)AMD64 Stack and Code Example (2)

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: call -0x2c <a>main+9: leave main+0xa: ret 0xfffffd7fffdffbf0: 0xfffffd7fffdffc00

0xfffffd7fffdffbf8: _start+0x6c

Save previous framepointer on the stack

Page 63: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 63IA-32 & AMD64

AMD64 Stack and Code Example (2)AMD64 Stack and Code Example (2)

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: call -0x2c <a>main+9: leave main+0xa: ret 0xfffffd7fffdffbf0: 0xfffffd7fffdffc00

0xfffffd7fffdffbf8: _start+0x6c

Establish new fixedframe pointer in RBP

It points to where wesaved the previousone

Page 64: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 64IA-32 & AMD64

AMD64 Stack and Code Example (2)AMD64 Stack and Code Example (2)

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: call -0x2c <a>main+9: leave main+0xa: ret 0xfffffd7fffdffbe8: main+9

0xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Call a()The argument ispassed in RDI

Page 65: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 65IA-32 & AMD64

AMD64 Stack and Code Example (2)AMD64 Stack and Code Example (2)a: pushq %rbpa+1: movq %rsp,%rbpa+4: movl $0x0,%eaxa+9: call +0x2 <b>a+0xe: leave a+0xf: ret

0xfffffd7fffdffbe0: 0xfffffd7fffdffbf00xfffffd7fffdffbe8: main+90xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Save the previousframe pointer to thestack

Page 66: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 66IA-32 & AMD64

AMD64 Stack and Code Example (2)AMD64 Stack and Code Example (2)a: pushq %rbpa+1: movq %rsp,%rbpa+4: movl $0x0,%eaxa+9: call +0x2 <b>a+0xe: leave a+0xf: ret

0xfffffd7fffdffbe0: 0xfffffd7fffdffbf00xfffffd7fffdffbe8: main+90xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Establish new framepointer in RBP

It points to theaddress where theprevious one is stored

Page 67: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 67IA-32 & AMD64

AMD64 Stack and Code Example (2)AMD64 Stack and Code Example (2)a: pushq %rbpa+1: movq %rsp,%rbpa+4: movl $0x0,%eaxa+9: call +0x2 <b>a+0xe: leave a+0xf: ret

0xfffffd7fffdffbd8: a+0xe0xfffffd7fffdffbe0: 0xfffffd7fffdffbf00xfffffd7fffdffbe8: main+90xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Zero EAXZero-extend to upper32bits of RAX

Clears the whole RAXNot needed

Page 68: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 68IA-32 & AMD64

AMD64 Stack and Code Example (2)AMD64 Stack and Code Example (2)a: pushq %rbpa+1: movq %rsp,%rbpa+4: movl $0x0,%eaxa+9: call +0x2 <b>a+0xe: leave a+0xf: ret

0xfffffd7fffdffbd8: a+0xe0xfffffd7fffdffbe0: 0xfffffd7fffdffbf00xfffffd7fffdffbe8: main+90xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Call b()The argument is stillin RDI

Page 69: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 69IA-32 & AMD64

AMD64 Stack and Code Example (2)AMD64 Stack and Code Example (2)a: pushq %rbpa+1: movq %rsp,%rbpa+4: movl $0x0,%eaxa+9: call +0x2 <b>a+0xe: leave a+0xf: ret

0xfffffd7fffdffbe0: 0xfffffd7fffdffbf00xfffffd7fffdffbe8: main+90xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Step through andreturn from b()

b()'s return value isin RAX

Page 70: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 70IA-32 & AMD64

AMD64 Stack and Code Example (2)AMD64 Stack and Code Example (2)a: pushq %rbpa+1: movq %rsp,%rbpa+4: movl $0x0,%eaxa+9: call +0x2 <b>a+0xe: leave a+0xf: ret

0xfffffd7fffdffbe8: main+90xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Destroy a()'s stackframe

Page 71: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 71IA-32 & AMD64

AMD64 Stack and Code Example (2)AMD64 Stack and Code Example (2)a: pushq %rbpa+1: movq %rsp,%rbpa+4: movl $0x0,%eaxa+9: call +0x2 <b>a+0xe: leave a+0xf: ret

0xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Return back tomain()

Return value is againin RAX

Page 72: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 72IA-32 & AMD64

AMD64 Stack and Code Example (2)AMD64 Stack and Code Example (2)

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: call -0x2c <a>main+9: leave main+0xa: ret

0xfffffd7fffdffbf8: _start+0x6c

Destroy main()'sstack frame

Page 73: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 73IA-32 & AMD64

AMD64 Stack and Code Example (2)AMD64 Stack and Code Example (2)

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: call -0x2c <a>main+9: leave main+0xa: ret

Return from main()

Page 74: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 74IA-32 & AMD64

AMD64 Stack and Code Example (2)AMD64 Stack and Code Example (2)

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: call -0x2c <a>main+9: leave main+0xa: ret

Return from main()

BOREDOM

Zzzzz...

.

Page 75: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 75IA-32 & AMD64

AMD64 Stack and Code Example (3)AMD64 Stack and Code Example (3)

Let's try different compiler optionsCompile using gcc -O0 -m64 -msave-args for AMD64Disassemble and single-step main() and a()Observe the stack

Page 76: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 76IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)a: pushq %rbpa+1: movq %rsp,%rbpa+4: movq %rdi,-0x8(%rbp)a+8: subq $0x20,%rspa+0xc: movl %edi,-0x14(%rbp)a+0xf: movl -0x14(%rbp),%edia+0x12: movl $0x0,%eaxa+0x17: call +0x2 <b>a+0x1c: leave a+0x1d: ret

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: movq %rsi,-0x10(%rbp)main+8: movq %rdi,-0x8(%rbp)main+0xc: subq $0x20,%rspmain+0x10: movl %edi,-0x14(%rbp)main+0x13: movq %rsi,-0x20(%rbp)main+0x17: movl -0x14(%rbp),%edimain+0x1a: call -0x6b <a>main+0x1f: leave main+0x20: ret

Page 77: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 77IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffbf8: _start+0x6c

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: movq %rsi,-0x10(%rbp)main+8: movq %rdi,-0x8(%rbp)main+0xc: subq $0x20,%rspmain+0x10: movl %edi,-0x14(%rbp)main+0x13: movq %rsi,-0x20(%rbp)main+0x17: movl -0x14(%rbp),%edimain+0x1a: call -0x6b <a>main+0x1f: leave main+0x20: ret

Initial stateNo instructionsexecutedInherited stackpointer frommain()'s caller

Page 78: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 78IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: movq %rsi,-0x10(%rbp)main+8: movq %rdi,-0x8(%rbp)main+0xc: subq $0x20,%rspmain+0x10: movl %edi,-0x14(%rbp)main+0x13: movq %rsi,-0x20(%rbp)main+0x17: movl -0x14(%rbp),%edimain+0x1a: call -0x6b <a>main+0x1f: leave main+0x20: ret

Save previous framepointer on the stack

Page 79: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 79IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: movq %rsi,-0x10(%rbp)main+8: movq %rdi,-0x8(%rbp)main+0xc: subq $0x20,%rspmain+0x10: movl %edi,-0x14(%rbp)main+0x13: movq %rsi,-0x20(%rbp)main+0x17: movl -0x14(%rbp),%edimain+0x1a: call -0x6b <a>main+0x1f: leave main+0x20: ret

Establish new fixedframe pointer in RBP

It points to where wesaved the previousone

Page 80: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 80IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: movq %rsi,-0x10(%rbp)main+8: movq %rdi,-0x8(%rbp)main+0xc: subq $0x20,%rspmain+0x10: movl %edi,-0x14(%rbp)main+0x13: movq %rsi,-0x20(%rbp)main+0x17: movl -0x14(%rbp),%edimain+0x1a: call -0x6b <a>main+0x1f: leave main+0x20: ret

Save the secondargument on thestack

Using the red zone

Page 81: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 81IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: movq %rsi,-0x10(%rbp)main+8: movq %rdi,-0x8(%rbp)main+0xc: subq $0x20,%rspmain+0x10: movl %edi,-0x14(%rbp)main+0x13: movq %rsi,-0x20(%rbp)main+0x17: movl -0x14(%rbp),%edimain+0x1a: call -0x6b <a>main+0x1f: leave main+0x20: ret

Save the firstargument on thestack

Using the red zone

Page 82: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 82IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffbd0: 0xfffffd7fffdffc000xfffffd7fffdffbd8: _start+0x63 0xfffffd7fffdffbe0: 0xfffffd7fffdffc180xfffffd7fffdffbe8: 10xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: movq %rsi,-0x10(%rbp)main+8: movq %rdi,-0x8(%rbp)main+0xc: subq $0x20,%rspmain+0x10: movl %edi,-0x14(%rbp)main+0x13: movq %rsi,-0x20(%rbp)main+0x17: movl -0x14(%rbp),%edimain+0x1a: call -0x6b <a>main+0x1f: leave main+0x20: ret

Allocate stack spaceWe can see thearguments now

Page 83: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 83IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffbd0: 0xfffffd7fffdffc000xfffffd7fffdffbd8: 0x100400eb3 0xfffffd7fffdffbe0: 0xfffffd7fffdffc180xfffffd7fffdffbe8: 10xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: movq %rsi,-0x10(%rbp)main+8: movq %rdi,-0x8(%rbp)main+0xc: subq $0x20,%rspmain+0x10: movl %edi,-0x14(%rbp)main+0x13: movq %rsi,-0x20(%rbp)main+0x17: movl -0x14(%rbp),%edimain+0x1a: call -0x6b <a>main+0x1f: leave main+0x20: ret

Save away thefirst argumentonce more

Page 84: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 84IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffbd0: 0xfffffd7fffdffc180xfffffd7fffdffbd8: 0x100400eb3 0xfffffd7fffdffbe0: 0xfffffd7fffdffc180xfffffd7fffdffbe8: 10xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: movq %rsi,-0x10(%rbp)main+8: movq %rdi,-0x8(%rbp)main+0xc: subq $0x20,%rspmain+0x10: movl %edi,-0x14(%rbp)main+0x13: movq %rsi,-0x20(%rbp)main+0x17: movl -0x14(%rbp),%edimain+0x1a: call -0x6b <a>main+0x1f: leave main+0x20: ret

Save away thesecond argumentonce more

Page 85: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 85IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffbd0: 0xfffffd7fffdffc180xfffffd7fffdffbd8: 0x100400eb3 0xfffffd7fffdffbe0: 0xfffffd7fffdffc180xfffffd7fffdffbe8: 10xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: movq %rsi,-0x10(%rbp)main+8: movq %rdi,-0x8(%rbp)main+0xc: subq $0x20,%rspmain+0x10: movl %edi,-0x14(%rbp)main+0x13: movq %rsi,-0x20(%rbp)main+0x17: movl -0x14(%rbp),%edimain+0x1a: call -0x6b <a>main+0x1f: leave main+0x20: ret

Just for sure, readthe first argumentback to EDI

Page 86: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 86IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffbc8: main+0x1f0xfffffd7fffdffbd0: 0xfffffd7fffdffc180xfffffd7fffdffbd8: 0x100400eb3 0xfffffd7fffdffbe0: 0xfffffd7fffdffc180xfffffd7fffdffbe8: 10xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: movq %rsi,-0x10(%rbp)main+8: movq %rdi,-0x8(%rbp)main+0xc: subq $0x20,%rspmain+0x10: movl %edi,-0x14(%rbp)main+0x13: movq %rsi,-0x20(%rbp)main+0x17: movl -0x14(%rbp),%edimain+0x1a: call -0x6b <a>main+0x1f: leave main+0x20: ret

Call a()The argument ispassed in RDI

Page 87: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 87IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffbc0: 0xfffffd7fffdffbf00xfffffd7fffdffbc8: main+0x1f0xfffffd7fffdffbd0: 0xfffffd7fffdffc180xfffffd7fffdffbd8: 0x100400eb3 0xfffffd7fffdffbe0: 0xfffffd7fffdffc180xfffffd7fffdffbe8: 10xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Save the previousframe pointer to thestack

a: pushq %rbpa+1: movq %rsp,%rbpa+4: movq %rdi,-0x8(%rbp)a+8: subq $0x20,%rspa+0xc: movl %edi,-0x14(%rbp)a+0xf: movl -0x14(%rbp),%edia+0x12: movl $0x0,%eaxa+0x17: call +0x2 <b>a+0x1c: leave a+0x1d: ret

Page 88: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 88IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffbc0: 0xfffffd7fffdffbf00xfffffd7fffdffbc8: main+0x1f0xfffffd7fffdffbd0: 0xfffffd7fffdffc180xfffffd7fffdffbd8: 0x100400eb3 0xfffffd7fffdffbe0: 0xfffffd7fffdffc180xfffffd7fffdffbe8: 10xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Establish new framepointer in RBP

It points to theaddress where theprevious one is stored

a: pushq %rbpa+1: movq %rsp,%rbpa+4: movq %rdi,-0x8(%rbp)a+8: subq $0x20,%rspa+0xc: movl %edi,-0x14(%rbp)a+0xf: movl -0x14(%rbp),%edia+0x12: movl $0x0,%eaxa+0x17: call +0x2 <b>a+0x1c: leave a+0x1d: ret

Page 89: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 89IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffbc0: 0xfffffd7fffdffbf00xfffffd7fffdffbc8: main+0x1f0xfffffd7fffdffbd0: 0xfffffd7fffdffc180xfffffd7fffdffbd8: 0x100400eb3 0xfffffd7fffdffbe0: 0xfffffd7fffdffc180xfffffd7fffdffbe8: 10xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Save the argumenton the stack

Using the red zone

a: pushq %rbpa+1: movq %rsp,%rbpa+4: movq %rdi,-0x8(%rbp)a+8: subq $0x20,%rspa+0xc: movl %edi,-0x14(%rbp)a+0xf: movl -0x14(%rbp),%edia+0x12: movl $0x0,%eaxa+0x17: call +0x2 <b>a+0x1c: leave a+0x1d: ret

Page 90: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 90IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffba0: 0 0xfffffd7fffdffba8: 00xfffffd7fffdffbb0: 0 0xfffffd7fffdffbb8: 10xfffffd7fffdffbc0: 0xfffffd7fffdffbf00xfffffd7fffdffbc8: main+0x1f0xfffffd7fffdffbd0: 0xfffffd7fffdffc180xfffffd7fffdffbd8: 0x100400eb3 0xfffffd7fffdffbe0: 0xfffffd7fffdffc180xfffffd7fffdffbe8: 10xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Allocate stack spaceWe can see theargument now

a: pushq %rbpa+1: movq %rsp,%rbpa+4: movq %rdi,-0x8(%rbp)a+8: subq $0x20,%rspa+0xc: movl %edi,-0x14(%rbp)a+0xf: movl -0x14(%rbp),%edia+0x12: movl $0x0,%eaxa+0x17: call +0x2 <b>a+0x1c: leave a+0x1d: ret

Page 91: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 91IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffba0: 0 0xfffffd7fffdffba8: 0x1000000000xfffffd7fffdffbb0: 0 0xfffffd7fffdffbb8: 10xfffffd7fffdffbc0: 0xfffffd7fffdffbf00xfffffd7fffdffbc8: main+0x1f0xfffffd7fffdffbd0: 0xfffffd7fffdffc180xfffffd7fffdffbd8: 0x100400eb3 0xfffffd7fffdffbe0: 0xfffffd7fffdffc180xfffffd7fffdffbe8: 10xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Save away the firstargument once again

a: pushq %rbpa+1: movq %rsp,%rbpa+4: movq %rdi,-0x8(%rbp)a+8: subq $0x20,%rspa+0xc: movl %edi,-0x14(%rbp)a+0xf: movl -0x14(%rbp),%edia+0x12: movl $0x0,%eaxa+0x17: call +0x2 <b>a+0x1c: leave a+0x1d: ret

Page 92: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 92IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffba0: 0 0xfffffd7fffdffba8: 0x1000000000xfffffd7fffdffbb0: 0 0xfffffd7fffdffbb8: 10xfffffd7fffdffbc0: 0xfffffd7fffdffbf00xfffffd7fffdffbc8: main+0x1f0xfffffd7fffdffbd0: 0xfffffd7fffdffc180xfffffd7fffdffbd8: 0x100400eb3 0xfffffd7fffdffbe0: 0xfffffd7fffdffc180xfffffd7fffdffbe8: 10xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Just for sure, readthe first argumentback to EDI

a: pushq %rbpa+1: movq %rsp,%rbpa+4: movq %rdi,-0x8(%rbp)a+8: subq $0x20,%rspa+0xc: movl %edi,-0x14(%rbp)a+0xf: movl -0x14(%rbp),%edia+0x12: movl $0x0,%eaxa+0x17: call +0x2 <b>a+0x1c: leave a+0x1d: ret

Page 93: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 93IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffba0: 0 0xfffffd7fffdffba8: 0x1000000000xfffffd7fffdffbb0: 0 0xfffffd7fffdffbb8: 10xfffffd7fffdffbc0: 0xfffffd7fffdffbf00xfffffd7fffdffbc8: main+0x1f0xfffffd7fffdffbd0: 0xfffffd7fffdffc180xfffffd7fffdffbd8: 0x100400eb3 0xfffffd7fffdffbe0: 0xfffffd7fffdffc180xfffffd7fffdffbe8: 10xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Zero EAXZero-extend to upper32bits of RAX

Clears the whole RAXNot needed

a: pushq %rbpa+1: movq %rsp,%rbpa+4: movq %rdi,-0x8(%rbp)a+8: subq $0x20,%rspa+0xc: movl %edi,-0x14(%rbp)a+0xf: movl -0x14(%rbp),%edia+0x12: movl $0x0,%eaxa+0x17: call +0x2 <b>a+0x1c: leave a+0x1d: ret

Page 94: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 94IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffb98: a+0x1c0xfffffd7fffdffba0: 0 0xfffffd7fffdffba8: 0x1000000000xfffffd7fffdffbb0: 0 0xfffffd7fffdffbb8: 10xfffffd7fffdffbc0: 0xfffffd7fffdffbf00xfffffd7fffdffbc8: main+0x1f0xfffffd7fffdffbd0: 0xfffffd7fffdffc180xfffffd7fffdffbd8: 0x100400eb3 0xfffffd7fffdffbe0: 0xfffffd7fffdffc180xfffffd7fffdffbe8: 10xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Call b()The argument is stillin RDI

a: pushq %rbpa+1: movq %rsp,%rbpa+4: movq %rdi,-0x8(%rbp)a+8: subq $0x20,%rspa+0xc: movl %edi,-0x14(%rbp)a+0xf: movl -0x14(%rbp),%edia+0x12: movl $0x0,%eaxa+0x17: call +0x2 <b>a+0x1c: leave a+0x1d: ret

Page 95: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 95IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffba0: 0 0xfffffd7fffdffba8: 0x1000000000xfffffd7fffdffbb0: 0 0xfffffd7fffdffbb8: 10xfffffd7fffdffbc0: 0xfffffd7fffdffbf00xfffffd7fffdffbc8: main+0x1f0xfffffd7fffdffbd0: 0xfffffd7fffdffc180xfffffd7fffdffbd8: 0x100400eb3 0xfffffd7fffdffbe0: 0xfffffd7fffdffc180xfffffd7fffdffbe8: 10xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Step through andreturn from b()

b()'s return value isin RAX

a: pushq %rbpa+1: movq %rsp,%rbpa+4: movq %rdi,-0x8(%rbp)a+8: subq $0x20,%rspa+0xc: movl %edi,-0x14(%rbp)a+0xf: movl -0x14(%rbp),%edia+0x12: movl $0x0,%eaxa+0x17: call +0x2 <b>a+0x1c: leave a+0x1d: ret

Page 96: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 96IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffbc8: main+0x1f0xfffffd7fffdffbd0: 0xfffffd7fffdffc180xfffffd7fffdffbd8: 0x100400eb3 0xfffffd7fffdffbe0: 0xfffffd7fffdffc180xfffffd7fffdffbe8: 10xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Destroy a()'s stackframe

a: pushq %rbpa+1: movq %rsp,%rbpa+4: movq %rdi,-0x8(%rbp)a+8: subq $0x20,%rspa+0xc: movl %edi,-0x14(%rbp)a+0xf: movl -0x14(%rbp),%edia+0x12: movl $0x0,%eaxa+0x17: call +0x2 <b>a+0x1c: leave a+0x1d: ret

Page 97: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 97IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffbd0: 0xfffffd7fffdffc180xfffffd7fffdffbd8: 0x100400eb3 0xfffffd7fffdffbe0: 0xfffffd7fffdffc180xfffffd7fffdffbe8: 10xfffffd7fffdffbf0: 0xfffffd7fffdffc000xfffffd7fffdffbf8: _start+0x6c

Return back tomain()

Return value is againin RAX

a: pushq %rbpa+1: movq %rsp,%rbpa+4: movq %rdi,-0x8(%rbp)a+8: subq $0x20,%rspa+0xc: movl %edi,-0x14(%rbp)a+0xf: movl -0x14(%rbp),%edia+0x12: movl $0x0,%eaxa+0x17: call +0x2 <b>a+0x1c: leave a+0x1d: ret

Page 98: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 98IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

0xfffffd7fffdffbf8: _start+0x6c

Destroy main()'sstack frame

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: movq %rsi,-0x10(%rbp)main+8: movq %rdi,-0x8(%rbp)main+0xc: subq $0x20,%rspmain+0x10: movl %edi,-0x14(%rbp)main+0x13: movq %rsi,-0x20(%rbp)main+0x17: movl -0x14(%rbp),%edimain+0x1a: call -0x6b <a>main+0x1f: leave main+0x20: ret

Page 99: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 99IA-32 & AMD64

AMD64 Stack and Code Example (4)AMD64 Stack and Code Example (4)

Return from main()

main: pushq %rbpmain+1: movq %rsp,%rbpmain+4: movq %rsi,-0x10(%rbp)main+8: movq %rdi,-0x8(%rbp)main+0xc: subq $0x20,%rspmain+0x10: movl %edi,-0x14(%rbp)main+0x13: movq %rsi,-0x20(%rbp)main+0x17: movl -0x14(%rbp),%edimain+0x1a: call -0x6b <a>main+0x1f: leave main+0x20: ret

Page 100: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 100IA-32 & AMD64

Compiling Without Frame PointerCompiling Without Frame Pointer

The frame pointer is actually not necessaryAddressing variables by RSP/ESP is sufficient in many functions (unless e.g. alloca() is used)

The compilers are smart enough to track the offsetsThe use of EBP/RBP is merely a convention

Extra general purpose register can be handySo is saving one or two instructions on entry/exit

Downside: Obtaining stack traces and debugging is more difficult – no simple linked list traversal

Page 101: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 101IA-32 & AMD64

AMD64 Stack and Code Example (5)AMD64 Stack and Code Example (5)

The compiler can omit frame pointersActually the default behavior in GCC on AMD64 above -O0

And on IA-32 since GCC 4.6Unless -fno-omit-frame-pointer is given

Example: Compile using gcc -m64 -fomit-frame-pointer

Using GCC 4.8.3 on Linux (more differences to previous examples)

Note: Using alloca() does result in frame pointer to be employed Disassemble and single-step main() and a()Observe the stack

Page 102: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 102IA-32 & AMD64

AMD64 Stack and Code Example (6)AMD64 Stack and Code Example (6)

main+0: sub $0x10,%rspmain+4: mov %edi,0xc(%rsp)main+8: mov %rsi,(%rsp)main+12: mov 0xc(%rsp),%eaxmain+16: mov %eax,%edimain+18: callq 0x40056e <a>main+23: add $0x10,%rspmain+27: retq

a+0: sub $0x8,%rspa+4: mov %edi,0x4(%rsp)a+8: mov 0x4(%rsp),%eaxa+12: mov %eax,%edia+14: callq 0x400556 <b>a+19: add $0x8,%rspa+23: retq

Page 103: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 103IA-32 & AMD64

AMD64 Stack and Code Example (6)AMD64 Stack and Code Example (6)

0x7fffffffd6d8: start_main+245

Initial stateNo instructionsexecutedInherited stackpointer frommain()'s caller

main+0: sub $0x10,%rspmain+4: mov %edi,0xc(%rsp)main+8: mov %rsi,(%rsp)main+12: mov 0xc(%rsp),%eaxmain+16: mov %eax,%edimain+18: callq 0x40056e <a>main+23: add $0x10,%rspmain+27: retq

Page 104: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 104IA-32 & AMD64

AMD64 Stack and Code Example (6)AMD64 Stack and Code Example (6)

0x7fffffffd6c8: 0x00000000000000000x7fffffffd6d0: 0x00000000000000000x7fffffffd6d8: start_main+245

Allocate stack spaceOnly zeros so far

main+0: sub $0x10,%rspmain+4: mov %edi,0xc(%rsp)main+8: mov %rsi,(%rsp)main+12: mov 0xc(%rsp),%eaxmain+16: mov %eax,%edimain+18: callq 0x40056e <a>main+23: add $0x10,%rspmain+27: retq

Page 105: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 105IA-32 & AMD64

AMD64 Stack and Code Example (6)AMD64 Stack and Code Example (6)

0x7fffffffd6c8: 0x00000000000000000x7fffffffd6d0: 0x00000001000000000x7fffffffd6d8: start_main+245

Save the firstargument on thestack

Not 8-bytes aligned

main+0: sub $0x10,%rspmain+4: mov %edi,0xc(%rsp)main+8: mov %rsi,(%rsp)main+12: mov 0xc(%rsp),%eaxmain+16: mov %eax,%edimain+18: callq 0x40056e <a>main+23: add $0x10,%rspmain+27: retq

Page 106: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 106IA-32 & AMD64

AMD64 Stack and Code Example (6)AMD64 Stack and Code Example (6)

0x7fffffffd6c8: 0x00007fffffffd7b80x7fffffffd6d0: 0x00000001000000000x7fffffffd6d8: start_main+245

Save the secondargument on thestack

main+0: sub $0x10,%rspmain+4: mov %edi,0xc(%rsp)main+8: mov %rsi,(%rsp)main+12: mov 0xc(%rsp),%eaxmain+16: mov %eax,%edimain+18: callq 0x40056e <a>main+23: add $0x10,%rspmain+27: retq

Page 107: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 107IA-32 & AMD64

AMD64 Stack and Code Example (6)AMD64 Stack and Code Example (6)

0x7fffffffd6c8: 0x00007fffffffd7b80x7fffffffd6d0: 0x00000001000000000x7fffffffd6d8: start_main+245

Read the saved firstargument to EAX

Because we can

main+0: sub $0x10,%rspmain+4: mov %edi,0xc(%rsp)main+8: mov %rsi,(%rsp)main+12: mov 0xc(%rsp),%eaxmain+16: mov %eax,%edimain+18: callq 0x40056e <a>main+23: add $0x10,%rspmain+27: retq

Page 108: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 108IA-32 & AMD64

AMD64 Stack and Code Example (6)AMD64 Stack and Code Example (6)

0x7fffffffd6c8: 0x00007fffffffd7b80x7fffffffd6d0: 0x00000001000000000x7fffffffd6d8: start_main+245

Put the firstargument for a()in EDI

It's already there ...

main+0: sub $0x10,%rspmain+4: mov %edi,0xc(%rsp)main+8: mov %rsi,(%rsp)main+12: mov 0xc(%rsp),%eaxmain+16: mov %eax,%edimain+18: callq 0x40056e <a>main+23: add $0x10,%rspmain+27: retq

Page 109: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 109IA-32 & AMD64

AMD64 Stack and Code Example (6)AMD64 Stack and Code Example (6)

0x7fffffffd6c0: main+230x7fffffffd6c8: 0x00007fffffffd7b80x7fffffffd6d0: 0x00000001000000000x7fffffffd6d8: start_main+245

Call a()The argument ispassed in RDI

main+0: sub $0x10,%rspmain+4: mov %edi,0xc(%rsp)main+8: mov %rsi,(%rsp)main+12: mov 0xc(%rsp),%eaxmain+16: mov %eax,%edimain+18: callq 0x40056e <a>main+23: add $0x10,%rspmain+27: retq

Page 110: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 110IA-32 & AMD64

AMD64 Stack and Code Example (6)AMD64 Stack and Code Example (6)

0x7fffffffd6b8: _start+0 (raw: 0x0000000000400440)0x7fffffffd6c0: main+230x7fffffffd6c8: 0x00007fffffffd7b80x7fffffffd6d0: 0x00000001000000000x7fffffffd6d8: start_main+245

Allocate stack spaceNot zeroed out thistime

a+0: sub $0x8,%rspa+4: mov %edi,0x4(%rsp)a+8: mov 0x4(%rsp),%eaxa+12: mov %eax,%edia+14: callq 0x400556 <b>a+19: add $0x8,%rspa+23: retq

Page 111: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 111IA-32 & AMD64

AMD64 Stack and Code Example (6)AMD64 Stack and Code Example (6)

0x7fffffffd6b8: 0x00000001004004400x7fffffffd6c0: main+230x7fffffffd6c8: 0x00007fffffffd7b80x7fffffffd6d0: 0x00000001000000000x7fffffffd6d8: start_main+245

Save the firstargument on stack

Again, not 8B alignedThe rest of oldaddress remains

a+0: sub $0x8,%rspa+4: mov %edi,0x4(%rsp)a+8: mov 0x4(%rsp),%eaxa+12: mov %eax,%edia+14: callq 0x400556 <b>a+19: add $0x8,%rspa+23: retq

Page 112: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 112IA-32 & AMD64

AMD64 Stack and Code Example (6)AMD64 Stack and Code Example (6)

0x7fffffffd6b8: 0x00000001004004400x7fffffffd6c0: main+230x7fffffffd6c8: 0x00007fffffffd7b80x7fffffffd6d0: 0x00000001000000000x7fffffffd6d8: start_main+245

Fast-forward ... andreturn from b()

Nothing new there

a+0: sub $0x8,%rspa+4: mov %edi,0x4(%rsp)a+8: mov 0x4(%rsp),%eaxa+12: mov %eax,%edia+14: callq 0x400556 <b>a+19: add $0x8,%rspa+23: retq

Page 113: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 113IA-32 & AMD64

AMD64 Stack and Code Example (6)AMD64 Stack and Code Example (6)

0x7fffffffd6c0: main+230x7fffffffd6c8: 0x00007fffffffd7b80x7fffffffd6d0: 0x00000001000000000x7fffffffd6d8: start_main+245

Destroy a()'s stackframe

No RBP handlingnecessary

a+0: sub $0x8,%rspa+4: mov %edi,0x4(%rsp)a+8: mov 0x4(%rsp),%eaxa+12: mov %eax,%edia+14: callq 0x400556 <b>a+19: add $0x8,%rspa+23: retq

Page 114: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 114IA-32 & AMD64

AMD64 Stack and Code Example (6)AMD64 Stack and Code Example (6)

0x7fffffffd6c8: 0x00007fffffffd7b80x7fffffffd6d0: 0x00000001000000000x7fffffffd6d8: start_main+245

Return from a()Return value in RAXThen the same ADDand RETQ in main()

a+0: sub $0x8,%rspa+4: mov %edi,0x4(%rsp)a+8: mov 0x4(%rsp),%eaxa+12: mov %eax,%edia+14: callq 0x400556 <b>a+19: add $0x8,%rspa+23: retq

Page 115: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 115IA-32 & AMD64

IA-32 ABI Cheat SheetIA-32 ABI Cheat Sheet

EAX return valueEBXECXEDXESIEDIEBP frame pointerESP stack pointer

non­volatile registersvolatile registers

Page 116: IA-32 & AMD64 - D3S – Department of Distributed and …d3s.mff.cuni.cz/.../slides/02-ia32-amd64.pdf · 2016-03-02 · Crash Dump Analysis 2015/2016 IA-32 & AMD64 7 Intel Manuals

Crash Dump Analysis 2015/2016 116IA-32 & AMD64

AMD64 ABI Cheat SheetAMD64 ABI Cheat Sheet

RAX return valueRBXRCXRDXRSIRDIRBP frame pointerRSP stack pointerR8R9R10R11R12R13R14R15

non­volatile registersvolatile registers

4th argument3rd argument2nd argument1st argument

5th argument6th argument