ibm presentation material component time constants and its ... · cv v fkhz π = ∆ ⋅⋅ − =...

IBM Presentation Material

Component Time Constantsand its Effect on Bandwidth

ByThomas VictorinZaki Moussaoui

IBM Presentation MaterialIBM Presentation Material

Component Time ConstantsComponent Time Constantsand its Effect on Bandwidthand its Effect on Bandwidth

ByByThomas VictorinThomas VictorinZaki Moussaoui Zaki Moussaoui

Agenda Agenda

Why the Need for High Bandwidth?

Techniques to Achieve High Bandwidth

Time Constant Blocks

Design Example and Experimental Results

Conclusion

Why the Need for High Bandwidth?

•Core Voltage is decreasing while Power is increasing. The output voltage is decreasing Smaller duty cycle

Power is increasing Current is increasing

Aggressive Microprocessor Power Management Higher

Loadline / Regulation Tighter transient limits

⇒⇒⇒ d i

d t⇒

Achieving Higher BandwidthAchieving Higher Bandwidth

Techniques to Achieve Higher BandwidthIncreasing the switching frequencyUsing low time constant capacitorsUsing high slew rate inductorsDecreasing the system time delays Increasing the compensator gain

Four Main Time Constant Blocks

Four Main Time Constant BlocksOutput Capacitor with ESRInductor Slew RateDelays

MOSFET Gate Drive and Pulse Width ModulationControl Loop Compensation

Error Amplifier Gain-Bandwidth Limitation

12 v inputLoad

C

ESR

L

RC time constant

Drivers

Driver/ mosfet responsedelay

maximum duty cycle limitgain-bandwidth limitation

Controller

Inductor slew rate

Equ2

0

1( ) ( ) ( )t

out c co

V t ESR i t i t dtC

= ⋅ + ∫

Solving for the peak voltage transient resulting from current step we get:

Where:

is the maximum step load current of the system

12peak o

c o

V If Cπ

∆ = ∆⋅ ⋅ ⋅

oI∆

Equ3

oI∆

Effect of the output capacitor time constant:

The capacitor current during a transient could be shown with the following equations:

2( ) (1 )ctfc oI t I e π−= ∆ − Equ1

_

_

1256.8

c cto

c ct

fESR C

f khzπ

=⋅ ⋅

=

•Critical frequency due to capacitor time constant•Each type of cap has an associated , the system will respond based on the effective time constant of the system.

cf

For: C= 560uF,ESR=5m

Analytical Study of Output Capacitor Time Analytical Study of Output Capacitor Time ConstantConstant

Analytical Study of Inductor Time ConstantsAnalytical Study of Inductor Time Constants

Effect of the output inductor time constant:The inductor slew rate limits the effective bandwidth as followed:

•Critical frequency at load releaseSo for load release it is:

odi Vdt L

= _ ( )2

oc re

o

VfI Lπ

=⋅∆ ⋅

Equ5

For load application it is:

lim( )in odi V V Ddt L

−= ⋅

Equ6

_ lim( )2

in oc ap

o

V Vf DI Lπ−

= ⋅⋅ ∆ ⋅

•Critical frequency at load applied

Due to low output voltage the most severe limitation is imposed at load release.

Driver, MOSFET and Modulation delayDriver, MOSFET and Modulation delay

Effect of the delay of the driver/ MOSFET plus modulation technique:

Phase1 PWM

Phase2 PWM

Time delaybefore any

effect

Load Step

Delay

o delaydelay

o

I tV

C∆ ⋅

≈

Delay is the total delay including propagation delay of driver, and turn on delay of the MOSFET.

Worst-case scenario delay is if the transient occurs right after the pulse was given for trailing edge modulation.

Limitation imposed by the gainLimitation imposed by the gain--bandwidth bandwidth of the controller amplifierof the controller amplifier•Typical PWM Error Amplifiers today: Gain-BW Product = 15-20MHz

•max achievable converter BW ~ 200kHz

Maximum output voltage as function of critical Maximum output voltage as function of critical frequencyfrequency

_ _

_ _ _

_ __

1 min( , )2

12

o delay c c ct c reo c

tr peak o delay c ct c c re

o delay c re c c cto c re

I V f f fC f

V ESR I V f f f

I V f f fC f

π

π

∆ ≤ ⋅ ⋅= ⋅∆ ≤ ≤

∆ ≤ ≤

⋅ ⋅

+ for

+ for

+ for

o delaydelay

o

I tV

C∆ ⋅

≈

_1

2c cto

fESR Cπ

=⋅ ⋅

Capacitors critical frequencyCapacitors critical frequency Inductor critical frequencyInductor critical frequency

_ ( )2

oc re

o

VfI Lπ

=⋅∆ ⋅

fc is the closed loop BW

Effects of ESL are ignored in these equations.Effects of ESL are ignored in these equations.

DelayDelay

Design ExampleDesign Example

Component considerations to remove limitations

• Low time constant capacitors• High slew rate inductors• Higher switching frequency• Controller with high compensator gain • Minimize delay time

Example:

Vin=12, Vout=1.2, =100A andoI∆ V 125mvTr_peak

=

Assume: 560uF at 5mΩ

_1 60

2c ctf KhzESR Cπ

= ≈⋅ ⋅

•System bandwidth is limited to ~60kHz

Design ExampleDesign Example

Component considerations to remove limitations

Example:

Vin=12, Vout=1.2, =100A andoI∆ V 125mvTr_peak

=

Assume: 22uF at 3mΩ

•System bandwidth is limited to ~ 2.4MHz_

_ 6

_

12

12 .003 22 102.4

c ct

c ct

c ct

fESR C

f

f Mhz

π

π −

=⋅ ⋅

=⋅ ⋅

=

Design ExampleDesign ExampleExample:Vin=12, Vout=1.2, =100A andoI∆ V 125mv, fc= 130khz

Tr_peak=

L needed in order to take advantage of the entire controller bandwidth and not have the slew rate of the inductor limit our system bandwidth is:

6

8

21.2

2 130 10 1001.469 10

15

oequ

c o

equ

equ

equ

VLf I

L

L

L nH

π

π−

=∆

=

=

=

For a 4 phase system, 100nH at 0DC is used that should give a 60nH to 70nH at 25A.

Board Level SummaryBoard Level Summary

Design Comments:

Compensation Loop remained fixed during testing and was not changed for different caps and inductors used.

The following components and parameters remained fixed:

ISL6561 Controller(2) IRF6604 Upper FETs(2) IRF6691 Lower FETs4-Phase SolutionFSW= 700khzTransient load= 1-100A, di/dt= 500A/usDroop= 20mV

Experimental ResultsExperimental Results

_

12 ( )

13.5

c oo tr peak delay

c

f IC V V

f khz

π= ∆

⋅ ⋅ −

=

Large signal measured effective critical frequencyCalculated critical frequency

_

_

1256.8

c cto

c ct

fESR C

f khzπ

=⋅ ⋅

=

Vtr_peak = 210mv

Capacitor Limited Design

Small signal measured

10x560uF, ESR=5m and 100nH Inductors

Fc = 65khz

•We are primarily looking at the cutoff and not the phase margin.



Vtr_peak = 175mv

Inductor Limited Design


_

12 ( )

41.3

c oo tr peak delay

c

f IC V V

f khz

π= ∆

⋅ ⋅ −

=

_

_

( )2

127

oc re

o eq

c re

VfI L

f khz

π=

⋅∆ ⋅

=


Fc = 135khz



Vtr_peak = 275mv



_

12 ( )

10.3

c oo tr peak delay

c

f IC V V

f khz

π= ∆

⋅ ⋅ −

=

_

_

( )2

32

oc re

o eq

c re

VfI L

f khz

π=

⋅∆ ⋅

=


Fc = 34khz


Calculated critical frequencyLarge signal measured

effective critical frequency

Vtr_peak = 275mv



_

12 ( )

26.3

c oo tr peak delay

c

f IC V V

f khz

π= ∆

⋅ ⋅ −

=

_

_

( )2

32

oc re

o eq

c re

VfI L

f khz

π=

⋅∆ ⋅

=

10x220uF,ESR=5m and 400nH Inductors

Fc = 44khz


_

12 ( )

124

c oo tr peak delay

c

f IC V V

f khz

π= ∆

⋅ ⋅ −

=

Large signal measured effective critical frequencySmall signal measured

_

_

( )2

127

oc re

o eq

c re

VfI L

f khz

π=

⋅∆ ⋅

=

Calculated critical frequency

Vtr_peak = 44mv


145x22uF,ESR=3m and 100nH Inductors

Fc = 198khz

ConclusionConclusion

••Small signal bandwidth is not a true Small signal bandwidth is not a true representation of the output voltage transient representation of the output voltage transient response.response.••Output voltage transient response is based on Output voltage transient response is based on the large signal response bandwidth.the large signal response bandwidth.••Large signal response bandwidth is dictated by Large signal response bandwidth is dictated by the slew rate of the inductor, time constant of the the slew rate of the inductor, time constant of the capacitors and any delay in the control system.capacitors and any delay in the control system.••Component selection is critical to designing a Component selection is critical to designing a high performance power supply.high performance power supply.

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