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Page 1: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

IC Manufacturing and Yield

ECE/ChE 4752: Microelectronics ECE/ChE 4752: Microelectronics Processing LaboratoryProcessing Laboratory

Gary S. May

April 15, 2004

Page 2: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Outline

IntroductionIntroduction Statistical Process ControlStatistical Process Control Statistical Experimental DesignStatistical Experimental Design YieldYield

Page 3: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Motivation IC manufacturing processes must be stable, IC manufacturing processes must be stable,

repeatable, and of high quality to yield repeatable, and of high quality to yield products with acceptable performance. products with acceptable performance.

All persons involved in manufacturing an All persons involved in manufacturing an IC (including operators, engineers, and IC (including operators, engineers, and management) must continuously seek to management) must continuously seek to improve manufacturing process output and improve manufacturing process output and reduce variability. reduce variability.

Variability reduction is accomplished by Variability reduction is accomplished by strict process control. strict process control.

Page 4: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Production Efficiency

Determined by actions both on and off the manufacturing floor

Design for manufacturability (DFM): intended to improve production efficiency

HighVolumeManufacturing

Process Design

Circuit Design

OFF ON

Page 5: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Variability

The most significant challenge in IC production Types of variability:

human error equipment failure material non-uniformity substrate inhomogeneity lithography spots

Page 6: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Deformations Variability leads to => deformations Types of deformations

1) Geometric: lateral (across wafer) vertical (into substrate) spot defects crystal defects (vacancies, interstitials)

2) Electrical: local (per die) global (per wafer)

Page 7: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Outline

IntroductionIntroduction Statistical Process ControlStatistical Process Control Statistical Experimental DesignStatistical Experimental Design YieldYield

Page 8: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Statistical Process Control

SPC = a powerful collection of problem SPC = a powerful collection of problem solving tools to achieve process stability solving tools to achieve process stability and reduce variabilityand reduce variability

Primary tool = the Primary tool = the control chart;control chart; developed developed by Dr. Walter Shewhart of Bell by Dr. Walter Shewhart of Bell Laboratories in the 1920s.Laboratories in the 1920s.

Page 9: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Control Charts

Quality characteristic Quality characteristic measured from a measured from a sample versus sample sample versus sample number or timenumber or time

Control limits Control limits typically set at typically set at 3 3 from center line (from center line ( = = standard deviation)standard deviation)

Page 10: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Control Chart for Attributes

Some quality characteristics cannot be easily Some quality characteristics cannot be easily represented numerically (e.g., whether or not a represented numerically (e.g., whether or not a wire bond is defective). wire bond is defective).

In this case, the characteristic is classified as either In this case, the characteristic is classified as either "conforming" or "non- conforming", and there is "conforming" or "non- conforming", and there is no numerical value associated with the quality of no numerical value associated with the quality of the bond. the bond.

Quality characteristics of this type are referred to Quality characteristics of this type are referred to as attributes. as attributes.

Page 11: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Defect Chart Also called “c-chart”Also called “c-chart” Control chart for total number of defects Control chart for total number of defects Assumes that the presence of defects in samples of Assumes that the presence of defects in samples of

constant size is modeled by Poisson distribution, constant size is modeled by Poisson distribution, in which the probability of a defect occurring isin which the probability of a defect occurring is

where where xx is the number of defects and is the number of defects and cc > 0 > 0

!)(

x

cexP

xc

Page 12: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Control Limits for C-Chart

C-chart with C-chart with ±± 3 3 control limits is given by control limits is given by

Centerline = Centerline = cc

(assuming (assuming cc is known) is known)

ccUCL 3

ccLCL 3

Page 13: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Control Limits for C-Chart

If If cc is unknown, it can be estimated from the is unknown, it can be estimated from the average number of defects in a sample. average number of defects in a sample.

In this case, the control chart becomes In this case, the control chart becomes

Centerline = Centerline =

ccUCL 3

ccLCL 3

c

Page 14: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

ExampleSuppose the inspection of 25 silicon wafers yields 37 Suppose the inspection of 25 silicon wafers yields 37

defects. Set up a c-chart.defects. Set up a c-chart.

SolutionSolution::Estimate Estimate cc using using

This is the center line. The UCL and LCL can be found as This is the center line. The UCL and LCL can be found as followsfollows

Since –2.17 < 0, we set the LCL = 0.Since –2.17 < 0, we set the LCL = 0.

48.125

37c

13.53 ccUCL

17.23 ccLCL

Page 15: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Defect Density Chart

Also called a “u-chart”Also called a “u-chart” Control chart for the Control chart for the averageaverage number of defects number of defects

over a sample size of over a sample size of nn products. products. If there are If there are cc total defects among the total defects among the nn samples, samples,

the average number of defects per sample is the average number of defects per sample is

n

cu

Page 16: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Control Limits for U-Chart

U-chart with ± 3U-chart with ± 3 control limits is given by: control limits is given by:

Center line =Center line =

where where uu is the average number of defects over is the average number of defects over mm groups of groups of size size nn

nuuUCL /3

nuuLCL /3

u

Page 17: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

ExampleSuppose an IC manufacturer wants to establish a defect density chart. Suppose an IC manufacturer wants to establish a defect density chart.

Twenty different samples of size Twenty different samples of size nn = 5 wafers are inspected, and a = 5 wafers are inspected, and a total of 183 defects are found. Set up the u-chart total of 183 defects are found. Set up the u-chart ..

SolutionSolution::

Estimate Estimate uu using using

This is the center line. The UCL and LCL can be found as followsThis is the center line. The UCL and LCL can be found as follows

83.1)5)(20(

183

mn

c

m

uu

64.3/3 nuuUCL

02.0/3 nuuLCL

Page 18: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Control Charts for Variables

In many cases, quality characteristics are In many cases, quality characteristics are expressed as specific numerical expressed as specific numerical measurements. measurements.

ExampleExample: the thickness of a film. : the thickness of a film. In these cases, control charts for variables In these cases, control charts for variables

can provide more information regarding can provide more information regarding manufacturing process performance.manufacturing process performance.

Page 19: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Control of Mean and Variance

Control of the mean is achieved using an -Control of the mean is achieved using an -chart:chart:

Variance can be monitored using the s-chart, Variance can be monitored using the s-chart, where: where:

x

n

ii

n xnn

xxxx

1

21 1

n

ii xx

ns

1

2)(1

1

Page 20: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Control Limits for Mean

nxUCL /3 2

xCenter

nxLCL /3 2

where the grand average is:

m

xxxx m

21

Page 21: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Control Limits for Variance24

4

13 cc

ssUCL

sCenter

where: and c4 is a constant

m

iis

ms

1

1

24

4

13 cc

ssLCL

Page 22: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Modified Control Limits for Mean

The limits for the -chart can also be written The limits for the -chart can also be written as:as:

x

nc

sxUCL

4

3

nc

sxLCL

4

3

Page 23: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Example

Suppose and s-charts are to be established to control Suppose and s-charts are to be established to control linewidth in a lithography process, and 25 samples of size linewidth in a lithography process, and 25 samples of size nn = 5 are measured. The grand average for the 125 lines is = 5 are measured. The grand average for the 125 lines is 4.01 4.01 m. If = 0.09 m. If = 0.09 m, what are the control limits for m, what are the control limits for the charts?the charts?

SolutionSolution: :

For the -chart:For the -chart:

s

x

x mnc

sxUCL 14.4

3

4

mnc

sxLCL 88.3

3

4

Page 24: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Example

SolutionSolution (cont.): (cont.):

For the s-chart:For the s-chart:

mcc

ssUCL 19.013 2

44

013 24

4

cc

ssLCL

Page 25: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Outline

IntroductionIntroduction Statistical Process ControlStatistical Process Control Statistical Experimental DesignStatistical Experimental Design YieldYield

Page 26: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Background

Experiments allow us to determine the effects of several Experiments allow us to determine the effects of several variables on a given process. variables on a given process.

A A designed experimentdesigned experiment is a test or series of tests which is a test or series of tests which involve purposeful changes to variables to observe the involve purposeful changes to variables to observe the effect of the changes on the process. effect of the changes on the process.

Statistical experimental designStatistical experimental design is an efficient approach for is an efficient approach for systematically varying these process variables and systematically varying these process variables and determining their impact on process quality. determining their impact on process quality.

Application of this technique can lead to improved yield, Application of this technique can lead to improved yield, reduced variability, reduced development time, and reduced variability, reduced development time, and reduced cost. reduced cost.

Page 27: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Comparing Distributions

Consider the following Consider the following yield data (in %):yield data (in %):

Is Method B better Is Method B better than Method A?than Method A?

WaferWafer Method AMethod A Method B Method B

11 89.789.7 84.784.7

22 81.481.4 86.186.1

33 84.584.5 83.283.2

44 84.884.8 91.991.9

55 87.387.3 86.386.3

66 79.779.7 79.379.3

77 85.185.1 86.286.2

88 81.781.7 89.189.1

99 83.783.7 83.783.7

1010 84.584.5 88.588.5

AvgAvg 84.2484.24 85.5485.54

Page 28: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Hypothesis Testing

We test the hypothesis that B is better than A using the We test the hypothesis that B is better than A using the null hypothesisnull hypothesis::

HH00: : AA = = BB

Test statistic: Test statistic:

where: are sample means of the yields, where: are sample means of the yields, nnii are are number of trials for each sample, and number of trials for each sample, and

BAp

BA

nns

yyt

11

)(0

iy

2

)1()1( 222

BA

BBAAp nn

snsns

Page 29: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Results Calculations: sCalculations: sAA = 2.90 and s = 2.90 and sBB = 3.65, s = 3.65, spp = 3.30, and t = 3.30, and t00 = =

0.88. 0.88. Use Appendix K to determine the probability of computing Use Appendix K to determine the probability of computing

a given t-statistic with a certain number of degrees of a given t-statistic with a certain number of degrees of freedom. freedom.

We find that the likelihood of computing a t-statistic with We find that the likelihood of computing a t-statistic with nnAA + n + nBB - 2 = 18 degrees of freedom = 0.88 is 0.195. - 2 = 18 degrees of freedom = 0.88 is 0.195.

This means that there is only an 19.5% chance that the This means that there is only an 19.5% chance that the observed difference between the mean yields is due to pure observed difference between the mean yields is due to pure chance. chance.

We can be 80.5% confident that Method B is really We can be 80.5% confident that Method B is really superior to Method A. superior to Method A.

Page 30: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Analysis of Variance

The previous example shows how to use The previous example shows how to use hypothesis testing to compare 2 distributions. hypothesis testing to compare 2 distributions.

It’s often important in IC manufacturing to It’s often important in IC manufacturing to compare several distributions. compare several distributions.

We might also be interested in determining which We might also be interested in determining which process conditions in particular have a significant process conditions in particular have a significant impact on process quality. impact on process quality.

Analysis of varianceAnalysis of variance (ANOVA) is a powerful (ANOVA) is a powerful technique for accomplishing these objectives. technique for accomplishing these objectives.

Page 31: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

ANOVA Example

Defect densities (cmDefect densities (cm-2-2) ) for 4 process recipes:for 4 process recipes:

kk = 4 treatments = 4 treatments nn11 = 4, n = 4, n22 = n = n33 = 6, n = 6, n44 = =

8; N = 248; N = 24 Treatment means:Treatment means:

Grand average:Grand average:

11 22 33 44

6262 6363 6868 5656

6060 6767 6666 6262

6363 7171 7171 6060

5959 6464 6767 6161

6565 6868 6363

6666 6868 6464

6363

5959

61686661 4321 yyyy

64y

Page 32: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Sums of Squares

Within treatments:Within treatments:

Between treatments:Between treatments:

Total:Total:

k

tttT yynS

1

2)(

k

t

n

itiD

t

yyS1 1

2)(

k

t

n

ittiR

t

yyS1 1

2)(

Page 33: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Degrees of Freedom

Within treatments:Within treatments:

Between treatments:Between treatments:

Total:Total:

1kT

1ND

kNR

Page 34: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Mean Squares

Within treatments:Within treatments:

Between treatments:Between treatments:

Total:Total:

TTT Ss /2

DDD Ss /2

RRR Ss /2

Page 35: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

ANOVA Table for Defect Density

SourceSource Sum of Sum of SquaresSquares

Degrees of Degrees of FreedomFreedom

Mean Mean SquareSquare

F-ratioF-ratio

Between Between TreatmentTreatment

ss

SSTT = 228 = 228 TT = 3 = 3 ssTT22 = 76.0 = 76.0 ssTT

22/s/sRR22= =

13.613.6

Within Within TreatmentTreatment

ss

SSRR = 112 = 112 RR = 20 = 20 ssRR22 = 5.6 = 5.6

TotalTotal SSDD = 340 = 340 DD = 23 = 23 ssDD22 = 14.8 = 14.8

Page 36: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Conclusions

If null hypothesis were true, sIf null hypothesis were true, sTT22/s/sRR

22 would follow would follow the the FF distribution with distribution with TT and and RR degrees of degrees of freedom.freedom.

From Appendix L, the significance level for the F-From Appendix L, the significance level for the F-ratio of 13.6 with 3 and 30 degrees of freedom is ratio of 13.6 with 3 and 30 degrees of freedom is 0.000046. 0.000046.

This means that there is only a 0.0046% chance This means that there is only a 0.0046% chance that the means are equal.that the means are equal.

In other words, we can be 99.9954% sure that real In other words, we can be 99.9954% sure that real differences exist among the four different differences exist among the four different processes in our example.processes in our example.

Page 37: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Factorial Designs

Experimental designExperimental design: organized method of conducting : organized method of conducting experiments to extract maximum information from limited experiments to extract maximum information from limited experimentsexperiments

GoalGoal: systematically explore effects of input variables, or : systematically explore effects of input variables, or factorsfactors (such as processing temperature), on (such as processing temperature), on responsesresponses (such as yield)(such as yield)

All factors varied simultaneously, as opposed to "one-All factors varied simultaneously, as opposed to "one-variable-at-a-time“variable-at-a-time“

Factorial designsFactorial designs: consist of a fixed number of : consist of a fixed number of levelslevels for for each of a number of factors and experiments at all possible each of a number of factors and experiments at all possible combinations of the levels. combinations of the levels.

Page 38: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

2-Level Factorials Ranges of factors discretized Ranges of factors discretized

into minimum, maximum and into minimum, maximum and "center" levels. "center" levels.

In In 2-level factorial2-level factorial, minimum , minimum and maximum levels are used and maximum levels are used together in every possible together in every possible combination. combination.

A full 2-level factorial with A full 2-level factorial with nn factors requires 2factors requires 2nn runs. runs.

Combinations of a 3-factor Combinations of a 3-factor experiment can be represented experiment can be represented as the vertices of a cube.as the vertices of a cube.

(-1,1,1) (1,1,1)

(-1,-1,1)

(-1,1,-1)

(1,1,-1)

(-1,-1,-1) (1,-1,-1)

Page 39: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

23 Factorial CVD Experiment

FactorsFactors: : temperature (T), temperature (T), pressure (P), flow pressure (P), flow rate (F)rate (F)

ResponseResponse: : deposition rate (D)deposition rate (D)

RunRun PP TT FF D (D (Å/min)Å/min)

11 -- -- -- dd11=94.8=94.8

22 ++ -- -- dd22=110.96=110.96

33 -- ++ -- dd33=214.12=214.12

44 ++ ++ -- dd44=255.82=255.82

55 -- -- ++ dd55=94.14=94.14

66 ++ -- ++ dd66=145.92=145.92

77 -- ++ ++ dd77=286.71=286.71

88 ++ ++ ++ dd88=340.52=340.52

Page 40: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Main Effects Effect of any single variable on the response Effect of any single variable on the response Computation method: find difference between average Computation method: find difference between average

deposition rate when pressure is high and average rate deposition rate when pressure is high and average rate when pressure is low:when pressure is low:

PP = = dpdp++ - - dpdp-- = 1/4[( = 1/4[(dd22 + + dd44 + + dd66 + + dd88) - () - (dd11 + + dd33 + + dd55 + + dd77)] = )] = 40.86 40.86

where where PP = pressure effect, = pressure effect, dpdp++ = average dep rate when = average dep rate when pressure is high, pressure is high, dpdp-- = average rate when pressure is low = average rate when pressure is low

InterpretationInterpretation: average effect of increasing pressure from : average effect of increasing pressure from lowest to highest level increases dep rate by 40.86 lowest to highest level increases dep rate by 40.86 ÅÅ/min. /min.

Other main effects for temperature and flow rate computed Other main effects for temperature and flow rate computed in a similar mannerin a similar manner

In generalIn general: : main effectmain effect = = yy++ - - yy--

Page 41: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Interaction Effects ExampleExample: : pressure by temperature interaction pressure by temperature interaction ((P P ×× T T). ). This is ½ difference in the average temperature effects at This is ½ difference in the average temperature effects at

the two levels of pressure:the two levels of pressure:

P P ×× T T = = dPTdPT++ - - dPTdPT-- = 1/4[( = 1/4[(dd11 + + dd44 + + dd55 + + dd88) - () - (dd22 + + dd33 + + dd66 + + dd77)] = 6.89)] = 6.89

P P ×× F F and and T T ×× F F interactions are obtained similarly. interactions are obtained similarly. Interaction of all three factors (Interaction of all three factors (P P ×× T T ×× F): F): average average

difference between any two-factor interaction at the high difference between any two-factor interaction at the high and low levels of the third factor:and low levels of the third factor:

P × T × FP × T × F = = dPTFdPTF++ - - dPTFdPTF-- = -5.88 = -5.88

Page 42: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Yates Algorithm

Can be tedious to calculate effects and interactions Can be tedious to calculate effects and interactions for factorial experiments using the previous for factorial experiments using the previous method described above, method described above,

Yates AlgorithmYates Algorithm provides a quicker method of provides a quicker method of computation that is relatively easy to program computation that is relatively easy to program

Although the Yates algorithm is relatively Although the Yates algorithm is relatively straightforward, modern analysis of statistical straightforward, modern analysis of statistical experiments is done by commercially available experiments is done by commercially available statistical software packages. statistical software packages.

A few of the more common packages: A few of the more common packages: RS/1RS/1, , SASSAS, , and and MinitabMinitab

Page 43: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Yates Procedure Design matrix arranged in Design matrix arranged in standard order (standard order (1st column has alternating 1st column has alternating

- and + signs, 2nd column has successive pairs of - and + signs, 3rd - and + signs, 2nd column has successive pairs of - and + signs, 3rd column has four - signs followed by four + signs, etc.)column has four - signs followed by four + signs, etc.)

Column Column yy contains the response for each run. contains the response for each run. 1st four entries in column 1st four entries in column (1)(1) obtained by adding pairs together, and obtained by adding pairs together, and

next four obtained by subtracting next four obtained by subtracting top number from the bottom numbertop number from the bottom number of each pair. of each pair.

Column Column (2)(2) obtained from column obtained from column (1)(1) in the same way in the same way Column Column (3)(3) obtained from column obtained from column (2)(2) To get the To get the EffectsEffects, divide the column , divide the column (3)(3) entries by the entries by the DivisorDivisor 1st element in 1st element in IdentificationIdentification (ID) column is grand average of all (ID) column is grand average of all

observations, and remaining identifications are derived by locating the observations, and remaining identifications are derived by locating the plus signs in the design matrix.plus signs in the design matrix.

Page 44: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Yates Algorithm Illustration

PP TT FF yy (1)(1) (2)(2) (3)(3) DivDiv EffEff IDID

-- -- -- 94.894.8 205.76205.76 675.70675.70 1543.01543.0 88 192.87192.87 AvgAvg

++ -- -- 110.96110.96 469.94469.94 867.29867.29 163.45163.45 44 40.8640.86 PP

-- ++ -- 214.12214.12 240.06240.06 57.8657.86 651.35651.35 44 162.84162.84 TT

++ ++ -- 255.82255.82 627.23627.23 105.59105.59 27.5727.57 44 6.896.89 PTPT

-- -- ++ 94.1494.14 16.1616.16 264.18264.18 191.59191.59 44 47.9047.90 FF

++ -- ++ 145.92145.92 41.7041.70 387.17387.17 47.7347.73 44 11.9311.93 PFPF

-- ++ ++ 286.71286.71 51.7851.78 25.5425.54 122.99122.99 44 30.7530.75 TFTF

++ ++ ++ 340.52340.52 53.8153.81 2.032.03 -23.51-23.51 44 -5.88-5.88 PTFPTF

Page 45: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Fractional Factorial Designs

A disadvantage of 2-level factorials is that the A disadvantage of 2-level factorials is that the number of experimental runs increasing number of experimental runs increasing exponentially with the number of factors. exponentially with the number of factors.

Fractional factorialFractional factorial designs are constructed to designs are constructed to eliminate some of the runs needed in a full eliminate some of the runs needed in a full factorial design. factorial design.

For example, a half fractional design with For example, a half fractional design with nn factors requires only 2factors requires only 2nn-1-1 runs. runs.

The trade-off is that some higher order effects or The trade-off is that some higher order effects or interactions may not be estimable.interactions may not be estimable.

Page 46: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Fractional Factorial Example 223-13-1 fractional factorial design fractional factorial design

for CVD experiment:for CVD experiment: New design generated by New design generated by

writing full 2writing full 222 design for P design for P and T, then multiplying those and T, then multiplying those columns to obtain F.columns to obtain F.

DrawbackDrawback: since we used : since we used PTPT to define to define FF, can’t distinguish , can’t distinguish between the between the P × TP × T interaction and the interaction and the FF main main effect. effect.

The two effects are The two effects are confoundedconfounded. .

RunRun PP TT FF

11 -- -- ++

22 ++ -- --

33 -- ++ --

44 ++ ++ ++

Page 47: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Outline

IntroductionIntroduction Statistical Process ControlStatistical Process Control Statistical Experimental DesignStatistical Experimental Design YieldYield

Page 48: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Definitions YieldYield: percentage of devices or circuits that meet a : percentage of devices or circuits that meet a

nominal performance specification. nominal performance specification. Yield can be categorized as functional or Yield can be categorized as functional or

parametric.parametric. Functional yieldFunctional yield - also referred to as "hard - also referred to as "hard

yield”; characterized by open or short circuits yield”; characterized by open or short circuits caused by defects (such as particles). caused by defects (such as particles).

Parametric yieldParametric yield – proportion of functional – proportion of functional product that fails to meet performance product that fails to meet performance specifications for one or more parameters (such specifications for one or more parameters (such as speed, noise level, or power consumption); as speed, noise level, or power consumption); also called "soft yield"also called "soft yield"

Page 49: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Functional Yield

Y = f(AY = f(Acc, D, D00))

AAcc = critical area = critical area (area where a defect (area where a defect has high probability has high probability of causing a fault)of causing a fault)

DD00 = defect density (# = defect density (# defects/unit area)defects/unit area)

Page 50: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Poisson Model

Let: C = # of chips on a wafer, M = # of defect types

CM = number of unique ways in which M defects can be distributed on C chips

Example: If there are 3 chips and 3 defect types (such as metal open, metal short, and metal 1 to metal 2 short, for example), then there are:

CM = 33 = 27possible ways in which these 3 defects can be distributed over 3 chips

Page 51: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Unique Fault CombinationsC1C1 C2C2 C3C3 C1C1 C2C2 C3C3

11 M1M2M3M1M2M3 1515 M3M3 M2M1M2M122 M1M2M3M1M2M3 1616 M1M2M1M2 M3M333 M1M2M3M1M2M3 1717 M1M3M1M3 M2M244 M1M2M1M2 M3M3 1818 M2M3M2M3 M1M155 M1M3M1M3 M2M2 1919 M1M1 M2M3M2M366 M2M3M2M3 M1M1 2020 M2M2 M1M3M1M377 M1M2M1M2 M3M3 2121 M3M3 M2M1M2M188 M1M3M1M3 M2M2 2222 M1M1 M2M2 M3M399 M2M3M2M3 M1M1 2323 M1M1 M3M3 M2M21010 M1M1 M2M3M2M3 2424 M2M2 M1M1 M3M31111 M2M2 M1M3M1M3 2525 M2M2 M3M3 M1M11212 M3M3 M2M1M2M1 2626 M3M3 M1M1 M2M21313 M1M1 M2M3M2M3 2727 M3M3 M2M2 M1M11414 M2M2 M1M3M1M3

Page 52: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Poisson Derivation If one chip contains no defects, the number of ways to distribute M

defects among the remaining chips is:

(C - 1)M

Thus, the probability that a chip will have no defects of any type is:

Substituting M = CAcD0, yield is # of chips with zero defects, or:

For N chips to have zero defects this becomes:

C 1– M

CM

---------------------- 11C----–

M=

)exp(1

1lim 0

0

DAC

Y c

DCA

C

c

)exp()exp( 00 DNADAY cN

c

Page 53: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Murphy’s Yield Integral

Murphy proposed that defect density should not be constant. Murphy proposed that defect density should not be constant. DD should be summed over all circuits and substrates using a should be summed over all circuits and substrates using a

normalized probability density function normalized probability density function f(D)f(D). . The yield can then be calculated using the integralThe yield can then be calculated using the integral

Various forms of Various forms of f(D)f(D) exist and form the basis for many exist and form the basis for many analytical yield models. analytical yield models.

0

)(0 dDDfeY DAc

Page 54: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Probability Density Functions

Page 55: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Poisson Model

Poisson model assumes Poisson model assumes f(D)f(D) is a delta function: is a delta function:

f(D) = f(D) = ((D - DD - D00))

where where DD00 is the average defect density is the average defect density

Using this density function, the yield isUsing this density function, the yield is

)exp()( 0

0

0 DAdDDfeY cDAc

Page 56: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Uniform Density Function

Murphy initially investigated a uniform density Murphy initially investigated a uniform density function.function.

Evaluation of the yield integral for the uniform Evaluation of the yield integral for the uniform density function gives:density function gives:

c

AD

uniform AD

eY

c

0

2

2

1 0

Page 57: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Triangular Density Function Murphy later believed that a Gaussian distribution would Murphy later believed that a Gaussian distribution would

be a better reflection of the true defect density function. be a better reflection of the true defect density function. He approximated a Gaussian function with the triangular He approximated a Gaussian function with the triangular

function, resulting in the yield expression:function, resulting in the yield expression:

The triangular model is widely used today in industry to The triangular model is widely used today in industry to determine the effect of manufacturing process defect determine the effect of manufacturing process defect density.density.

2

02

1 0

c

AD

triangular AD

eY

c

Page 58: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Seeds Model Seeds theorized high yields were caused by a large Seeds theorized high yields were caused by a large

population of low defect densities and a small proportion population of low defect densities and a small proportion of high defect densities of high defect densities

He proposed an exponential function:He proposed an exponential function:

This implies that the probability of observing a low defect This implies that the probability of observing a low defect density is higher than observing a high defect density. density is higher than observing a high defect density.

Substituting this function in the Murphy integral yields:Substituting this function in the Murphy integral yields:

Although the Seeds model is simple, its yield predictions Although the Seeds model is simple, its yield predictions for large area substrates are too optimistic. for large area substrates are too optimistic.

00

exp1

)(D

D

DDf

cADY

0lexponentia 1

1

Page 59: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Negative Binomial Model

Uses Gamma distribution Uses Gamma distribution Density function: Density function: f(D)f(D) = [ = [(())]]DDeeDD

Average defect density is Average defect density is DD00 = =

f(D)

D/D0

= 3

= 2

= 1

Page 60: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Negative Binomial (cont.) Yield: Yield:

= “cluster” parameter (must be empirically determined= “cluster” parameter (must be empirically determined high: variability of defects is low (little clustering); high: variability of defects is low (little clustering);

gamma function approaches a delta function; negative gamma function approaches a delta function; negative binomial model reduces to Poisson modelbinomial model reduces to Poisson model

low: variability of defects is significant (much low: variability of defects is significant (much clustering); gamma model reduces to Seeds exponential clustering); gamma model reduces to Seeds exponential modelmodel

If the AIf the Acc and D and D00 are known (or can be measured), negative are known (or can be measured), negative binomial model is an excellent general purpose yield binomial model is an excellent general purpose yield predictor.predictor.

01

DAY c

gamma

Page 61: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Parametric Yield

Evaluated using “Monte Carlo” simulation Let all parameters vary at random according to

a known distribution (usually normal) Measure the distribution in performance

Recall:

Or: IDnsat = f (tox, VTn)

2TnGSoxnDnsat VV

L

WCI

Page 62: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Input Distributions

Assume: mean () and standard deviation () are known for tox, VTn

Calculate IDnsat for each combination of (tox, VTn)

tox VTn

Page 63: IC Manufacturing and Yield ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 15, 2004

Output Distribution

Yield (best parts) =

Yield (worst parts) =

a

dxxf )(

c

dxxf )(

f(x)

x

IDnsat

c (bad devices) b(moderate devices)

a (good devices)