IDE ControllerIDE Controller

Group MembersGroup Members Brian KuligBrian Kulig Graig PlumbGraig Plumb James PierpontJames Pierpont Saif ShaikhSaif Shaikh

AdvisorAdvisor Arun RamanathanArun Ramanathan

Development of an Ultra DMA Development of an Ultra DMA Module for a Hard Disk ControllerModule for a Hard Disk Controller

Specifications – IDE ATA5 StandardsSpecifications – IDE ATA5 Standards

RTL Description of PIO and Ultra DMA (Direct RTL Description of PIO and Ultra DMA (Direct Memory Access) Module in Verilog HDL Memory Access) Module in Verilog HDL (Support for PIO Modes 0 to 4 & UltraDMA (Support for PIO Modes 0 to 4 & UltraDMA Modes 0 to 4)Modes 0 to 4)

Behavioral description of the Hard Disk Behavioral description of the Hard Disk InterfaceInterface

Functional and Timing Simulations using Functional and Timing Simulations using Cadence VerilogXLCadence VerilogXL

ArchitectureArchitecture

IDEFSM

IDEFSM

DMAMODULE

PIOMODULE

DMAMODULE

PIOMODULE

To Hard Disk

To Hard Disk

IDE CHANNEL 0

IDE CHANNEL 1

Fifo’s and Rest

of System

Fifo’s and Rest

of System

Ultra DMAUltra DMA

Modes 0-4Modes 0-4 Data In(Out)Data In(Out)

• Initiate Data-in(out) BurstInitiate Data-in(out) Burst• Transfer the DataTransfer the Data• Pause Data-in(out) BurstPause Data-in(out) Burst• Terminate Data-in(out) BurstTerminate Data-in(out) Burst

Ultra DMA Ultra DMA ConstraintsConstraints

Ultra DMA Mode Cycle Time(nanoseconds)

MaximumTransfer Rate

(MB/s)

DefiningStandard

Mode 0 240 16.7 ATA/ATAPI-4

Mode 1 160 25 ATA/ATAPI-4

Mode 2 120 33.3 ATA/ATAPI-4

Mode 3 90 44.4 ATA/ATAPI-5

Mode 4 60 66.7 ATA/ATAPI-5

Programmed I/OProgrammed I/O

Modes 0-4Modes 0-4 Replicate Timing Diagrams Replicate Timing Diagrams

Presented In ATA/ATAPI - 5 Presented In ATA/ATAPI - 5 StandardsStandards

Much Simpler Than Ultra DMAMuch Simpler Than Ultra DMA

Programmed I/O Programmed I/O ConstraintsConstraints

Cycle Time(nanoseconds)

MaximumTransfer Rate

(MB/s)

DefiningStandard

Mode 0 600 3.3 ATA

Mode 1 383 5.2 ATA

Mode 2 240 8.3 ATA

Mode 3 180 11.1 ATA-2

Mode 4 120 16.7 ATA-2

Course Of ActionCourse Of Action

Two People Work on Programmed Two People Work on Programmed I/OI/O

Two People Work On Ultra DMATwo People Work On Ultra DMA Finish PIO And Focus On Ultra DMAFinish PIO And Focus On Ultra DMA Develop Behavioral Description To Develop Behavioral Description To

Simulate Hard DiskSimulate Hard Disk Simulate And Test Our InterfaceSimulate And Test Our Interface

Gantt ChartGantt ChartFeb

22-28March

1-8March9-15

March25-31

April1-7

April8-14

April15-21

April22-30

May1-8

Become Familiar withTools

Design PIO Mode

Software to SimulateHDD

Design of UDMA Mode

Simulate EntireOperation

Project Website

FinalFinal ProductProduct

Verilog RTL Description That Verilog RTL Description That Represents Ultra DMA And PIO Represents Ultra DMA And PIO ModulesModules

Behavioral Description of Hard Behavioral Description of Hard Disk InterfaceDisk Interface

ReferencesReferences

General IDE Information: General IDE Information: http://www.pcguide.com/ref/hdd/inhttp://www.pcguide.com/ref/hdd/index.htmdex.htm http://www.hardwarecentral.com/hardwarecentral/tutorials/39/1/

ATA5 Specification: ATA5 Specification: http://www.t13.orghttp://www.t13.org