ieee 1588, standard for a precision clock synchronization ...tb/twiki/pub/lehre/...ip time to live =...

© 2005 ZHW

Prof. Hans Weibel, Zurich University of Applied [email protected]

IEEE 1588, Standard for aPrecision Clock Synchronization Protocol

What is it?Where is it used?

How does it work?How to implement it?

© ZHW / H. Weibel, 24.2.2005 Emedded World / 2

What is it all about?

��

��

Packet Network

Distribution of• frequency and• timeover a packetnetwork

Master

Slaves


IEEE 1588 and other Time Dissemination NetworksWhy a new standard?

� NTP does a good job since many years� runs on legacy data networks� but some applications demand for much higher accuracy

� Specialized sync networks can do this job more accurate� but at much higher cost� e.g. IRIG-B, a specialized dedicated sync network� e.g. GPS, allows for global synchronization, requires outdoor antenna

� IEEE 1588 offers high accuracy over a data network� but requires hardware assistance� applicability restricted to a closed environment


Nature and Importance of System Time

System time can exist in different ways

� implicitly: the system does not have a real clock, but a timing behaviour given byoperational sequences in HW and/or SW; typical in small closed systems

� explicitly: time is represented by a clock; in complex systems most often anecessity

System time is important

� to coordinate measurement instant (sampling, triggering)

� to measure time intervals (and to calculate derived quantities)

� as a reference to determine the order of events

� to determine the age of data items (data correlation; data base replication)

� as a basis for the execution of coordinated actions (time based behaviour)� scheduled execution of scripts� scheduled execution of mutual exclusion

� to decouple communication from execution


Some important DefinitionsAccuracy and Stability

t

Deviationfrom theReference

accurate and stableaccurate and not stable

inaccurate and not stableinaccurate and stable

inaccurate and stable


Application of synchronized ClocksWhere is sub-µs Accuracy required?

� Automation and control systems� Synchronize multi axis drive systems� Synchronize subsystems with cyclic operation

� Measurement and automatic test systems� Correlation of decentrally acquired values� Time stamping of logged data

� Power generation, transmission and distribution systems� Control of switching operations� Reconstruction of network activities and events� Isolation of problems (distinguish cause and impact)

� Ranging, Telemetry and Navigation� Triangulation

� Telecommunications� Emulation of TDM circuits through packet networks

� Backup for other time sources� Loss of GPS signal


Application of synchronized ClocksAutomation and Control Systems

� Application of IEEE 1588 is announced by different organizationsproposing Real-time Ethernet concepts, such as� ETHERNET Powerlink� EtherCAT� CIPSync� ProfiNet

� System wide clock does not guarantee but enable real-time behaviourwith mechanisms such as� cyclic operation� time stamping of data� scheduled actions and communication� communication decoupled from execution



Example: Multi axis motion control, e.g. in a printing machine

� Many drives have to be synchronized

� Paper speed is 25m/s ( corresponds to 40µµµµs/mm)



© Picture: KUKA Roboter GmbH

Example: Multi axismotion control, e.g. incoordinated robots


Application of synchronized ClocksMeasurement and Data Acquisition Systems

� Capture / acquire data� within a distributed environment� simultaneously at different places� deliver data with a time stamp

� Processing� Correlate the data� Report the order of events to enable diagnosis� Reconstruct complex, fast and distributed activities

� Straight forward installation� Sync and data over the same standard packet network� no special sync lines required


Application of synchronized ClocksAutomatic Test Systems

Example: Automatic Test Systems based on Synthetic Instruments

� What is a Synthetic Instrument?� A collection of hardware and software modules that can be concatenated

together and configured to emulate a standard instrument.� Advantages: re-configurable, re-usable, less rack space!

� What is a Synthetic Instrument module?An elementary building block of a larger measurement system.� Synthetic Instrument modules can be used in reconfigurable applications� Simpler the building block, the easier to upgrade� Standard interfaces� Application software is external to the Synthetic Instrument module


Application of synchronized ClocksPower Generation, Transmission and Distribution Syst.

� Components of the power grid have to be protected from critical loadsituations and turned off

� Protection switching guarantees high service availability

� U/I is measured at all critical points within the grid at precise time pointsand in a high rate� to monitor the network� to predict critical load situations� to measure delivered/consumed power between providers

� The traditional solution for synchronization is based on a dedicated andcostly cabling (e.g. IRIG-B)

� Using the same network for data and synchronization has big economicand operational advantages


Application of synchronized ClocksPower Generation, Transmission and Distribution Syst.

Example:Substation Automationaccording to IEC 61850


Application of synchronized ClocksTelemetry / Navigation

t1 t2 t3Example: Positioning Systemfor Divers (SubmarineNavigation)

Principle is similar with GPS, but

� sonar instead of radio

� bojes insted of satellites


Application of synchronized ClocksTelecommunications

� Frequency distribution over packet networks� Circuit Emulation Service in packet networks (TDM over Packet)

�� becomes more and more attractive in IP-centric infrastructure� compelling solution in pure Ethernet configurations such as

Metro Ethernet or Eternet in the First Mile

� Base station synchronization� for handover (GSM, DECT, …)� Single Frequency Networks (SFN) such as Trunk Radio systems or DVB,

where all transmitters are synchronously modulated with the same signal andoperate on the same frequency

� Benefits for Operations Support Systems (OSS)� Billing mechanisms� SLA-compliance checking


Application of synchronized ClocksTelecommunications

Packet Network

PacketFlow

Bit Stream(TDM)

Example: Emulation of a TDM Circuit over a Packet Network� Packet Network may be Metro Ethernet, IP, ATM or MPLS

� Sync Network may be separate or - if IEEE 1588 is applied - the same as for the payload

� Goal is fs = fd

Bit Stream(TDM)

Packetization De-Packetization

ClockingData In

ClockingData Out

Synchronization Network

fdfs

SwitchEdge Edge


IEEE 1588 SpecificationContents of the Standard

� descriptors to characterize system clocks

� states and behaviour of system clocks

� data type definitions

� time representation

� Precision Time Protocol (PTP) operation� Determination of a loop-free topology� Selection of the master clock (Master Clock Selection Algorithm)� Syncronization of system clocks

� details of application in Ethernet networks

� conformance requirements


IEEE 1588 SpecificationGoals

� synchronization of distributed system clocks with high precision (< µs )

� applicable in any multicast capable network� the focus here is Ethernet

� easy configuration

� fast convergence

� support of a heterogeneous mix of different clocks with differentcharacteristics (accuracy, resolution, drift, stability)

� moderate demand for bandwidth and computing ressources


Principal Operation of Clock Adjustment

The Master Clock sends itstime to the Slave Clock. Theremaining error corres-ponds to the transfer delayof the time message.

PTP Precision Time Protocol (Application Layer)UDP User Datagram Protocol (Transport Layer)IP Internet Protocol (Network Layer)MAC Media Access ControlPhy Physical Layer

UDP

IP

MACPhy

PTP

UDP

IP

MAC

Phy

�� Master Clock Slave Clock

Network

PTP


Main Problems are Delay and Jitter

UDP

IP

MACPhy

PTP

UDP

IP

MAC

Phy

�� Master Clock Slave Clock

Delayand

JitterProtocol

Stack

Delay and JitterNetwork

DelayandJitterProtocolStack

Network

PTP

MII MII

The Transfer Delay can bemeasured and eliminated. Itremains an error caused byfluctuations of the transferdelay, called Jitter.

PTP Precision Time Protocol (Application Layer)UDP User Datagram Protocol (Transport Layer)IP Internet Protocol (Network Layer)MAC Media Access ControlPhy Physical Layer


Delay and Offset Determination

Follow_up(t0)

Sync(testim)

testimt0

Delay_Resp(t3)t3 = t2-O+D

pretended concurrencyO = Offset = ClocksSlave – ClocksMaster

Delay_Req

t3

t2B

measured values t1, t2, t3, t4

A = t1-t0 = D+O

B = t3-t2 = D-O

Delay D =

Offset O =

A + B2

A - B2

t1 = t0+D+O

A

O

D = Delay

Master Clock Slave Clock40

42

44

46

48

50

52

54

56

58

60

62

64

40

42

44

46

48

50

52

54

56

58

60

62

38


Frequency and Time Transfer

� Drift Compensation �� Frequency Transfer� When free running, the slave‘s oscillator has not exactly the same frequency

as the master� Consecutive time stamped SYN messages allow to determine and

compensate the deviation (accelerate or slow down the oscillator)� The frequency varies over time (due to environmental conditions, e.g.

temperature, acceleration, vibration, etc.)� This compensation is repeated regularly (frequency depending on

oscillator stability and desired accuracy)� Remember: 1 ppm results in 1 us / s

� Offset Correction �� Time Transfer� Set the slave‘s time to the master‘s time� Correction is based on the round trip time measurement (carried out

by time stamped SYN and Delay_Req messages)


Sync Interval and Network Load

� Dimensions� 1 ppm of deviation corresponds to 1 µs per second (1 µs/s results in 1s/12 days)� a cheap quartz has a temperature dependance of 1 ppm/0C or more

� In order to achieve high accuracy, frequent adjustments are required� the standard allows for Sync intervals of 1, 2, 8, 16 and 64 seconds� it is proposed to extend this choice to ⅛, ¼ and ½ seconds

� Sync and Follow_up messages are sent as multicasts� the master can serve all slaves of a segment with one single message� this enables each slave to calculate its offset individually (provided that the delay is

known)

� Delay_Req and Delay_Resp messages are point-to-point, but sent withmulticast addreses anyway (no address administration required)� this enables the slave to calculate the delay (assumed that transmission is

symmetric, i.e. same transit delay for both directions)� because delay is assumed not to change quickly, it is not measured as frequent as

the offset is -> resulting network load is fairly low


PTP over UDP / IP / Ethernet

� UDP Port 319: event port for Sync und Delay_Req messagesPort 320: general port for Follow_up, Delay_Resp and Mgmt messages

� IP Time To Live = 0, i.e. will not be forwarded by routersmulticast addresses224.0.1.129 for PTP-primary (default Domain)

224.0.1.130 for PTP-alternate1 (alternate Domain)224.0.1.131 for PTP-alternate2 (alternate Domain)224.0.1.132 for PTP-alternate3 (alternate Domain)

� Ethernet

Src L/T Data CRCDstPreamble SFD

10101011

Time Stamp Point

Ethernet Frame

IP H PTP MessageUDP H


Hardware assisted Time Stamping

precise send time

precise receive time

Follow_up(precise send time)

Offset Computation

Delay_Resp(precise receive time)

Delay Computation= (t1-t0)+(t3 -t2)/2

precise send timeprecise receive time

Time Stamping

PTP Applic. MII MII PTP Applic.Master Clock Slave Clock

t t

t0estimated send timeSync(estimated send time) t1

Delay_Reqt3

t2


Concept of Boundary ClockEliminate the Network‘s Fluctuation!

PTP

UDP

IP

MAC

Phy

PTP

UDP

IP

MAC

Phy

��

MAC

Phy

MAC

Phy

Switch with Boundary ClockMaster Clock Slave Clock

Switching Function

MII

Time Stamp Unit

PTP

UDP

IP

��Slave

PTP

UDP

IP

Master


Topology and „Best Master Clock“

M

MS

M M

MSM M

S

SSSS

Ordinary Clock, Grandmaster: clockselected as „best Master“ (selection basedon comparison of clock descriptors)

Ordinary Clock

Boundary Clock, e.g. Ethernet switch

S: Port in Slave StateM: Port in Master State


ImplementationHow to achieve high Accuracy?

� Time stamps have to be taken as near as possible to the physical layer, inorder to eliminate the impact of protocol stack and operating systemsoftware� Implementiation with HW assistance:

� Install a PTP message detector and time stamp unit at the MII (MediaIndependent Interface, connecting MAC and PHY).

� Exact time stamp has to be taken for every emission and reception of relevantPTP messages (i.e. Sync and Delay_Req).

� Implementiation without HW support:� Time stamps taken by SW, at the entry/exit point of the interrupt service

routine serving the MAC controller or at the application layer

� Provide Boundary Clocks in switches (and routers)� switch has its own clock which is synchronized with the master� plays the slave role at one port and the master role on all remaining ports

� Use statistical mehtods to reduce jitter� filtering, averaging, ...� such methods slower the convergence


ImplementationStatistical Methods

� Even with HW assistance, some fluctuations can still be observed� quantization effects due to time stamp resolution� jitter in the data path (PHY chips, eventually hubs)� oscillator instabilities

� Stochastic fluctuations may be removed by statistical methods� filtering and averaging algorithms� long-term averaging requires a reasonable oscillator stability

� If a topology change occurs (e.g. fast reconfiguration in ring configuration)� filtering and averaging slower the convergence� if reconfiguration can reliably detected, filtering and and averaging should be

bypassed to accelerat convergence

� Systematic effects remain� e.g. imperfect symmetry


PTP Protocol Engine

PHY PHY

TSU Clock

TSU Interface CLK Interface

PHY

MAC

IP

Application

TCP UDP

Port Interface

RXTX

TimeStamps

Drift Offset Time

Packets

PPS

PC/104 Board

OSC

Network Interface

ImplementationZHW‘s Eval Kit as an Example


PTP Protocol Engine

TSU Interface CLK Interface

PHY

IP

Application

TCP UDP

Port Interface

Data

Packets

ImplementationA typical IEEE 1588 enabled Network Interface

TimeStamps

DriftOffsetTime

MDIO

MII Clock PPS

OSC

TSU

MACDriver

timed I/O


ImplementationHardware Assistance - Overview

Time Increment

PTP EventFrame

Detector

Time Stamp

Snapshot

Time Stamp

Compare

+

≥

MII

Input

Output

Time stampersfor PTP frames

- one for TX- one for RX

Time stampersfor ext. events

Clock

Time triggeredoutputs

2

k

m

1tn

tn+1

Registers


ImplementationHardware Assistance – Clock Design Details

s ns fractions of ns

ns fractions of ns Increment

tn

s ns fractions of ns tn+1

Overflow∑

� The nominal increment is choosen according to the nominal oscillator frequency� The drift is compensated by slightly increasing od decreasing the increment

31 0 31 0 k 0


Synchronization via HubStart-up Period


Synchronization via HubAccuracy under stable Conditions

Values: 1’000

Max: 80ns

Min: -120ns

Mean: 4ns


PerformanceDeviation of two synchronized Clocks

Offset betweenMaster and Slave+ / - 60 ns

Std deviation: 15ns

© Hirschmann Electronics


IEEE 1588 StandardStatus and Future

� Standard was approved 12th of September 2002 and published in Nov 2002� IEC has adopted the standard under the label IEC 61588 in 2004� Application of IEEE 1588 was announced by different standards

organizations and interest groups� First commercial IEEE 1588 enabled products are on the market� On a plug fest, several implementations have proved interoperability� Components with integrated HW assistance were anounced or are available

� ERTEC from Siemens� netX from Hilscher� XScale network processor from Intel� hyNet32XS from Hyperstone

� Increasing interest in new application areas� A standard revision working group has been established to elaborate

enhancements and improvements to meet new requirements


Next Version of the IEEE 1588 StandardProposed Enhancements

� Resolution of known errors

� Conformance enhancements

� Enhancements for increased resolution and accuracy,i.e. shorter sync interval; higher time stamp resolution

� Increased system management capability, i.e. SNMP support

� Mapping to DeviceNet

� Annex D modifications for variable Ethernet headers

� Prevention of error accumulation in cascaded topologies,i.e. transparent clock

� Ethernet layer 2 mapping and short sync message format

� Extensions to enable implementation of redundant systems

� Extension mechanism, i.e. uniform way of extending fields/messages


Many thanks for your attention!

Prof. H. Weibel

Zurich University of Applied SciencesInstitute of Embedded Systems

http://ines.zhwin.ch

ieee 1588, standard for a precision clock synchronization ...tb/twiki/pub/lehre/...ip time to live =...

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