An Equivalent Circuit Approach to Semiconductor Device Simulation

TONY K. P. WONG and PHILIP C. H. CHAN Dept. of Electrical and Electronic Engineering,

The Hong Kong University of Science and Technology, Clear Water Eay, N.T., Hong Kong. Te1:358-7082

Area A : Silicon Process Technology & Devices

I. INTRODUCTION Equivalent circuit models have been developed by Sah [1,2] to describe the small signal characteristics of a semiconductor device. The model is derived from the set of differential equations governing the carrier transport in semiconductor. They are the electron and hole current equations, the carrier continuity equations, the kinetic equations that govem the generation, recombination, trapping processes and the Poisson’s equation. These equations can be expressed in terms of V, (electrostatic potential), V,, V,, and V, (quasi-fermi potential of electrons, holes and recombination centers respectively). These equations may be solved simultaneously or iteratively. Chan and Sah [3] have transformed the set of equations into an equivalent circuit. The dc equivalent circuit is shown in Fig.]. Only one lump of the equivalent circuit is shown in Fig.1. The number of lumps can be increased as required by the accuracy. With the transformation, the device simulation problem becomes a circuit analysis problem. The dc solution of the device can be obtained by applying the Newton-Raphson iteration technique to the circuit model. A trial dc solution is made to compute the error sources and circuit elements in Fig.1. The potentials V,, V,, V,, V, are solved by KCL. They are then used to correct the trial solution. The new solution, in turn, becomes the trial solution for the next iteration. The iteration is repeated until the potentials converge. The converged solutions are the dc potentials of the device. Device parameters and terminal characteristics can be computed using the potential distribution.

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Figurel. One section of equivalent circuit f o r single-energy level SRH center with error sources.

This paper presents a simulation program using the equivalent circuit model approach by applying a symbolic manipulation tool to simplify the analysis of circuit model equations. The result is used to obtain the dc solution of a p+/n junction. The simulated dc solution of an abrupt junction will be

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compared with those obtained from analytic expressions to show that the simulator indeed produces correct result. Simulation on a device with Gaussian impurity profile is also performed to show the versatility of this approach.

11. CIRCUIT ANALYSIS PROCEDURE A section of the equivalent circuit with single Shockley-Read-Hall (SRH) center for dc analysis is shown in Fig.1. The expressions for the circuit elements can be found in [3]. When the dc solution is achieved, the four error sources re,,, rep, I, and Q drop out and the model reduces to the small-signal ac circuit [4]. By applying Kirchhoff's current laws (KCL) at nodes vpk, V: and v:, and charge conservation at node v:, and eliminating the nodes v: by expressing them in terms of the other three potentials, a set of three linear algebraic equations can be obtained relating the sections k-1, k, and k+l. The symbolic manipulation tool MAPLE [5 ] is employed to transform the three linear equations into a Matrix form :

[v]'" = [XI' [VI' + [YIk [v]"" + [A]' where [VI' is a 3 by 1 vector containing v:, v:, v:. [XI' and [Y]' are 3 by 3 matrices containing the circuit elements and [A]' is a 3 by 1 matrix containing the error sources. In order to extract the element expressions from the matrices for the simulation program to use, the set of matrix equation can be re-arranged to form a single matrix of XY with the help of MAPLE. First, we combine [XIk and [YIk matrices into a 3 by 6 matrix and obtain

The [XU] and [A] matrix elements in symbolic expression can be extracted and translated into FORTRAN code using the MAPLE converter. The extracted matrix elements are only for one section of the equivalent circuit model. The elements are re-arranged to form a band sparse matrix. For N-sections model the system of equation is:

[VI'+' = [XYIk [\,Ik.'+' - [A]'

S is a 3(n+l) square sparse matrix with the boundary conditions which are set for the small signal circuit (error calculations) as ~pn+~=v,,"*'=vin+l=O at the x=L and vpl=v,,'=vil=O at the input x=O. This provides 3(n-1) equations with 3(n-1) interior unknown potentials. The entire matrix is then solved by using the IMSL routines [6] as described in next section, and the error potentials along the transmission line circuit can be obtained.

111. COMPUTATIONAL SIMULATION PROCEDURE Fig.2 shows a flow chart of the iteration procedure performed by the simulation program. The dopant impurity concentration profile and the parameters of recombination center are input. The number and the size of sections are also input. A piecewise-linear approximation is used for the initial trial solution of V, at zero bias. The equilibrium Fermi potential is calculated at x=xL using the charge neutrality condition and then the contact potential at x=O is worked out. In order to minimize the round off error on the numerical data in solving the sparse matrix, all numerical data should be declared as a double precision type in the program for gaining the accuracy. The program begins at zero bias and calculates the value of circuit elements using the set of input initial trial solutions. Having done that, the program will work on the equivalent circuit matrices to re-arrange the N sections of matrix elements into a sparse matrix format which can be operated by the IMSL sparse matrix routine. The M L routine will then be called upon to solve the sparse matrix and the result obtained is the error potentials. The trial solution is corrected by the error potentials and the improved solution is used to compute the circuit elements and the error sources. Repeat the process until the error potential becomes sufficiently small ( <lo7 ). The dc potentials have then converged. The set of converged true potentials can be used as the trial solution for the next applied bias voltage except at k=l section. The three potentials at k=l are increased by AV, the increase in applied voltage. The process is repeated with the new applied voltage until the circuit solution converged. The program continues to perform calculations and terminates when a desired bias voltage has reached.

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1V.SIMULATlON RESULT To demonstrate the Fortran simulation program, a p+/n abrupt junction diode was analysed under the zero bias condition. The dopant impurity profile of the device is N,=3~10'~ cm" in the pi region and ND,=5.7x10'' cm.3 in the n region. The junction depth is 5um. The recombination center is taken to be zinc and is assumed constant in the device and equal to 10'' cm-', and the calculations are done at 29%. Since the dc analysis is required only, s=jw terms are set to zero for all capacitors. Other parameters were used in the program as follows: q=1.5x101" cm-', a capture rate for electrons of cn=5x1O-" cm'/sec. and for holes of c,=6.Ox1O4 cm3/sec and corresponding emission rates of e,=19.286 sec-' and e,=2.9x101 sec-' 131. The device was divided into 100 sections and 60 of them were placed in the space-charge region where a major change in electrostatic potential is expected. Trial solution was a piecewise linear approximation with a linearly increasing potential variation over the space-charge region. Convergence to the final true solution was obtained in nine iterations. Fie.3 shows the trial " solution and the converged solution of V. at zero bias.

PLOT LEGEND Proqram Plot +

Trial solution * Approx. plot -

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X (microns) gure 3. Comparison of the calculation and simulation results with the trial solution.

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Using the depletion approximation, the contact potential to the width of the depletion region can be calculated by integrating the Possion's equation twice. Substituting different length values to the equation obtained, the contact potential variation over the space-charge region can be calculated. Fig.3 also shows comparison of the calculated result and the simulation result. The two curves are very close to each other. Note the simulation does not assume depletion approximation. The same device but with Gaussian dopant impurity profile was used for the forward and reverse bias simulations. It has the Gaussian profile as N,(x)-N,,(x)=3~10'~ e~p(-x~/2.3~10~~)-5.7~10'~. For this device, 180 sections were used and 60 of them were placed in space-charge region. Simulation started from zero bias and converged at seventeen iterations. Fig.4 shows the result of electrostatic potential (Vi) and Fermi potentials (VN, V,). V, and V, are constant throughout the length of device. Increase the apply voltage to force the device in forward bias, Fig.5 illustrates the three potentials for the bias at 0.1V. The drop of Vi occurs very close to the contact since the length of the p' region is much smaller than the diffusion length. The minority hole potential in the n-type region decreases slowly until the equilibrium value is reached, while the majority electronic potential is almost constant along the device. The simulation agrees with the result obtained in [3] using a different approach. For the reverse bias, a negative voltage was applied to the k=l section and then proceeded with the iteration. With the voltage step size of O.O2V, the reverse bias dc solution at 1.3V is shown in Fig.6.

V. CONCLUSION The development of a simulation program based on the equivalent circuit model approach and using symbolic manipulation tools was presented. We have shown that the result from simulation program is verified with simple analytical expressions. We have also shown that this approach is general in a sense that any arbitrary impurity and recombination center profiles can be used. In this approach, the device is converted to an equivalent circuit. We expect this approach to be useful for mixed circuit and device simulation. Although we have only present the result for dc analysis, the result can easily be extended to transient and small-signal analysis.

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X (m ic rons j igure 4. converged solution of electrostatic potential at zero bias for gaussian junctior

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VP plot VN plot- Forwurd Bios

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igilre 5 . Electrostatic and quasi-fermi potentials at 0.1V forward bias for gaussia m c ti on

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igure 6. Quasi-fermi potentials at 1.3V reverse bias f o r gaussian junction.

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VI. REFERENCES [l] C.T. Sah, Proc. IEEE, vo1.55, p.654, 1967. [2] C.T. Sah, Solid-state Electron., vo1.13, p.1547, 1970. [3] P.C.H. Chan. C.T. Sah, IEEE Trans. on Electron Devices, vol. ED-26, p.924, 1979. [4] M.A. Green, J. ShewChun, Solid-state Electron., vo1.17, p941, 1974. [5] "Maple V User's Manual", Springer-Verleg, 1992. [6] "IMSL User's Manual (Fortran subroutine for maths. applications)", Ver.2.0, 1991.

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