Proceedings 1994 EEE International SO1 Conference, Oct. 1994

A METHODOLOGY FOR CONVERTING POLYGON BASED STANDARD CELL FROM BULK CMOS TO SO1

Kevin Y. WU, C. H. than Department of Electrical & Electronics Engineering

Clear Water Bay, Kowloon, Hong Kong

Phone: (852)358-7041 Email: eepchan@usthk.BITNET

The Hong Kong University of Science & Technology

Fax: (852)358-1485

The SO1 (Silicon On Insulator) M O S has many potential advantages over the traditional bulk CMOS circuit as it is free of latch-up and has improved perfo&&ce and a higher-packing density. The thin-film fully depleted SO1 is the most attractive among other types SO1 technologies not only due to its improved property such BS subthreshold slope and reduced parasitic, but also due to its simple fabrication process comparing to bulk CMOS. It is becoming a viable technology for ULSI due to recent advances in highquality thin-film SO1 wafer technology. It has same layers as bulk CMOS except the well, the substrate contact and the well contact. In this paper we shall present a methodology to convert a polygon-based fullcustom bulk CMOS to SOYCMOS. The objective is to convert existing bulk CMOS layout to SO1 automatically. The methodology is implemented using the Virtuoso Layout System from Cadence Design System. We shall illustrate the methodology using the Orbit Scalable CMOSN standard cell library.

The layout conversion process involves the following steps. First, the bulk CMOS is converted to SO1 by removing well, substrate contacts and well contacts. In the next step a compactor is used to remove the unused space while ensuring the design rules are met. Since our goal is to apply our methodology to hand-crafted full-custom polygon-based layout. we must first convert the polygons to symbolic layout so that it can be operated by the compactor. The compaction must be done with proper constraints so that the architecture of the standard cells are retained.

Note that this methodology can also be applied to further reduce the SOYCMOS cell area because of 1) decreased transistor sizes due to reduced parasitic capacitance; 2) reduced n and p transistor spacing in SOI; 3) reduced power and ground bus width due to decreased in current drive if the SOYCMOS is to operate in lower voltage. We can convert the CMOSN standard cell library to SOYCMOS with an arbitrary set of design rules using this methodology and proper scaling of the original bulk CMOSN standard cell layout. Next, scaling is discussed in more detail.

If all layers of the cell are scaled by the same factor, we simply place an instance of the cell with the scaling factor. The placed cell is flattened since our methodology do not support hierarchy. The scaled bulk CMOS standard cell is then converted to SO1 cell. Changes in specific design rules can be handled as follows. If only spacing rules are changed and the width rules remain the same. the SO1 cell can be directly converted to SO1 symbolic layout. The compactor will compact the cell based on the layer properties. If the layer widths are also changed, the changed widths can be incorporated by setting path width in the symbolic layout. The paths will be generated with proper widths. If rules related to symbolic devices such as the contact enclosure rules needs to be scaled, the symbolic 'rules in the technology file must be modified. After that, Layout Versus Schematic (LVS) is performed to make sure the connectivity of the cell is correct.

nof- We choose to use Cadence Virtuoso Layout System to implement the methodology instead 0; writing our

own because it has essentially all the features we need and that we can customize the tool to implement the methodology by SKILL calls to the system kernel. We can modify the parameters of data object through SKILL calls. Through SKILL calls, we can integrate our applications to the Cadence environment. For this application, three main sets of SKILL functions are used. They are Database Access, Layout Editor Functions and Graphics Editor.

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"IT& work is supported by RGC Earmarked Research Grant HKUST 547/94E.

94CH35722

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Most full-custom layouts are constructed using polygons. Polygons must be converted to symbolic layout before it can be operated by a compactor. We have developed heuristics to convert specific layers from polygon to symbolic depends on the characteristics of each layer. The heuristics are too detailed to be described here. The results are shown in Figure 1.

The Symbolic layout generated from the above conversion is compatible with the Cadence compactor. The compaction is based on the design rules set in the layer property and symbolic rules. There are many compaction heuristics that must be tuned to generate desirable results. The heuristics include many types of constraints such as separation, width and alignment constraint. Wire length minimization is used to guarantee the wire length is minimized. All of the cell pins must remain at the cell boundary throughout the compaction. The result of compaction also depends on individual cell layout.

The conversion methodology is illustrated in Figure 1. The cell presented is DEL.-2 that has eight inverters connected in series. Figure l(a) shows the original bulk CMOS from the Orbit Scalable CMOSN library. Figure l(b) shows the cell converted to SOI. The SO1 cell is COPT-erted to symbolic layout in Figure l(c). Figure l(d) shows the compacted cell. The symbolic layout is converted back to polygon in Figure l(e>.

We have experimented the above methodology using five cells. We use the same design rule for both the bulk CMOS cell and SOI/CMOS. That is the design rules used in bulk CMOS used are also applied to SOUCMOS except that there is no well, substrate contact, well contact related design rules. The results are shown in Table 1. The first row of Table 1 is the original cell size that is the size of SO1 symbolic cell before compaction. The second row is the cell size after compaction. The third row is the percentage reduction of cell area, that is (cell size after compaction - original cell size) / original cell size * 100%.

a m % Redudion -6.6 I -27.6 I +5.1 I -2.4 I Table 1 Bulk CMOS to SO1 c~npaction results "e lhe same design rule

All of these cells show that the cell area is reduced after the compaction except COM8. This cell size increased after compaction. The reason is that the large cell is more complex and is already very compact. After compaction, there is more chance for large optimized cell to become larger. In this case, compaction does not help and should not be used unless the cell is scaled to a set of reduced design rules.

Conclusion We have developed a methodology to convert polygon-based full-custom bulk CMOS cells to SOUCMOS.

This methodology is implemented using the Cadence Design Systems Virtuoso environment. We have demonstrated the methodology by converting the Orbit Scalable CMOSN standard cells. The results are quite good for small cells. However, for complex and highly optimized cell, this methodology may lead to a slight increase in the cell area. We will also demonstrate that this methodology can also be applied to further reduce the cell areas if the SOUCMOS cells are resigned to take advantage of the low-power and high-performance capability of SOUCMOS during presentation.

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