Bennv T. Y. Cheung , Jack Lau, Samuel K. E?. Fung, and Philip C. H. Chan Department of Electricall and Electronic Engineering

The Hong Kong University of Science and Technology Clear Water Bay? Hong Kong

e-mail : eedenny@ee.ust.hk, phone : (852) 2358-8844, fax : (852) 2358-1485

In this paper, a narrow-width methodology (NWM) for designing analog gain stages in SO1 technology is pre- sented. By employing NWM, we can achieve better circuit perfomance in SO1 when compxed with bulk CMOS. Given the same testing conditions for both bulk and SO1 2-stage Miller compensated op amp, our study showed a 2X+ speed improvement and a 2X+ reduction of compensation capacitance in SOI. With a judicious choice of transistor sizes, one can also exploit the speed advantages of SO1 circuits over bulk in other op amp topologies such as folded-cascode.

SO1 technology has been highly promoted as a suitable candidate for low power circuit applications [ 11. One of the cited reasons is the small parasitic capacitance which is mainly attributed by : (1) the reduced bottom-wall drain/source-to-substrate capacitance (Cjw) due to the underneath buried oxide; and (2) the single-sided drain/ source side-wall capacitance (CjSw) in SO1 rather ahan four-sided in bulk [21 because of the mesa isolation. A 3-D structure of SO1 MOSFET is shown in Figure 1. As far as narrow-width device is concerned, the ratio of C, and Cg, increases in bulk case since C, is dominated by the side-wall Capacitance along the length of drain region rather than the device width. For SOI, the ratio of Cdb and C,, is nearly constant with different width. This is illus- trated in Figure 3. Moreover, by reducing the transistor width, one can also lower the power dissipation [3].

For the traditional 2-stage op amp built on SOI, poles are related to the nodal capacitances (Cdb and Css at nodes 1 & 2 in Figure 2) and the Miller compensation capacitance, C,. C, also depends on the nodal capacitances in the output gain stage. With the width reduction of the output transistor (M7), the nodal capacitances, as well as C, (for ensuring stability), are also reduced. As a result, better frequency response can be achieved. By employing NWM in SO1 op amp design, results showed that only 45fF is required for C,. Moreover, the unity-gain frequency vmiQ) can be boosted up to 170MHz as W, is reduced to be 2pn. This resulted in great improvement over their bulk counterparts. Figure 4 shows the frequency response and Table 1 summaries the circuit performance of the op amp in both technologies.

For the folded-cascode architecture, the dominant poles are also related to the output loading capacitance (CL) and the nodal capacitances of the output stage transistors (M8-Mll in Figure 2) [4]. By reducing the width of these transistors, 50% of improvement in speed performance was obtained. Moreover, C, for a phase margin of 45’ is even smaller in the narrow width design (Wg41=2pn). Obviously, the larger the CL, the larger the phase margin will be obtained and the more stable of the circuit will be. The results are shown in Figure 5 and Table 2 V;,it, is 53.43MHz for SO1 while 38.65MHz for bulk).

All devices built on the test circuits are source-body-grounded non-fully depleted (NFD) SO1 transistors [5], which are quite suitable for analog circuits. However, experimental measurement shows that Vth increases slightly with reducing the device width. This V,h shift is attributed to the bird‘s beak effect, which increases the side-wall oxide of the transistor 161.

t is supported by RGC Earmarked Grants HKUST 547/94E and HKUST 681/95E.

[l] [2] [3] E41 [5] [6]

J. P. Colinge, Ecole Polytechnique Advanced Engineering Course, Switzerland, June 1995. K. Kumagai et. aL, Proceeding of 1994 IEEE International SO1 Conference, pp. 15-16, Oct. 1994. M. Horowitz, “Low-Power Digital De~ign’~, I994 IEEE Sym. on Low Power Electronics, pp. 8-11,1994. S . M. Mallya et. aL, IEEE Joumal of Solid-state Circuit, Vol. 24, No. 6, pp. 1737-1740, Dec. 1989 M. Chan et. aL, IEEEi Transaction on Electron Devices, vol. 42, no. 11, pp. 1975-1981, Nov. 1995. S . K. H. Fung et. al., Proceeding of 1995 IEEE International SO1 Conference, pp. 88-89, Oct. 1995.

0-7803-3315-2

Proceedings 1996 IEEE International SO1 Conference, Oct. 1996 23

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Figure 1 : 3-D structure of SO1 nMOSFET. Figure 2 : Schematics of 2-stage (left) and folded-cas- code (right) op amps.

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Figure 3 : C&Cgs versus W with different L in SO1 (solid) and bulk (dashed) technologies.

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F - w w W ) Figure 4 : Voltage gain (solid) and phase (dashed) plots of SO1 2-stage op amp.

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Figure 5 : Voltage gain (solid) and phase (dashed) plots of SO1 folded-cascode op amp.

Table 1 : Performance Summary of 2-stage op amp with different W, for both technologies.

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Figure 6 : Vrh shift versus drawn W for SO1 MOSFET.

Table 2 : Performance Summary of folded-cascode op amp with different Ws-ll for both technologies.

96CH35937 0-7803-3315-2