112 200OIEEE Intemational SO1 Conference, Oct. 2000

High performance Gate-All-Around devices using Metal Induced Lateral Crystallization

Victor W. C. Chan, Philip C. H. Chan Department of Electrical & Electronic Department, Hong Kong University of Science and Technology, Hong Kong

Introduction Double gate or gate-all-around transistors were predicted to cohtinue the improvement in device

performance down to 0.02 pn gate length [l-31. In our work, high performance gate-all-around transistor (GAT) is demonstrated. The device is fabricated from either a bulk silicon wafer or on the top of any device layers. The fabrication process uses Metal-Induced-Lateral-Crystallization (MILC) to recrystallize the amorphous silicon to form large silicon grain in the active area. Using this thchnique, the transistor performance is comparable to a SOI MOSFET [SI. Compared to the method of cavity etch on the buried oxide, our method provides a uniform bottnm gate length [2]. Compared to the single-gate thin film transistor (SGT) and solid phase crystallization (SPC) device, GAT has lower subthreshold slope, lower threshold voltage, higher transconductance, nearly double drive current and lower off-current. The impact of channel length and width scaling is investigated.

Fabrication of the device Fig. 1 shows the schematic diagram of the GAT structure. A 3000A thermal oxide is grown on the silicon

substrate and serves as the buried oxide. A silicon nitride film of 2500A thickness is deposited and is etched with a dummy gate pattern. 2000A oxide is deposited and blankly etched to form an oxide spacer. Subsequently, an amorphous silicon film of IOOOA is deposited. Metal induced lateral crystallization (MILC) is applied as follow [5]. After 508, of nickel is deposited, lateral crystallization is carried out at 560°C for 50 hours in N2 ambient. The remaining nickel is removed. The re-crystallization annealing is performed at 900°C for an hour to enhance the g a i n size. This poly-silicon film is then patterned by e-beam lithography and to form the device channel. The feniaining silicon nitride is completely removed by hot phosphoric acid. A hollow is formed'for the bottom gate. After VI adjustment implantation, a 140A thick gate oxide is thermally grown. Doped poly-silicon is deposited and patterned to form the gate electrodes. The top and bottom gates are self-connected during the poly-silicon deposition. The remaining steps are sourcddrain implantation, dopant activation annealing, contact opening and metallization. Fig. 2 shows the SEM photograph of the device. For comparison, conventional device is also fabricated using solid phase crystallization (SPC). The fabrication process is similar to that of MILC device, except that no nickel strip is placed prior to the crystallization process.

Device Characteristics Figs. 3a-3b and 4a-4b show the Id-Vd and the subthreshold characteristics of MILC GAT, together' with the

MILC SGT, SPC GAT and SGT, and the conventional SO1 devices for comparison. The measurements were taken from n-channel and p-channel devices. The channel length L, and width We are 0 . 5 5 p and 0.47pm respectively. It is observed that MILC single gate devices have the comparable performance as the conventional SO1 devices. Moreover, both GAT and SGT MILC devices have steeper subthreshold slope, lower V,, higher current drive, higher carrier mobility and higher breakdown voltage than SPC devices. In addition, compared to SGT, GAT device has higher cunent drive, steeper subthreshold slope and lower threshold voltage. With l2OA thick gate oxide and 8008, channel thickness, subthreshold slope of 68mV/dec and on/off ratio of 2x10' can be achieved by these GATS.

Figs. 5a-5b show the transconductance of various devices with respect to channel length Le. Undoubtedly, MILC device has lower interface-state and higher mobility, and thus leads to remarkably higher transconductance than that of SPC devices. Furthermore, GAT exhibits carrier volume inversion, which results in higher cmier mobility. This leads GAT to higher transconductance than that of SGT, especially in the low gate voltage region.

Figs. 6a-6b show the subthreshold slope of various devices. MILC device has superior subthreshold slope compared to SPC device. SPC device has subthreshold slope 250-500mV/dec. MILC GAT has subthreshold slope from 6.8 to 78mV/dec, and that of SGT is 75-85mVldec. The threshold voltage dependence on Lg is shown in Figs. 7a- 7b. SPC device has higher VI from 1.6 to 2.8V. MILC GAT has smaller VI, from 0.2 to 0.4V. The VI variation is also smaller compared to SGT. GAT has saturation current around 1.7 to 2.1 times higher than that of SGT.

Figs. 9-10 show the current drive and the threshold voltage of various devices with respect to channel width W,. Narrow channel effect decreases the threshold voltage and increases the current drive. GAT shows better narrow channel behavior as compared to SGT, as the current drive is more linear with respect to the channel width.

Figs. 8a-8b shows the current drive of various devices at IV,I=IV,1+2.5.

Conclusion High performance gate-all-around transistors have been demonstrated. Using this method, GAT devices can

be fabricated from either a single bulk wafer or on the top of any device layers. The conventional fabrication process is feasible. The devices provide better short-channel behavior, improved subthreshold slope and larger drive current. It is suitable forhigh performance, low voltage, low power arid memory applications.

0-7803-6389-2/00$10.00 02000 IEEE.

2000 IEEE International SO1 Conference, Oct. 2000

Hong Kong, SAR. References

[ I ] H.S.P. Wong et al . , IEUMTech. Dig.,Pg. 427-430, 1991 1'21 J . P. Colinge, et al . , IEDM Tech Die., Pg. 595, 1990 [31 '1'. Tanaka, et al., VLSl Tech. Symp.. Pg. 1 1 , 1994 [4] S . Maegawa,et al., Jpn.J.Appl. Phys.,vol,34,Pg. 895, 1995 15lS.Jaaaretai.,SOIConf.Uig.,Pg. 112-113,1999

I Fig. I gate-all-around transistors (GAT) schematic structure

Fig 2 SEM nucrograph of the GATdevices

- n , 0 , 2 3 O , I I < ' ". 1"I v, / V I

l'ie 3. ninos I-V curves of GAT and Stil ' , with SPC devices for comparison. LA.31=0.55/0.47pn. a) Id-V, & b) I d - V d curves

1 .I .A ., - 2 .I Y 1 . 2 . / 0 ". IW V I lyi

comparison. L/W=0.59/0.48pni. a) L-V, & b) Id-Vd curves Fig 4. prnor I-V curves of GAT arid SGT, with SPC devices for

I v: ( V I .' v* ( V I .7 .3 0

Fig 5 . Transconductance (SI,dSV,) at IV,,I=O.OSV, with SPC: devices for coinparison. a ) nmos arid b) pinos g,,, with UW=0.57/0.48pm.

65 65 6 0 7 - - r-~q 60 7- I ,1

0 1 2 LcmP 4 5 0 1 2 3 4 5 L 6 ~ 1

Fig 6. Subtlireshold slopc vs. clianriel length at IVd,I=0.05V for a) ninos and b) pmos devices, with W=0.48pm.

VI [VI nmaD . Single galo -Daublo O * l < 1 2 1

2Lbun)" 0 1

Fig 7. Threshold voltage vs. channel lengtti at IVd,I=O.OSV

b . t ! l t A l Ill,>". Id.., IPA1 /IrnO.

for a) ninos anti b) prnos devices, with W=0.48pni.

- *wLa W O .. .w p l r

20

0 1 2 3 4 5 0 , 1 3 , 1 LLll"') LLv"il

Pig 8. Saturation current vs. channel length at IV,,I=IV,Ii-2.SV for a) nnios and b) pmos devices, with W=0.48pm.

vt M m m . - . . Y n j e @ o NtlM pnx ' 0 Sn;le@ -- Wis @e . * " . ,, . . ...

,,,. I . . . 02 r

0.0 o 0.1 oz. 0.3 0.4 a5 0.6 0.7 0.8 o a i 0% a3 a4 a5 a6 a7 ati

W? w Fig 9. Threshold voltage vs. channel width at IVd,I=0.05V

for a) nnios and b) pmos devices, with L=O.S6jtrn. Idau ha1 Il l l iOl - muie y l l 0 '4.' PA) pmoa . - * i w e y l t o . l i n j 0 W'Y

0 0.1 0.2 o.."hdm,o.5 0.0 0.7 0.8

Fig IO. Saturation current vs. channel width at lV,,I=lV,l-1-2.5V for a) nmos iind b) pmos devices, with L,=0.56jtin.

o 0.1 0 2 0.3 0.4 0 5 0.6 0.7 0.8 W W )