A Novel Bias Temperature Instability Characterization Methodology for High-k MOSFETs

Dawei Heh, Gennadi Bersuker, Rino Choi, Chadwin D. Young, and aByoung Hun Lee

SEMATECH, 2706 Montopolis Drive, Austin, Texas 78741; aIBM assignee

Tel: 1-512-356-7663, Fax: 1-512-356-7640, E-mail: dawei.heh@sematech.org

Abstract

A characterization methodology based on a single pulse measurement for evaluating the bias temperature instability (BTI) of high-k devices has been developed. It is shown that the time dependence of the threshold voltage instability extracted from conventional DC and pulse Id-Vg measurements can be affected by the fast charge relaxation process leading to erroneous predictions of lifetime. The proposed methodology separates the relaxation effects associated with the fast transient and slower constant voltage charging and allows extracting the dependence of intrinsic threshold voltage on stress time. Introduction

Hafnium-based dielectrics have been demonstrated as promising candidates for advanced high-k gate stacks. However, it has been found that in high-k devices the measured threshold voltage instability (DVth) under bias temperature stress is strongly affected by the interruption time of the sense measurement, which may result in an inaccurate prediction of device lifetime. This Vth recovery has been attributed to the fast (µs range) charge relaxation (detrapping) process when the stress bias is removed [1, 2, 3]. Such fast relaxation raises questions about the validity of the conventional Vth monitoring methodology during BTI stresses.

To address the issue of charge relaxation during sense measurements, several approaches were implemented with varying success. In particular, monitoring drain current degradation during the stress, at Vg=Vstress [4], does not provide the Vth shift values directly, while sensing drain current in the linear Id regime is accompanied by switching delay as well as charge loss due to fast relaxation. The single pulse Id-Vg measurement technique [5,6] was developed to minimize trap charging/discharging due to short measurement times. It has also been applied to BTI studies [7]. However, as shown below, charge relaxation may still be observed during practically achievable pulse measurement times. In this work, a new analysis methodology based on the charge trapping/detrapping physical mechanism is

proposed. In this approach, the effect of charge relaxation on DVth could be eliminated regardless of stress interruption time. The intrinsic stress time dependence of DVth can be revealed by using this analysis methodology. Experiment

The nFETs used in this work are fabricated using a conventional CMOS process, including a 1000 °C dopant activation anneal, with 3 nm ALD HfO2/1 nm SiO2 gate dielectric and TiN electrode [8]. Results for devices with considerable charge trapping are presented here to illustrate the proposed methodology.

The experimental setup of the single pulse measurement is shown in Fig. 1. Fig. 2 shows the dependence of the drain current during the single pulse Id-Vg measurements on the pulse time: the

Fig. 1. Experiment setup of single pulse measurement. Id is calculated from DVout.

Vout

V in

Z O

VD D

D ig ital O SC Pulse

G enerator

Fig. 2. Comparison of Id-Vg characteristics measured at different pulse times and DC condition.

0.0 0.5 1.0 1.5 2.0

0

100

200

300

400

500

I d (µA)

Vg (V)

1 µs pulse3 ms pulseDC

Recovery from charge trapping

nMOSFET3nm HfO2/1nm SiO2

W/L = 10/1 µm

1-4244-0301-4/06/$20.00 ©2006 IEEE. 387

current recovery with shorter pulse times is due to less fast transient charge trapping. Fig. 3 shows diagrams of BTI characterization using conventional DC Id-Vg and single pulse Id-Vg methods. Results and Discussion

Single pulse Id-Vg curves before and during the stress are shown in Fig. 4. A hysteresis observed in the initial pulse Id-Vg curve is due to the fast transient charge trapping/detrapping. The most significant shift of the pulse Id-Vg curves occurred during the initial moments of stress. Hysteresis of Id-Vg curves measured during the stress is attributed to net charge relaxation during the pulse measurement. To study the charge relaxation effect on DVth during BTI stress, various total pulse times, from tenths of a second to one microsecond, were used in the single pulse measurements, as shown in Fig. 5. A significant difference in the hysteresis of the Id-Vg curves with different pulse times reflects the net result of the competing charge trapping and detrapping processes during pulse measurements resulting in a bell-shaped

curve of the hysteresis values vs. pulse time, as shown in Fig. 6. To study the effect of the stress interruption time on DVth, Vth values were extracted from the rising portion of the Id-Vg curves in Fig. 5 using a linear approximation method. Fig. 7 shows that DVth values increase with shorter pulse times due to less charge detrapping (relaxation). The DVth vs. stress time plots for different pulse times (including the DC measurement) are presented in Fig. 8. A consistent trend of smaller slopes of DVth dependency on the stress time with shorter sensing pulse times, accompanied by higher absolute values of DVth, is observed. The corresponding power law exponent values are plotted in Fig. 9. This data demonstrates that the power law exponent values are affected strongly by the stress interruption time (at least, down to 1 µs pulse time in this particular case) [9].

To eliminate the charge relaxation effect during pulse measurements, Vth values were extracted from the falling portion of the Id-Vg curves in Fig. 5 corresponding to the falling portion of the Vg

Fig. 3. Comparison of stress-sense time scales using DC and single pulse Id-Vg measurement.

STRESSInitialsense

Sense

STRESSInitialsense Sense

Vg

time

Vg

DC IdVg

Pulse IdVg

time

Stress bias

STRESS

Stress interruption timeStress time

Vg falling Vg rising

STRESSInitialsense

Sense

STRESSInitialsense Sense

Vg

time

Vg

DC IdVg

Pulse IdVg

time

Stress bias

STRESS

Stress interruption timeStress time

Vg falling Vg rising

Fig. 4. Comparison of single pulse Id-Vg curves before and after different stress times.

0.0 0.5 1.0 1.5 2.0

0

100

200

300

400

I d (µA)

Vg (V)

Initial 2 sec 200 sec 1500 sec 3000 sec

Stress voltage = 2VPulse time = 55 µs

Stress time

10-6 10-5 10-4 10-3 10-2 10-1 100

0.00

0.05

0.10

0.15

0.20

0.25

Hys

tere

sis

(V)

Pulse time (sec)

Stress voltage = 2V

Vg

IdHysteresis

Fig. 6. Hysteresis of single pulse Id-Vg curve shows net charge relaxation during measurement.

Fig. 5. Pulse Id-Vg curves measured after 1500-sec stress using different pulse times.

0.0 0.5 1.0 1.5 2.00

100

200

300

400

3.3ms 550ms

Vg falling

I d (µA)

Vg (V)

1µs 55µs

Vg rising

After 1500 sec stress@ 2V

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pulse (see Fig. 3), which does not include the pulse time delay, as shown in Fig. 10. However, the slopes of the DVth vs. stress time plots are similar to the corresponding plots in Fig. 8, which indicates that charge relaxation does not affect the slopes in Fig. 8 and 10. As follows from the pulse data in Fig. 4, after the initial moment of stress, DVth is dominated by fast transient charging. Therefore, the initial data point of each curve in Fig. 8 and 10 corresponds to the relaxation of the fast transient charges as shown in Fig. 11. To remove the contribution from the transient process, data in Fig. 8 and 10 are replotted by subtracting the DVth value of the first data point, as shown in Fig. 12. It demonstrates that for all pulse conditions the DVth data follow a similar stress time dependence. These results suggest that the major contribution to the pulse time dependence of the power law exponent comes from the relaxation of the fast transient charge. Note that the relative

positions of the parallel curves in Fig. 12 follow the same trend as the hysteresis values in Fig. 6.

The relaxation time dependence is further investigated by comparing the DVth of devices on which the sensing (stress interruption) was done in the linear and logarithm time scales. Data in Fig. 13 shows that the different total relaxation time introduced by sense measurements in linear and log time scales does not change the slope, which further confirms that charge relaxation does not affect the power low exponent values as observed in Fig. 8 and 10.

To explain fast transient charge trapping and charge relaxation mechanisms, a physical model was proposed [10], as shown in Fig. 14. It suggests that captured electrons are eventually localized in shallow traps (process A). This is a fast transient charging process, which is responsible for the hysteresis of the initial pulse Id-Vg curve (Fig. 4)

Fig. 8. Stress time dependence of DVth extracted from Vg rising measured at different pulse times

100 101 102 103

10-1

100

550ms

3.3ms

1µs

55µs

∆Vth

(V)

Stress time (sec)

DC

Vg rising pathStress voltage = 2VW/L = 10/1 µm

Fig. 9. Power law exponent values of DVth dependence on stress time at 25°C and 125°C

10-6 10-5 10-4 10-3 10-2 10-1 1000.00

0.02

0.04

0.06

0.08

Pow

er la

w e

xpon

ent n

Pulse time (sec)

Open symbol: 125CClosed symbol: 25C

∆Vth(t) ~ tn

nMOSFET3nm HfO2/1nm SiO2

W/L = 10/1 µm

Fig. 10. Stress time dependence of DVth extracted from Vg falling measured using different pulse times

100 101 102 103

10-1

100Stress voltage = 2V Vg falling path

∆Vth

(V)

Stress time (sec)

550ms

3.3ms

1µs

55µs

Fig. 7. DVth extracted from pulse Id-Vg curves measured using different pulse times

10-6 10-5 10-4 10-3 10-2 10-1 100 101

0.1

0.2

0.3

0.4∆V

th (V

)

Stress interruption time (sec)

Room temperature125 oC

After 1500sec stress @ 2V

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and causes a DVth jump at the beginning of a stress. The applied field then helps trapped charges hop into adjacent traps (process B) during BTI stress. When the stress bias is removed during sense measurements, the charges trapped through processes A and B may detrap differently, in particular, through back tunneling as with fast transient charges. By subtracting the first data point in Figs. 8 and 10, we have eliminated the contribution of fast transient charges to Vth relaxation. The relaxation of the remaining charges trapped through the process B is proportional to the amount of the trapped charge and, therefore, results in a parallel shift of the DVth curves for different pulse (relaxation) times, as shown in Fig. 12. Conclusion

The proposed analysis methodology during BTI for high-k devices separates the contribution to Vth relaxation from fast and slow charging processes. The intrinsic stress time dependence of ∆Vth is not

affected by interrupting the stress within the six decades of the interruption times. It is also shown that the intrinsic stress time dependence of ∆Vth in high-k devices could be extracted even from the conventional DC Id-Vg measurement results using this proposed analysis method. Reference [1] G. Bersuker et al., Microel. Reliab., 44, p.1509,

2004 [2] R. Choi et al., EDL, p. 197, 2005. [3] R. Choi et al., APL, p. 122901, 2005. [4] M. Denais et al., IEDM, p. 109, 2005. [5] C. D. Young et al., EDL, p. 586, 2005. [6] A. Kerber et al., IRPS Proc., p.41, 2003. [7] C. Shen et al., IEDM, p. 733, 2004. [8] J. Barnett et al., MRS, p. E1.4.1, 2004. [9] S. Mahapatra et al., IEDM, p. 105, 2004. [10] G. Bersuker et al., IRPS p. 179, 2006.

Fig. 11. Initial DVth shift measured at both Vg rising and falling paths.

10-6 10-5 10-4 10-3 10-2 10-1 1000.0

0.1

0.2

0.3

0.4

0.5∆V

th (V

)

Pulse time (sec)

Vg rising Vg falling

Measured after 2 sec stress@ 2V

Fig. 13. DVth measured using pulse and DC Id-Vg methods in different sense scales.

100 101 102 10310-2

10-1

100

Pulsed Id-Vg

∆Vth

(V)

Stress time (sec)

More frequent interruptionLess interruption

nMOSFET3nm HfO2/1nm SiO2

W/L = 10/1µm

Stress bias = 2 V

DC Id-Vg

Fig. 14. Proposed physical model explaining fast charge trapping and charge relaxation mechanisms.

GateGate

SiHigh-k SiO2

AB

GateGate

SiHigh-k SiO2

AB

Fig. 12. Intrinsic DVth dependence on time is obtained by removing the first data point in Fig. 8 and 10.

101 102 10310-3

10-2

10-1

∆Vth

(V)

Stress time (sec)

1µs 55µs 3.3ms 550ms DC

Open symbol: Vg fallingClosed symbol: Vg rising

∆Vth(t)=Vth(t)-Vth(t=2)

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