An Approach to the Central Control Part of Digital Satellite ReceiverBased on Pervasive Computing

Zhuoyun Zhang, Chunping Hou, Yonghong Hou, Yanlong ZhangTianjin University, Tianjin, P. R. China

Zhuoyun_tiu@ghotmail. comr, hcpg@tu. edu. cn

Abstract

Pervasive computing enables people to obtain allkinds of information at any time and place. In thispaper, considering the embedded device which is thekey technology of the pervasive computing, it uses theNios II embedded soft core processor to realize thecentral control part of digital satellite receiver.Utilizing the hardware customized characteristic ofNios II, this paper promotes a central control scheme ofthe digital satellite receiver which has the desire of thehigher reliability, the lower cost and the smaller volume.

Keywords: Pervasive Computing, The Nios II

Processor, the Satellite Receiver, AD6654.

1. Introduction

Embedded computing device is the key technologyof the pervasive computing. It includes embeddedprocessor, peripherals, embedded operating system andspecial application programs. It also integrates thehardware and software. Nowadays, pervasivecomputing aims at developing smaller and more

powerful embedded system, and realizing the strongerperformance.

This design of the central part of the digital satellitereceiver is based on the pervasive computing. Thedesign method with Nios 11 has the pervasive applicablevalue. It can reduce the interfaces of FPGA and realizethe highly-integrated goal if embedding the Nios II softprocessor into the digital satellite receiver and usingNios II as the central processor. It integrates theperipheral logics into the CPU and adds modules ofdecoding and deinterlacing into FPGA. Because theNios II processor has low cost and is easy to expandand upgrade, it can improve the cost performance andmake the system expandable and flexible.

In this design, we use the 32-bit Nios II processor as

the core of on-chip structure to control the entirereceiver. It can provide the changeable clock and every

kind of control signals for the whole system, realize thedata inter-transmission and configure the special chipAD6654. It debugs via the ByteBlaster II downloading

cable. If the Nios II system is downloaded to Flashsuccessfully, it will run automatically after resetting.

The Nios II processor is a RISC processor core, itsmain characteristics are as follows:

(1) CPU structure: full 32-bit instruction set, datapath, address space, 32 general-purpose registers and 32general-purpose registers.

(2) On-chip debug: the debug logic based on theJTAG boundary scan testing, support hardware breakpoint, data triggering and on-chip or off-chip debuggingand tailing.

(3) Customize instruction: up to 256 customerdefined CPU instructions.

(4) Software development environment: Nios 11 IDE,based on the GNU C/C++ tool chain, the hardware-assisted debug module.

(5) Configurable peripherals: up to 60 peripheralsincluding USB, the memory controller .etc.

(6) Instruction set architecture (ISA) is compatiblewith all Nios II processor.

(7) Performance beyond 150 DMIPS.The Nios II processor represents the Nios II

processor core, a group of on-chip peripherals, on-chipmemories and off-chip memory interfaces. It is muchlike a processor family that all the Nios II processor

systems use the fixed instruction set and coding modes.[1].

2. The hardware design of the system basedon the Nios II processor

As in Figure 1, the satellite receiver system uses

analog receiver to receive data, and AD6654 to realize14-bit AD sample of the fixed frequency point which iscontrolled by Nios II via SPI interface, so it can fulfillthe digital down-converting function; AD6654 can

transmit the processed data to Cyclone II in order todecode and deinterlace. After processing, it can triggerthe interrupt of Nios II via PIO, put data in paths of Iand Q to it, and store the data in SDRAM. [2]. Nios II

can also inter-transmit data with PC via UART interface.The hardware configuration and software controlling

program of Nios II can write to Flash via Tristatebridge. After resetting, the system can read data fromFPGA and run the system.

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Figure 1. The Nios II processor configurationtheory figure

2.1. The Nios IL processor configuration

In this design, we choose the Nios II /f. When SOPCBuilder generates a processor, it has to finish the followprocedures: configuring CPU hardware, addingperipherals, define the processor start address, settingthe memory of the instructions. After adding thecorresponding interface modules in SOPC Builder, itcan generate the Verilog HDL file. According to thecustomized results, it generates the head files andfunction libraries in C and assemble language accordingto the special hardware environment.

2.2. The inter-transmission with PC via UARTin Nios II

UART means universal asynchronousreceiver/transmitter. It can be used to control the PCand the serial devices. It provides the RS-232C dataterminal device interface, and realizes thecommunication between the PC and serial deviceswhich have the RS-232C interface.UART synchronizes the received data using exterior

clock, which can be obtained from crystal oscillator or

the system clock. It always sets a parity check bit.In this system, the Nios II communicates with PC

via UART. It can add UART interface in SOPC Builder.According to the system need, it has to set: transmit rate,data bits, parity and stop bits.

After setting the Nios II system, it has to do thesame thing in PC. This set will be down in hyperterminal.We should notice that the parameters will be the

same in both PC and Nios II system.

2.3. Controlling AD6654 via SPI in Nios II

In this design, it uses AD6654 to realize the digitaldown-converting and 14-bit AD sampling. The functionfigure ofAD6654 is shown in Figure 2.

Figure 2. AD6654 function theory figure

In Figure 2, the control of AD sampling, NCOfrequency, the filter exponents of CIC,DRC,CRC inAD6654 will all be realized in Nios II via SPI.

SPI means serial peripheral interface. SPI is a highspeed, full-duplex, synchronous communication bus. Itonly uses four pins of the chip, so it saves the pins andthe space of the PCB. According to these characteristics,the SPI bus is used to control AD6654 to implement thefunction. The interface of Nios II and AD6654 via SPIis shown in Figure 3.

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The SPI logic is synchronous to the clock inputprovided by the Avalon interface. When configured as a

master, the SPI core divides the Avalon clock togenerate the SCLK output. [4].

The hardware feature and the timing settings are

configured in SOPC Builder SPI core configurationwizard. The timing settings of the SPI core must bematched with that of AD6654.

In SPI mode, the write timing of AD6654 is shownin Figure 4. We have to configure the SPI parametersaccording to the timing characteristics and writeinstructions according to the AD6654 protocol. Afterthat we can configure AD6654 successfully.

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underlying hardware. The API is integrated with theANSI C standard library. The HAL API allows us toaccess devices and files using familiar C libraryfunctions. [5].

The software design of this system is mainly aimingat the UART and the SPI core. The system flow chart isshown in Figure 5.

4. Interrupt control of Nios II system

Figure 4. AD6654 timing figure in SPI writing mode

3. The system software design based on

Nios II

The software design ofNios II system is as follows:(1) Edit C/C++ source code in Nios II IDE

development environment and compile the source

code to generate the executable code.(2) After debugging the executable code, store the elf

file to flash memory and ordain the file initializeRAM. Then the Nios II will execute the program

automatically after resetting the CPU.

Figure 5. The software flow chart of digitalsatellite receiver

After customizing the Nios II hardware system inSOPC Builder, it generates the head files in C andassembling language automatically. Whenprogramming, we can use both the ANSI C standardlibrary and the application program interface (API)provided by hardware abstraction layer (HAL). TheHAL system library is a lightweight runtimeenvironment that provides a simple device driverinterface for programs to communicate with the

The PIO core can be configured to generate interruptif there is special input. In this system, the Nios II can

implement the interrupt control because of thischaracteristic. The theory figure is shown in Figure 6.

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Figure 6. The Nios IL interrupt control theory figure

After processing system data, the PIO core can

generate interrupt when the special triggering conditionhappens. Then it can transmit data to Nios II CPU viathe PIO interface. Having identified the instructions, theNios II can configure AD6654 and realize the inter-transmission with PC.

5. Comparisons

We also design a system of the central control partwithout Nios II processor. The resources occupied inFPGA are 20 percent larger. In addition, we have muchdifficult in controlling AD6654 effectively andupgrading the performance ofthe system.

6. Conclusions

In this design, the digital satellite receiver based on

the Nios II processor can fulfill the effective control tothe central device AD6654 which can sample at thefixed frequency point and implement the digital down-converting. The receiver can also transmit data with PC.

The Nios II processor is flexible and customized, so

it can shorten the development period, reduce the debugprocess, and achieve the performance of the system.

Acknowledgement

The following individuals have contributed to thiswork:

Di Sun, Liqiang Zhang, Yicai Ying.

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References[1] Nios II Processor Reference Handbook. Altera, 2005.15 20.[2]K4S641632H-TC(L)70 SDRAM datasheet. SumsungElectronics, 2004.3-11.[3] AD6654 Data Sheet. Analog Devices, 2005. 1-17.[4] Altera Embedded Peripherals Handbook. Altera, 2005.93 107.

[5] Nios II Software Developer's Handbook. Altera, 2005. 33-55[6] Zhuo Fang, Chenglian Peng, Zewen Chen. "SOPC designbased on the Nios II ". Computer project and design.2004,25(4).[7] Song Pan, Jiye Huang. SOPC technology tutorial.Beiing,2005.