A High Band Impulse Radio UWB Transmitter for Communication and Localization

Denys Martynenko, Gunter Fischer, Oleksiy Klymenko Dept. Circuit Design

IHP GmbH Frankfurt Oder, Germany

gfischer@ihp-microelectronics.com

Abstract— This paper describes a monolithic integrated transmitter intended for impulse radio (IR) Ultra-wide band (UWB) applications including indoor communication and indoor localization. The transmitter operates in the higher UWB band centered at 7.68 GHz and it is optimized for a pulse bandwidth of about 1.5 GHz. The transmitter generates single pulses with a repetition rate of 60 MHz and utilizes pulse position modulation (8-PPM) for data communication. A dedicated time-of-arrival (TOA) measurement extension supports precise indoor localization in conjunction with an appropriate UWB receiver. The demonstrated spatial ranging resolution is about 3.9 centimeter under line-of-sight conditions.

Ultra wideband; impulse radio transmitter; indoor localization

I. INTRODUCTION Impulse Radio Ultra-Wide Band systems became recently

attractive for wireless short range, low power applications since the Federal Communication Commission (FCC) has allowed to use of the frequency band between 3.1 and 10.6 GHz. A bandwidth of at least 500 MHz and the utilization of the IR approach open the door to new applications on civil RF systems, such as localization and data communication employing the same RF components.

Many of the recently published transmitters were designed as fully digital [1], [2] or mixed analog/digital [3], [4] circuits. The fully digital solution has a flexible pulse shape control and is less sensitive to the process or temperature variations. However, most of them are adopted for their use in the low UWB band, which lies between 3.1 and 5.1 GHz. Furthermore, fully digital designs have a complex circuitry realization. The mentioned mixed analog/digital solutions above are neither fully integrated on the chip, nor have a localization ability.

This work presents a fully integrated differential transmitter for high UWB band with a center frequency of 7.68 GHz and a 1.5 GHz pulse bandwidth. The pulse generator utilizes 3 bit of pulse position modulation (8-PPM) and an optional pulse amplitude modulation (PAM). Together with the corresponding receiver presented in [5], the transmitter provides precise time-of-arrival measurements with a time resolution of 260 ps (spatial resolution 7.8 cm).

II. UWB TRANSMITTER ARCHITECTURE

TOA PLL

Comparator(from Reciever)

VGA LPF PG

DAC4 bit

TOA7 bit

Output UWBsignal

TOT TOT3 bit

CrystalOscillator

Fig. 1. UWB transmitter block diagram

Fig. 1 shows the block diagram of the implemented UWB transmitter architecture. It includes the following major components: a phase locked loop (PLL), a TOA logic, a time-of-transmission (TOT) logic which is connected to the pulse generator (PG), a low pass filter (LPF), a variable gain amplifier (VGA), an up conversion mixer, and a passive transformer. Additional external components are crystal oscillator as reference clock of the PLL, and a 4-bit digital to analog converter (DAC) controlling the VGA.

The basic block of the transmitter is an integer-N PLL. It provides the local oscillator (LO) signal with a frequency of 7.68 GHz used as carrier for the up conversion mixer as well as the system clock of 3.84 GHz for the TOT logic. The external reference is 60 MHz. The PLL divider chain is implemented as a synchronous counter to provide additional signals for the 3 bit PPM (TOT). Furthermore, the counter builds the time basis of the TOA measurement extension. The high system clock allows a time measurement accuracy of 260 ps which is essential for precise ranging and localization accuracy. The PG produces digital pulses (duration of 260 ps), which are then shaped by the LPF in order to meet the FCC spectral requirements for UWB. The implemented VGA is used to enable PAM. The up-conversion mixer converts the shaped impulses into the higher UWB frequency band. Finally, the passive transformer ensures output impedance matching to 50 Ohm as well as the differential to single ended conversion.

This work was supported in part by the Commission of the European Union in scope of the Integrated Project PULSERS Phase II.

ICUWB 2009 (September 9-11, 2009)

9781-4244-2931-8/09/$25.00 ©2009 IEEE 359

III. UWB TRANSMITTER COMPONENTS DESIGN

A. Phase locked loop The PLL is implemented as a conventional integer-N PLL

and consists of a voltage controlled oscillator (VCO), a frequency divider with the fix division ratio of 128, a phase frequency detector (PFD), a charge pump (CP), a passive loop filter and a reference crystal oscillator.

B. VCO design The VCO phase noise performances are generally defined

by the resonator quality factor, the oscillator architecture and the power consumption. This can be easily foreseeing from the Leeson equation [6]. At the same time, the Leeson equation shows that increasing the tank quality factor and the VCO power consumption will decrease the phase noise. Thus, the optimization of the passive oscillator components, like the inductor and varactor, as well as the active components like cross coupled pair is necessary to obtain low phase noise VCO design. The coil is implemented as two turn fully differential spiral inductor. The windings are designed from the thick top alumina metal layer and have 21 μm of width. Simulations give an inductance of around 1 nH and a maximum quality factor of roughly 20 at frequencies between 7.4 and 7.8 GHz. Moreover, the chosen inductor structure offers a good compromise between the quality factor and occupied area. The varactor and cross coupled pair design optimization is done similar to [7]. The simulated varactor quality factor varies with the tuning voltage between 28 and 12 at the frequency of 7.68 GHz.

The PLL dynamic characteristic strongly depends on the VCO gain (KVCO). For instance, to minimize PLL settling time (preferable to minimize average transmitter power consumption), the KVCO needs to be maximized. On the other hand, a high KVCO will have a negative influence on the oscillator phase noise. Therefore, a compromise between the PLL locking time and phase noise needs to be found. In this design, KVCO is chosen to be 400 MHz/V resulting in a settling time less than 5 μs for 1ppm frequency accuracy. Furthermore, the achieved VCO tuning range of about 900 MHz covers all potential process, voltage and temperature variations.

V tune

Vdd

Fig. 2. VCO circuit diagram

The presented transmitter is designed in the 0.25 μm BiCMOS process offered by IHP [8]. Thus, both the bipolar and the CMOS oscillator configuration would be possible. For this VCO, the CMOS solution is chosen due to its larger output voltage swing compared with the bipolar version. While in the bipolar configuration the voltage swing is limited by the saturation condition [9], here the implemented CMOS oscillator can reach the full swing of 2.5 V.

The VCO circuit diagram is shown in Fig. 2. It consists of complementary cross-coupled differential nMOS and pMOS pairs, an LC tank which is created by a symmetrical inductor and an accumulation mode varactor.

C. Divider design Besides the VCO, the frequency divider is an interesting

block regarding its design too. It is implemented as a synchronous frequency counter with a clock frequency of 3.84 GHz. Such a high clock is required to reach the necessary timing accuracy in the TOA and TOT logic. Consequently, this block has a complex design and causes high power dissipation in the transmitter. Fig. 3 shows the two last stages of the six-stage counter. The synchronous counter was designed using the fast ECL logic library offered by the IHP [8]. Further design and implementation issues of this counter are described in detail in [10].

&

1 D

CLK

Q

QTrigger

C1...C4

C5

1 D

CLK

Q

QTrigger

C1...C5

C6

...

CLK 3.84 GHz

&

Fig. 3. Last two dividing stages of the frequency counter

D. Phase frequency detector, charge pump and loop filter The PFD is designed similar to [11], and consists of two D

flip-flops and a delay cell in order to avoid the dead zone phenomena [12]. The PFD continuously compares the reference and the divider output signals and produces UP or DOWN impulses according to their difference. Those impulses drive the CP current sources. The loop filter transforms the CP current impulses into a DC voltage controlling the varactor in the VCO resonance circuit. The CP utilizes cascode current sources in cooperation with steering switches [13]. The loop filter includes an extra low pass filter for additional reference spur reduction. A high PLL bandwidth provides a good VCO phase noise suppression and fast PLL settling.

The measured PLL phase noise performance is shown in Fig. 4. The PLL bandwidth of 1.5 MHz is chosen as a trade-off between phase noise, settling time and spurs level. The expected PLL settling time is around 4 μs for 1ppm frequency accuracy and the phase noise is -96dBc/Hz at 1MHz offset.

360

1k 10k 100k 1M 10M-160

-140

-120

-100

-80

-60

-40

-20

Pha

se n

oise

, dB

c/H

z

Frequency offset, Hz 1k 10k 100k 1M 10M-160

-140

-120

-100

-80

-60

-40

-20

PLL phase noise

VCO phase noise

Fig. 4. Phase noise of the free running VCO and locked VCO

E. Time-of-transmission logic and pulse generator The PG together with TOT logic provides a train of single

pulses (duration of 260ps) with an average pulse repetition frequency (PRF) of 60 MHz. The 3 bit control of the TOT logic allows to modulate the pulse train with 8-PPM. Theoretically, this allows obtaining a data rate communication up to 180 Mbit/s. In practice, the implemented transmitter is dedicated for wireless sensor network applications in industrial and logistics environments [14], [15]. For this application the user data rate is set to 1Mbit/sec, where the margin to the theoretical limit is employed for uncoordinated multi-user operation.

The baseband processor runs with a clock of 120 MHz and is not able to directly trigger the transmission of single pulses with the needed time resolution of about 260 ps. Thus, a fast logic block depicted in Fig. 5 has been implemented on chip using differential ECL. This logic selects 1 of 64 potential time slots and generates one impulse, where the 3 LSBs are fix and the 3 MSBs are set by the baseband processor. This construction ensures a time-of-transmission accuracy of 260 ps which is important for the overall ranging and localization accuracy.

C1

C2

C3

C4 C5 C6

TOT_EN TOT0 TOT1 TOT2

Impulse

C5

C6

>=1

>=1

>=1 >=1 >=1 >=1

>=1

>=1

>=1

>=1

=1 =1 =1

>=1

Fig. 5. Pulse release logic including time-of-transmission setting

F. Low pass filter and variable gain amplifier design The pulse shaping is implemented using a passive

differential 4th order Bessel filter. The relatively high corner frequency allows the use of a passive solution, where a stacked

inductor structure makes the layout size reasonable for the implementation on chip. Simulations including parasitic components show a corner frequency of 763 MHz and the expected linear group delay. Additional design and implementation issues of this LPF are described in detail in [5]. The VGA allows a PAM modulation and is implemented like a conventional Gilbert cell structure with differential control inputs [16]. External DAC is used in order to set the amplitude levels.

G. Up conversion mixer and output transformer design A mixer with current injection [17] is implemented in the

presented transmitter in order to up convert shaped impulses into the high UWB band. Such mixer architecture allows to improve the gain and the linearity of the mixing stage compared to conventional Gilbert cell solutions. Furthermore, the mixer topology with current injection was used to reduce the LO feedthrough at the output of the mixing stage. This reduction is important in direct up conversion transmitter architectures which was chosen in this work.

The output transformer is implemented as a stacked structure with two thick top metal layers. It provides the transformation of the mixer output impedance to the 50 Ohm antenna input impedance at frequencies between 6.9 and 8.5 GHz. The voltage standing wave ratio (VSWR) is kept ≤ 2 for the entire band. The winding ratio of the transformer is 4 to 2.

H. Time-of-arrival logic design The TOA measurement is performed by an extension of the

receiver and transmitter shown in Fig. 6.

TOA

COMP... DAC SPI

PLL Reg0

Reg1

...

MUX

Reciever

Transmitter

SPI

control

TOA

7 bit

Fig. 6. The TOA logic block diagram

CLK_60 MHz

Counter [0:6]

Reg0

Comp_In

Reg1

TOA [0:6]

Event A Event B

Counter at "A" Counter at "B"

Counter at "A" Counter at "B"

tres

tres

Fig. 7. Example of the TOA measurement timing diagram (tres – register reset time)

361

The receiver extension contains a fast comparator which

continuously compares the received signal with a threshold level (set by the baseband processor through the SPI and DAC). If the received signal exceeds the threshold, the comparator generates a trigger signal for the TOA block feeded into the transmitter. When signal appears at the TOA input, then the current counter content will be stored in one of the two registers (Reg0 or Reg1). Afterwards, the logic will be locked (ignoring additional trigger events) in order to prevent the registers from overwriting which may caused by multi-path reflections or high noise level at the receiver input. For better understanding of the functionality of the TOA measurement system a sample timing diagram is shown in Fig. 7.

This type of self-locking described above needs a release after a certain time. Every 8.3 ns the logic will be reset, which corresponds to the system clock of the baseband processor (120 MHz). In order to prevent any losses of trigger events two registers are implemented, where one is sensitive to trigger events while the other one stores the captured result of the previous time frame. Every 8.3 ns they toggle their operation mode. In storage mode the register content is delivered to the digital interface via a 2-to-1 multiplex block and reset shortly before it turns into the sensitive mode again. In addition, the storage mode allows the baseband processor to read the captured data with its own clock.

The described procedure reveals that every 8.3ns the leading edge of one event can be captured. This fits well to the proposed data communication where the average pulse repetition rate is set to 16.7 ns. In conjunction with the communication branch of the system the TOA extension acts as a high-resolution add-on providing precise time information within the frame of a single cycle of the baseband processor.

IV. MEASUREMENT RESULTS Fig. 8 shows a chip photograph of the presented impulse

radio UWB transmitter. The transmitter was fabricated using a 0.25µm SiGe:C BiCMOS technology of the IHP [8].

Fig. 9 shows different transmitter output measurement results in time and frequency domains. The output amplitude is around 200 mVpp, while the LO feed-through is less than -48 dBm.

Ranging measurement results of the entire demonstrator involving the presented transmitter are shown in Fig. 10. The first picture (a) shows the time plot of a continuous range measurement between two nodes, whereas the distance was changed during the measurement between two steady positions. Note that the variations at the steady positions are very small and there is no visible drift. The second picture (b) shows a histogram of the measured ranges at the second position. The size of one bin is about 3.9 cm. This measurement shows the resolution of the entire demonstrator under almost ideal line-of-sight (LOS) conditions over a short distance. By taking these measurement conditions the best ranging performance could be achieved. Under realistic conditions, taking into account multi-user interference, NLOS channel conditions and maximum radio link distance, the ranging performance will drop. Such field tests are not done yet and will be published later.

Fig. 8. Die photograph of the IR-UWB transmitter (chip area 2.5 x 2.0 mm2)

(a)

(b)

Fig. 9. Measurements of the transmitter output: a) Example of the pulse sequence with PPM; b) Output spectre with constant pulse rate without PPM

V. CONCLUSION Table 1 summarizes the overall performance of the

presented high-band impulse radio transmitter. It has been designed and fabricated in 0.25 µm SiGe:C BiCMOS technology of the IHP. The transmitter incorporated in a demonstration platform in conjunction with a corresponding UWB receiver fabricated with the same technology. The demonstration of the performance of the entire system shows a ranging accuracy of about 3.9 cm under best LOS conditions.

The presented results are first measurements and show the hardware capabilities in terms of high-precision ranging. Further work is needed to fully demonstrate localization involving a number of nodes in a real test environment. Concerning the presented transmitter future research is focused on decreasing the power consumption in active mode and the introduction of sleep modes to minimize the average power dissipation.

362

(a)

(b)

Fig. 10. TOA measurement results: a) demonstrates continuously ranging measurements between two nodes including a distance change; b) histogram of ranging results with narrow distribution confirms system stability and high accuracy

TABLE I TRANSMITTER PERFORMANCE

Chip size 2.5x2.0 μm2

Operation frequency 7.68 GHz Bandwidth 1.5 GHz Pulse repetition frequency 60 MHz Modulation 8 – PPM, PAM (optional) TOA resolution 260 ps Pulse amplitude 200 mVpp Supply voltage 2.5 V Total power consumption: TOA and TOT logic PLL(w/o divider chain), VGA and Mixer

413 mW 334 mW 79 mW

LO feed- through - 48.35 dBm

ACKNOWLEDGMENT The work presented was carried out within the European

research project PULSERS Phase II which is partly funded by the Commission of the European Union under the 6th European Framework Programme for Research and Technological Development (FP6) and here under the Information Society and Technology (IST) research programme.

Moreover, we would like to thank cordially all project partners for their helpful discussions and valuable contributions. In particular, we would like to thank our partners from IMST, Sennheiser electronics, and EADS for the excellent collaboration during the project and afterwards.

Finally, the authors acknowledge Dr. Valentyn Solomko and A. Veronica Vargas A. for their help during the paper preparation.

REFERENCES

[1] P.P. Mercier, D.C. Daly, A.P. Chandrakasan, “A 19pJ/pulse UWB transmitter with dual capacitively-coupled digital power amplifiers,” Radio Frequency Integrated Circuits Symposium, IEEE June 17 2008-April 17 2008 Page(s):47 – 50

[2] T. Norimatsu, R. Fujiwara, M. Kokubo, M. Miyazaki, A. Maeki, Y. Ogata, S. Kobayashi, N. Koshizuka, K. Sakamura, “A UWB-IR Transmitter With Digitally Controlled Pulse Generator,” Solid-State Circuits, IEEE Journal, Vol. 42, Issue 6, June 2007 Page(s):1300 – 1309

[3] A. Jha, R. Gharpurey, P. Kinget, “A 3 to 5-GHz UWB pulse radio transmitter in 90nm CMOS,” Radio Frequency Integrated Circuits Symposium, IEEE June 17, April 17 2008 Page(s):35 – 38

[4] O. Werther, M. Cavin, A. Schneider, R. Renninger, B. Liang, L. Bu, Y. Jin, J. Marcincavage, “A Fully Integrated 14-Band 3.1-to-10.6GHz 0.13um SiGe BiCMOS UWB RF Transceiver,” Solid-State Circuits Conference, IEEE International, Feb. 2008 Page(s):122 – 601

[5] O. Klymenko, G. Fischer, D. Martynenko, “A High Band Non-Coherent Impulse Radio UWB Receiver,” Ultra-Wideband, IEEE International Conference 10-12 Sept. 2008 Vol. 3, On page(s): 25-29

[6] J. Maget, “Varactors and inductors for integrated circuit in standard MOS technologies,” Doktor-Ingenieur thesis, Munich, 2002

[7] C. Changhua and K. O. Kenneth, “Millimeter-Wave Voltage-Controlled Oscillators in 0,13-um CMOS Technology,” IEEE J. Solid-State Circuit, vol. 41, No. 6, June 2006

[8] Foundry Service of IHP, Available: http://www.ihp-microelectronics.com/12.0.html

[9] D. Wang, X. Wang, “The performance comparison of CMOS vs bipolar VCO in SiGe BiCMOS technology” Microwave Symposium Digest, 2003 IEEE MTT-S International, 8-13 June 2003, Volume 1, On page(s): A101- A104

[10] G. Fischer, O. Klymenko, D. Martynenko, “Time-of-Arrival Measurement Extension to a Non-Coherent Impulse Radio UWB Transceiver,” Positioning, Navigation and Communication, 5th Workshop, March 2008. On page(s): 265-270

[11] S. Sinha, “Design of an integrated CMOS PLL frequency synthesizer,” Electrotechnical Conference, MELECON 2002. 11th Mediterranean 7-9 May 2002 Page(s):220 – 224

[12] D. Mandal, T. K. Bhattacharyya “Implementation of CMOS Low-power Integer-N Frequency Synthesizer for SOC Design,” Jornal of Computers, Vol.3 NO. 4, April 2008

[13] W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked loops,” ISCAS, Vol. 2, 30 May-2 June 1999 Page(s):545 – 548

[14] H. Luediger, B. Kull, M. D. Perez-Guirao, “An ultra-wideband approach towards autonomous radio control and positioning systems in manufacturing & logistics processes” in Proc. 4th Workshop on Positioning, Navigation and Communication 2007, Hannoversche Beiträge zur Nachrichtentechnik, vol. 0.4, pp. 291-296

[15] M. D. Perez-Giurao, K. Jobmann, “Cognitive resource access scheme for IR-UWB autonomous networks” in Proc. 4th Workshop on Positioning, Navigation and Communication 2007, Hannoversche Beiträge zur Nachrichtentechnik, vol. 0.4, pp. 267-272

[16] C. Wu; C. Liu; S. Liu, “ A 2 GHz CMOS variable-gain amplifier with 50 dB linear-in-magnitude controlled gain range for 10GBase-LX4 Ethernet” Solid-State Circuits Conference. Digest of Technical Papers. Vol.1, Feb. 2004 Page(s): 484 - 541

[17] L.A. NacEachern, T. Manku, “A charge-injection method for Gilbert cell biasing,” Electrical and Computer Engineering, IEEE Canadian Conference, Vol. 1, 24-28 May 1998 Page(s):365 - 368

363