Design of A 26GHz Phase-Locked Frequency Synthesizer in 0.13um CMOS

Chen Yueyang, Zhong Shun’an, Dang Hua （Department of Electronic Engineering, School of Information Science and

Technology, Beijing Institute of Technology, Beijing 10081, China）

Abstract

A 26GHz Phase-Locked Frequency Synthesizer in 0.13um CMOS process is designed. This frequency synthesizer generates quadrature outputs at 26GHz. The PLL utilizing a QVCO with tuning range from 23.75GHz to 28.25GHz can be locked from 24GHz to 28GHz. The power consumption of the circuit is 34mW with a power supply of 1.2V. The phase noise of the QVCO is -95dBc/Hz at 1MHz offset and the Q-mismatch is 1.7°. Circuits are simulated by Cadence Spectre in 0.13μm Standard CMOS Process. Key words: Phase-locked loop, frequency synthesizer, high-speed, CMOS 1．Introduction

A phase-locked loop(PLL) is a control sy- stem that generates a signal that has a fixed relation to the phase of a "reference" signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signals, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase.A phase-locked loop is an example of a control system using negative feedback.

Phase-locked loops have been widely used in radio,telecommunications,computersand other electronic applications. They may generate stable frequencies[1], recover a signal from a noisy communication channel, or distribute clock timing pulses[2] in digital logic designs such as microprocessors.Since a single inte- grated circuit can provide a complete phase- locked-loop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a cycle per second up to many gigahertz[3-5].

High-Speed communication integrated circuit design has been one of the most challenging areas nowadays. The limit of current fabrication process and the increasing demands for higher and higher data rate have always been a pair of conflicts which embarrassed designers with more issues to take into consideration when designing the

circuits. This work proposed the design of a PLL frequency synthesizer generating high-frequency clock signal of 26GHz from an input reference clock of 812.5MHz in 0.13μm standard CMOS process.

2．Phase-Frequency Detector

The conventional charge pump PLL Explicitly discussed in many publications, although widely used in most designs, suffers from long settling time, narrower acquisition range. In order to eliminate the defects of the traditional charge pump, an additional frequency detector (FD) can be employed to compare the frequency difference and generate a proportional dc output which is finally applied in the feedback loop with the output of the phase detector (PD), as shown below in figure 1[1]. The diagram of the PLL system is also shown here.

Fig. 1 Diagram of the PLL system

Here the PD and voltage-current converter was incorporated in one circuit, as shown below[1].

Fig. 2 Schematic of the Phase Detector and the

Voltage-current converter

2009 International Conference on Communications and Mobile Computing

978-0-7695-3501-2/09 $25.00 © 2009 IEEE

DOI 10.1109/CMC.2009.213

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2009 International Conference on Communications and Mobile Computing

978-0-7695-3501-2/09 $25.00 © 2009 IEEE

DOI 10.1109/CMC.2009.213

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In the above figure, the input is quadrature signal from the output of frequency divider.

1 3dnI I I= + （1）

2 4upI I I= + （2）

Now we consider the timing of fig. 2. If iCK and qCK come early than refCK ,or iCK and qCK lead refCK ,

then the phase difference 0φΔ > , the pulse width of upI

is wider than dnI and therefore 0OUTI > . For the case when iCK and qCK come later than refCK , or iCK and qCK

lag refCK , the phase difference 0φΔ > , the pulse width of upI is narrower than dnI and therefore 0OUTI < .

3．Voltage-Controlled Oscillator

The voltage-Controlled Oscillator is design- ed to generate quadrature output signal at 26GHz. Three conventional design options are available to generate quadrature signals: (1)Combination of VCO, poly-phase filter (or R-C filter); (2) VCO at double frequency fol- lowed by master-slave D flip-flops which can generate the quadrature signal; (3)Two cross- coupled VCOs. This topology is also named as Q-VCO. The first option needs four output buffers consuming more power. The second choice, in order to have a frequency range of 24GHz to 28GHz, requires the VCO to work with a tuning range from 48GHz to 56GHz which is probably impossible. The third option provide a more precise quadrature output waveforms along with a very high voltage swing which eases the design of the frequency divider. However, it comes with the problem that it costs double VCO areas. The QVCO topology is shown in Fig.3. Several design issues should also be addressed here.

3.1．Varactor

The LC-QVCO adjusts its oscillation frequency by changing the voltage across the varactor which is implemented using NMOS transistor connecting source and drain together. In order to obtain a wider tuning range, Cmax should be increased and Cmin be decreased. The conclusion here is Cmax increases proportionally to the product of W and L, and Cmin decreases when L is increased. Therefore, the minimum channel length for the MOS varactor should not be used and for a given length, the width is determined by the oscillation frequency. Furthermore, the overall capacitance loading the tank should be minimized as low as possible.

Fig. 3 Schematic of the Q-VCO

3.2．PMOS current source

Instead of using NMOS current source for the VCO, a PMOS counterpart is used here which enables the modulation of drain voltage by changing the varactor bias voltage. The use of PMOS current source allows utilization of the full range of the varactor without requiring tuning voltages above Vdd. 3.3．Output buffer

To isolate the QVCO and following frequency divider, a buffer is inserted between the output of the QVCO and the input of the first-stage frequency divider. Furthermore, the buffer should be carefully designed, because 1) to lower the parasitic capacitors loading on the tank, the transistor size used as the buffer should be small; 2) to get enough output swing, the buffer should provide enough gain. Due to the above two issues, two stages buffer is used in this design. As for the first stage, the input transistor’s W/L equals to 5 and the gain is mainly provided by the second stage. Another concern here is that each stage is actually a narrow band tuned amplifier with a Q value around 9.5. Therefore, the self oscillation frequency of the tuned amplifier should be in the neighbor of the VCO output frequency.

4．Frequency Divider

A conventional DFF based frequency divider widely used in broadband communication systems is shown in Fig. 4. Compared to the LC topology based Injection-locked frequency divider (ILFD), this divider

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has a much wider locking range but with a lower operation frequency. Ideally, LC based frequency divider can operate up to several tens of GHz. This DFF based ILFD, however, due to the large parasitic capacitance at the load node, can not exceed operation frequency of 15GHz. The best case would be using inductive peaking and hence a maximum self-oscillation frequency of appro- ximately 20GHz can be achieved. Therefore, the divide-by-32 circuitry can be implemented using the cascaded Divide-by-2 DFF frequency dividers.

Fig. 4 Schematic of the Frequency Divider

The design challenge for this DFF based divider lies on the self-oscillation frequency close to 13GHz. Based on experience, to achieve locking of the 28GHz signal, a DFF based FD with a self-oscillation frequency of 11GHz -12GHz would be a qualified candidate. The key point is the size of the latch transistor pairs. Due to the cross-coupled load pair, the output node exhibits a large load parasitic capacitance (normally twice as the value of the differential pair output node). Therefore, the size of the latch pairs should be kept small enough to gain a high self-oscillation frequency.

5．Result and conclusion

In fig 5, it can be observed that when 0φΔ > , the output of PFD increases to speed up the VCO oscillation. The loop filter has been optimized to limit the ripple within 10mV.

Fig. 5 Output of PFD when a phase error exists

Shown in figure 6 is the tuning range of VCO. The X-axis is the control voltage of the VCO, Vcont. Y-axis is the oscillation frequency of the VCO. So as the control voltage varies from 0 to 1.2V, a wide tuning range from 23.75GHz to 28.25GHz is achieved.

Figure 6 Vcon versus oscillation frequency

In fig. 7, the frequency of the input and output of the first stage divider is shown. It is always the case that the first stage of frequency divider is always the most challenging. The input frequency of the first stage divider is 26.4GHz and the output frequency is 13.2GHz.

Figure 7. the frequency spectrum of the input and

output signal of the first stage divider The main specifications are list below in the table.

Table1 the main specifications of the PLL synthesizer 1ststage frequency divider locking range GHz

Power (static) mW

Quadrature Mismatch

Q-VCO tuning range GHz

Vcont range (V)

8-30 34 1.7° 23.75-28.25 0.05-1.2

In this work, we proposed a 26GHz Phase- Locked Loop based Frequency Synthesizer in 0.13um CMOS Process. The frequency synthesizer generates the 26GHz output signal from 812.5MHz input. The static power consumption with a power supply voltage of 1.2V is

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34mW. With the control voltage of the varactor varying from 0.05V to 1.2V, a tuning range from 24GHz to 28GHz can be achieved. The mismatch is the quadrature signal from the VCO is less than 2°. The phase noise of the QVCO is -95dBc/Hz at 1MHz offset. The first-stage of divide-by-2 divider has a wide locking range from 8GHz up to 30GHz.

6．Reference

[1] Lan-Chou Cho, Chihun Lee, and Shen-Iuan Liu, “A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13um CMOS Technology”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 6, JUNE 2007, P1261-P1270.

[2] David R. Rolston, David M. Gross, Gordon W. Roberts, and David V. Plant,” A Distributed Synchronized Clocking Method”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 52, NO. 8, AUGUST 2005, P1597-1607. [3]Sadeka Ali, Faquir Jain. “A Low Jitter 5.3GHz 0.18um CMOS PLL Base Frequency Synthesizer”. IEEE Radio Frequency Integrated Circuits Symposium. 2002, P173-176. [4]Ping-Chen Huang, Ming-Da Tsai, Huei Wang etc. “A 114GHz VCO In 0.13um CMOS Technology” 2005 IEEE International Solid-State Circuits Conference 2005 P404-405. [5] L. M. Franca-Neto et al.,”64 GHz and 100 GHz VCOs in90 nm CMOS using optimum pumping method”, IEEEISSCC, pp. 444-445, Feb. 2004.

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