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Audio Sub word Sorter Unit on Merger Sorter Network For Secure Transmission

Gaurav Vijay Bansod Department of Electronics and Telecommunication

Symbiosis Institute of Technology Pune,India

[email protected]

Abstract - Low power applications are major concern area nowadays. One of the major aspects is cryptography which includes software cryptography in audio as well as video applications. Many algorithms are developed to achieve software cryptography. But in recent year’s algorithm are proved to be more efficient. This paper aims to enhance characteristics of HDL based implementation of GRP algorithm. As GRP algorithm is most attractive in term of sorting and cryptographic contents [8]. In this paper low power HDL based design is implemented for audio based applications with much more less power without losing encryption standards as compared to previous algorithms like EMSN[1].This paper proposes a new algorithm REMS which is rich in encryption standards and consumes much more less power.

Keywords: Cryptography, Audio subword, HDL, low power, Permutation

I. INTRODUCTION For audio based Cryptographic application the audio packet

is divided into one or two subwords and then it is further processed for cryptographic application. This concept is called subword parallelism. In this paper implementation of GRP based permutation technique is done at HDL level. As in GRP algorithm each bit is associated with corresponding control bit and Permutation will be done according to control word derived by using GRP algorithm[3].In this paper 16 bits are divided into subword of 8 bits and separate architecture is designed for right as well as for left datapath. As per GRP data bits which are associated with corresponding control bit equal to 1 are concentrated on left hand side while corresponding bit equal to control word 0 are concentrated to right hand side. This permutation technique implemented in hardware as HDL based design to improve speed as well as power. As GRP emerged as an most attractive algorithm by using butterfly and ibutterfly networks [5] , its implementation at hardware level makes algorithm more stronger and versatile. In this paper new architecture is designed as mentioned above with lesser no of multiplexers and even less power as compared to previous existing algorithms. This algorithm can be used for audio based applications for secure transmission.

II. MODIFED ENHANCED MERGER SORTER NETWORK(MEMS)

As in MEMS ,the left and right datapaths are designed by using 2 x 1 multiplexer which consumes much more low power and also used for doing permutation effectively.

Control words are fed as an select signal for individual multiplexer. In MEMS structure[1].The permutation is done by using 18 multiplexer at different levels. A signal called barrier signal is introduced at second level to achieve higher level encryption. This is the first audio sub word sorter unit implemented in FPGA.

The structure of MEMS (Older Algorithm) is shown in fig 1.

Figure 1. Structure of MEMS for Left datapath

III. REMODIFIED MERGER SORTER NETWORK(RMSN)

In this algorithm , first control word is formed for 8 bit subword sorter by using GRP algorithm[3].For a given arrangement that is A7 to A0 ,control word is generated at each iterations[3] and different control words are used for different levels in RMSN architecture.

To generate one GRP instruction and the arrangement Q

2011 IEEE International Conference on Control System, Computing and Engineering

978-1-4577-1642-3/11/$26.00 ©2011 IEEE 127

INPUT: Arrangement P

OUTPUT: Arrangement Q and control bits

INSTRUCTION

Let Pi represent the i(th) MIS in P.the operations that combine integer sequenlonger sequence. Sort(x) is a function that sequence x in increasing order. P can be misses as follows:

P = (P1, P2, P3,…, Pm, Pm+1 , Pm+2…,P

Note that m = k/2 , and P1, P2, P3, …, PMISes.

1. Generate temporary sequences T1, T2,…2,… ,m-1

Ti = (Pi , Pi+m)

If (k is odd) then

Tm = Pm else

Tm=(Pm , Pk)

2. Generate Q:

For i = 1, 2,… , m

Qi= Sort(Ti)

Let Q = (Q1, Q2,Q3,…,Qm).

3. Generate control bits c:

Q can also be considered as a bit string:

Q = (Q1, Q2, Q3,…,Qm) = (b0, b1, b2, …,

For j = 0, 1,… , n-1

if (bj is in P1, P2, P3,… , or Pm)

cj = 0 else

cj = 1

Control words are generated according for arrangement A7,A6,A5 to A0. We can chand accordingly the control words will getEMSN, the bits are swapped according to coto each block, even if one bit of the controlthe whole process and the network structurGRP, the data bits that are associated withequal to one are concentrated to the left sSimilarly, the data bits that are associated wiequal to zero are concentrated on the routput[3]. This action resembles a sorting control bits, where the largest bits that aregathered to the left. Therefore the problemhardware unit that executes GRP is equivalea sorting network that sorts the control bits abits appropriately. So in EMSN special reserve MSB which is good in one side thawill occur in a system our MSB’s are safe aretrieve the information. While other side

c for GRP

. (x, y) denotes ce x and y into a sorts elements in represented by k

Pk-1, Pk)

Pm is the first half

…,Tm: For i = 1,

,bn-1)

to GRP algorithm hange arrangement t changed. As in ontrol words given l word is changed, e changes. As per h the control bits ide of the output. ith the control bits right side of the operation for the

e equal to one are m of designing a nt to the design of

and moves the data care is taken to

at even some error and we can able to is we are losing

encryption standard which is RMSN all bits are reshuffled different stages generated fromencryption standards. Initialencryption and they are dividebits are called Left datapath aRight datapath. Left datapath cwhich are fed through the chaistages of encryption for left as weach stages different control woalgorithm.

IV. IMPLEMENTATIONTRANSMI

In Left datapath ,8 bits withto muxes for doing encryptiowill be done through multiplfed to multiplexer[1] .The cusing GRP algorithm. In firsto A0 are grouped as (A7according to GRP algorithm are swapped with A6 and A0swapped according to the contralgorithm .Grouping are (A5,A3rd stage groupings are (A0fig.2.

Figure 2.Implementatio

IST STAGE

BITS A7 A6 A5

CONTROL 1 0 1

EQUIVALENT SWAPPED

A7 A2 A5 A0 A3 A6

IIND STAGE

BITS A7 A2 A5

CONTROL 0 1 0

more serious issue. So in this using different control words at

m GRP algorithm which is rich in lly 16 bits are taken for ed into groups of 8.Leftmost 8

and rightmost 8 bits are called consist of 8 bits of information in of multiplexers .There are 3 well as for right datapath and for ords are generated by using GRP

N OF LEFT DATAPATH AT ITTER END h arrangements A7 to A0 are fed on. As mentioned above sorting lexers and control words are

control words are generated by st stage arrangements A7 7,A3),(A6,A2),(A5,A1),(A4,A0)

m and as shown below A2,A0 0. In the second stage bits are rol words generated from GRP

A6),(A3,A4) and (A0,A1) and in 0,A5) and (A4,A1) as shown in

on of Left Datapath at Tx end

A4 A3 A2 A1 A0

0 1 0 1 0

D BITS

A1 A4

A0 A3 A6 A1 A4

1 0 1 0 1


128

EQUIVALENT SWAPPED BITS

A7 A2 A6 A0 A4 A5 A1 A3

IIIRD STAGE

BITS A7 A2 A6 A0 A4 A5 A1 A3

CONTROL 0 1 0 1 0 1 0 1


A7 A2 A6 A0 A1 A5 A4 A3

V. IMPLEMENTATION OF LEFT DATAPATH AT RECEIVER END

For leftdata path at receiver again control words are generated according to GRP algorithm. The bits are swapped according to the control words for each multiplexer structure. Again sorting aim should be same to concentrate 1’s on left hand side. Rest e algorithm will be same. In Ist stage (A6, A5) and (A4, A1) are compared and swapped as shown in fig 2. In IInd stage (A5, A2) and (A3, A1) are swapped and in IIIrd stage (A0, A3) are swapped.

At Receiver end

IST STAGE


CONTROL 1 0 1 0 1 0 1 0

SWAPPED BITS

A7 A6 A2 A4 A1 A5 A0 A3

IIND STAGE


CONTROL 0 1 0 1 0 1 0 1

SWAPPED BITS

A7 A6 A5 A4 A0 A2 A1 A3

IIIRD STAGE


CONTROL 0 1 0 1 0 1 0 1

SWAPPED CONTROL BITS

A7 A6 A5 A4 A3 A2 A1 A0

Figure 3.Implementation of Left Datapath at Receiver end

VI. IMPLEMENTATION OF RIGHT DATAPATH AT TRANSMITTER END

For right datapath sorting network implemented on inverted control bits to achieve more encryption standards. Control bits are generated for arrangements A7 to A0. Different control words are generated from different arrangement pattern. In first stage (A7, A3) and (A5, A1) are checked and swapped.

In IInd stage (A4, A1) are swapped and in IIIrd stage (A6,A4) and (A2,A0) are swapped as shown in fig 4.

IST STAGE


CONTROL 0 1 0 1 0 1 0 1

SWAPPED BITS

A3 A6 A1 A4 A7 A2 A5 A0

IIND STAGE


CONTROL 1 0 1 0 1 0 1 0

SWAPPED BITS

A3 A6 A1 A5 A7 A2 A4 A0

IIIRD STAGE


CONTROL 1 0 1 0 1 0 1 0

SWAPPED BITS

A3 A5 A1 A6 A7 A0 A4 A2


129

The above table shows swapping algorithm according to control bits. Different control words are generated for each stage and corresponding bits are swapped. Special care is also taken in this algorithm that swapped bits should not get swapped again so that repetition should not be there.[1].Fig 4. Shows Its Implementation

Figure 4.Implementation of Right Datapath at Transmitter end

VII. IMPLEMENTATION OF RIGHT DATAPATH AT RECEIVER END

At Receiver end for right datapath same algorithm is implemented and bits are swapped according to control word generated for given pattern by using GRP algorithm. In first stage (A3,A7) and (A5,A1) are compared and swapped. In IInd stage (A6,A5) and (A2,A0) are swapped and in IIIrd stage (A6,A4) is compared as shown in fig.5

IST STAGE


CONTROL 0 1 0 1 0 1 0 1

SWAPPED BITS

A7 A5 A4 A6 A3 A0 A1 A2

IIND STAGE


CONTROL 1 0 1 0 1 0 1 0

SWAPPED BITS

A7 A4 A5 A6 A3 A2 A1 A0

IIIRD STAGE


CONTROL 1 0 1 0 1 0 1 0


A7 A6 A5 A4 A3 A2 A1 A0

Figure 5.Implementation of Right Datapath at Receiver end

VIII .RESULT AND DISCUSSION Following changes are made in previous algorithm (EMSN)

1.Different and separate structures are designed for left datapath and right datapath which are rich in encryption standards .

2.In previous algorithm ,2 MSB’s are preserved which will lose encryption standards , in this algorithm all bits are shuffled.

3. Moreover RMSN architecture consists of lesser no of Muxes which will reduce power consumption as well as area without reducing encryption standard

4. Different control words are generated for different arrangements at different stages with GRP algorithm which make RMSN universal.

5.RMSN algorithm is more advantageous as compared to previous algorithms in terms of power, area, speed and complexity.

6. RMSN algorithm provides transparent relation between GRP algorithm and its hardware implementation.[3]

This algorithm is written in Verilog and power is calculated with Xpower tool (Xilinx) as it should be implemented through FPGA..Same circuit is implemented in Cadence tools with RTL compiler and NC SIM Power calculation and waveforms are shown below


130

Figure 6. Power Calculation with XPOWER

Above table shows power for Left datapath at Tx end is

about 77mw . We had calculated for left as well as for right datapath. It is coming 360mw.

TABLE I

Algorithms Power (mW) Sorter based 70

EMSN[1] 600 RMSN 360

IX.CONCLUSION

GRP instruction is useful not only for fast permutations of n bits, but also for sorting n subwords. This versatility is important if GRP is to be included in a general-purpose processor. [7].RMSN algorithm provides high encryption standards as compared to previous algorithm. As this algorithm consists of Lesser Muxes, so it would result in low power as well as low area which would be advantageous for ASIC designing. Since this algorithm is implemented in hardware its speed is also more and can be implemented for Audio as well as video Application. In this paper algorithm is implemented for 16 bit it can be extended for 32, 64 bit also. This algorithm can be implemented for bubble sort effectively [7]. This algorithm is reconfigurable which is new era in ASIC designing[4].RMSN algorithm can be implemented by butterfly and ibutterfly structure so that permutations can be done till 64 bits.[5] This paper is real time application and can be implemented for audio as well as video security applications. The table below shows [5] area will also get reduced.As mentioned from previous papers[6] EMSN is the fastest solution with a minimum delay. So RMSN is faster as compared to EMSN, so much lesser delays as shown in fig 6

Figure 7. Delay Comparison

TABLE II

CIRCUIT AREAORIGINAL GRP ALGORITHM 68.6KGRP ON IBFLY 19.7K

ACKNOWLEDGEMENT

The author would like to thank Symbiosis Institute Of Technology for providing all the tools and support required to carry out this project successfully.

REFERENCES [1]. Karthigaikumar , K Baskaran, ”Hardware Implementation of Low

Power Audio Sub word Sorter Unit for High Security Transmission” International Journal of Computer and Electrical Engineering, Vol. 1, No. 2, June 2009.

[2]. Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Kostas Galanopoulos and Dimitris Niolos, “Sorter based permutation units for Media-Enhanced Processors” IEEE Transactions on VLSI systems, vol 15, no. 6, pp 711-715, June 2007

[3]. Zhijie Shi, Ruby B. Lee,” Bit Permutation Instructions for Accelerating Software Cryptography”, Application-Specific Systems, Architectures, and Processors, 2000. Proceedings. IEEE International Conference ,JULY 2000

[4]. Jer Min Jou, Yun Lung Lee, Chen Yen Lin and Chien Ming Sun, “A Novel Reconfigurable computation unit for DSP applications”, IEEE comp. society annual symp. on VLSI, ISVLSI’07, pp 439- 444, 9-11 March 2007

[5]. Yedidya Hilewitz, Zhijie Jerry Shi and Ruby B. Lee, “Comparing Fast Implementations of Bit Permutation Instructions” Signals, Systems and Computers, 2004. Conference Record of the Thirty-Eighth Asilomar Conference 7-10 NOV 2004

[6]. Zhijie Shi and Ruby B. Lee,” Subword Sorting with Versatile Permutation Instructions” Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD’02)

[7]. Ruby B. Lee, Z. J. Shi and Y. L. Yin,Ronald L. Rivest M.J.B. Robshaw” On Permutation Operations in Cipher Design” Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004. International Conference 5-7 April 2004

[8]. Z.J.Shi and R.B.Lee, “Implementation Complexity of bit permutation instructions”, in Proc.Asilomar Conf. Signals Stst. Comput, pp 879-886, 2003.

[9]. Navid Lashkarian, Ed Hemphi, Helen Tarn, Hemang Parekh and Chris Dick, “Reconfigurable Digital Front End Hardware for wireless base-station transmitters: Analysis, Design and FPGA implementation”, IEEE transactions on circuits and systems, vol 54, No. 8, pp 1666-1677, Aug 2007.


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