PPTP: Pre-Post Terminal Propagation in Modern Fixed-Outline Soft Module VLSI Floorplanning

Design

Chyi-Shiang Hoo*, Kanesan Jeevan, Velappa Ganapathy, Harikrishnan Ramiah Department of Electrical Engineering, Faculty of Engineering,

University of Malaya (UM) Lembah Pantai, 50603 Kuala Lumpur, Malaysia

Email: francioshoo@siswa.um.edu.my Abstract—From the point of view of the industry, floorplanning is very important in VLSI chip physical design because it will deeply affect the time-to-market and the quality of the product. A new floorplanning algorithm namely Pre-Post Terminal Propagation (PPTP) has been proposed to handle soft module floorplanning by employing multilevel framework. Pre-Terminal Propagation is employed at the root node only in order to increase more possible partitionings, as introduction of TP at every level will restrict the partitioning results. However, non-inclusion of TP at the subsequent partitioning will lead to the lack of information about the external pins at every level in the tree. Hence, Post-Terminal Propagation is adapted to compensate this deficiency. PPTP gives improved optimal HPWL solutions and faster runtimes for soft module floorplanning based on Gigascale Systems Research Center (GSRC) benchmarks. The results obtained establish that PPTP is a high performance floorplanner as compared to other state-of-the-art floorplanning algorithms. This indicates this makes PPTP more suitable for industrial VLSI physical design implementation.

Keywords-Computer-Aided Design; Floorplanning; Terminal Propagation; VLSI; Circuit Layout.

I. INTRODUCTION The physical design of VLSI chip has become more and

more complicated and complex as the scale of the chip is decreasing due to the advancement in nanoscale IC technologies. This is because of the Moore’s law [1][2] which has been steadily maintained in the commercial IC design. The density for a particular IC chip is highly depending on the electronic design automation (EDA) tool as well as the assumptions made, constraints considered and framework selection by the software developers. However, there are some crucial challenges existing in the classical outline-free floorplanning, which are limitations in packing-driven floorplanning [3], difficulty in choosing the coefficients in Pareto front/ non-dominated frontier (NDF) [4], low scalability, time consuming, and inconsideration of essential constraints such as fixed-outline [5].

Hence, as discussed by Chen et al. [6], the hierarchical [7] and multilevel floorplanning frameworks are preferred in modern floorplanning, rather than flat frameworks. The works in [5] and [8] have reviewed and revealed the new trend of modern EDA floorplanning concerning the elimination of classical floorplanning bottlenecks as discussed above. Adya et al. [9] have pointed out that the fixed-outline constraint

[10][11] and optimization of half-perimeter wirelength (HPWL) are the necessary parts in practical floorplanning. In [9], evolutionary turn points of the modern floorplanning are introduced where the minimal whitespace requirement is considered as a constraint instead of an objective. This simplifies the modern floorplanning by prioritizing the wirelength minimization. This is because the whitespace assigned can be used for other design purposes such as buffer insertion [12], level shifter positioning [13], thermal legalization, etc. Fixed-outline constraint causes modern floorplanning more difficult than conventional outline-free type, even in area-driven floorplanning [11].

A. Recent Works Recent outperformed works on EDA floorplanning are

employing hierarchical/multilevel frameworks. Defer [14] generated the generalized slicing tree by using the state-of-the-art hMetis [19] hypergraph partitioning method and the orientation of the modules are deferred to a certain level before they are combined via dynamic programming enumerative packing (DPEP) and refined. IMF [6] is the first floorplanner which proposed the “Λ-shaped” multilevel framework which imply connectivity-driven hMetis [19] and Accelerative Fixed-outline (AFF) packing techniques, with no interference in between. In [15], the whitespace fundamentals in top-down hierarchy are proposed so that whitespace can be controlled and predicted. However, there is no empirical comparison with other state-of-the-art floorplanning algorithms. PATOMA [16] employed purely cutsize-driven top-down approach followed by legalization. UFO [17] introduced a 2-ways multilevel framework. During the global distribution, circle and push-pull (PP) model is used to distribute the circles by considering the wirelength only. Meanwhile during the local legalization, the modules geometrical information is formulated. SAFFOA [18] introduced a SA-based top-down Ordered Quadtree hierarchical framework to handle purely soft modules floorplanning problems. Fixed-outline constraint is considered in all these recent modern floorplanning algorithms.

The rest of this paper is organized as follows. Section II shows the algorithm flow of PPTP and discusses the techniques used in PPTP. Section III compares the proposed PPTP with other recent fixed-outline floorplanning algorithms. Finally, this paper ends with the conclusion drawn in section IV.

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Fig. 1. Pseudocode on algorithm flow of PPTP.

Fig. 2. Outline Violation/aspect ratio outmatch in partition *.

II. ALGORITHM FLOW OF PPTP This paper presents a fast, high-quality, and scalable fixed-

outline floorplanner, namely PPTP which can handle soft module modern floorplanning efficiently and effectively. Essentially, PPTP consists of three steps as shown in Fig. 1.

A. Partitioning Step (Pre-Terminal Propagation) PPTP employs a slicing tree to represent the floorplan

layout where the orientation of subcircuits (left-right/top-bottom) and cutline of the subcircuits are determined during the top-down recursive min-cut algorithm. There are three crucial factors in the partitioning stage:

1) hMetis Hypergraph Partitioning As discussed in section I, hierarchical frameworks are

employed to handle large scale floorplanning problems as hierarchical framework can slit the floorplan problem into k-subproblems recursively and speed up the solution search space. Though flat framework can explore the solutions, it causes an extremely high cost. Thus this stage divides the floorplan circuit into two subcircuits recursively, by minimizing the min-cut/interconnections between the subcircuits until the number of modules in circuits has become four or less. In PPTP, the state-of-the-art hypergraph partitioner, namely hMetis [19] is adapted to construct the generalized slicing tree, until the number of modules is four or less. In order to make sure all the soft module dimensions fit to the constraints, two near square constraints are generated by cutting the outline appositively at every level (horizontal followed with vertical or vice versa).

2) Area-driven Linear Ordering Partitioning When the number of modules in a particular level is equal

to four or less, an area-driven linear ordering partitioning is applied in order to reduce the fixed-outline constraint violation. The modules will be sorted into a linear descending order by referring to the areas of modules. If the number of module is four, the two largest modules will be put into the same partition, so do the other two. Meanwhile, if the number of modules is three, the largest module will be put into a single partition, so do the other two. This is because when hypergraph partitioner generates two subfloorplans with similar weights, there is a high possibility that the largest module is grouped with the smallest module. This will cause the aspect ratio violation if the smallest module has to be fitted

into the flat outline which is caused by cutline, as shown in Fig. 2. Thus, the smallest module will be assigned the minimum sustainable aspect ratio as well as its dimensions, which infract the required outline constraint. This will degrade the overall floorplan in terms of outline constraint, area tolerance as well as wirelength optimization.

3) Pre-Terminal Propagation Terminal Propagation (TP) [20] is introduced at the first

level of this partitioning stage although TP can be applied at every levels of a tree theoretically. However, in this work, TP is not applied at every level with the purpose of increasing the possible partition outcomes as TP restricts the possible partitioning results. On top of that, when the size of partition decreases, the effect of TP on the floorplan reduces. The TP involved during hypergraph partitioning is called as Pre-TP.

B. Geometrical Formulation Step In this stage, the dimensions of the soft modules are

determined based on the outline constraint and the soft modules with fixed dimensions will be orientated based on the cutline. The cutline direction is always parallel to the shorter side of a region in order to generate a pair of near-to-square subregions as this will maintain the aspect ratios of the subregions from exceeding the maximum aspect ratio of the soft modules at the leaf nodes.

C. Rotation/Flipping Step (Post-Terminal Propagation) Terminal propagation [20] only considers the one third of

the IO pads at the root node and at every level all the modules in a partition are considered to be concentrated on the center of the partition. The preferable location of a module and the subfloorplan order are unpredictable due to lack of TP at every level. Hence, Post-Terminal Propagation (Post-TP) is introduced to compensate the lack of global knowledge during hypergraph partitioning. After the final floorplan layout is obtained, the first three level partitions will be rotated through 180 degree or flipped one-by-one in order to try out all the possibility of best orientation. It is possible to try rotation/flipping for all partitions at every level but this will expensive in terms of computational complexity and runtime.

TABLE I. RESULTS OF PPTP ON GSRC SOFT MODULE FLOORPLANNING PROBLEMS.

Problem AR = 1:1 AR = 2:1 AR = 3:1 Trun (sec) HPWL WS HPWL WS HPWL WS

n10a 35140 0 36022.2 0 38046.8 0 0.05 n10b 41732.5 0 42117.9 0 45836.1 0 0.07 n10c 38865.5 0.1 40859.7 0 41818.3 0 0.08 n30a 104443 0 105145 0.72 112605 0.08 0.14 n30b 106800 0 114994 0 124645 0 0.15 n30c 131727 0 138248 0 137048 0 0.13 n50a 133989 0.06 135770 0.47 146708 0 0.17 n50b 150827 0.45 160243 0.37 170797 0.35 0.20 n50c 147462 0 155851 0.08 165129 0.09 0.18

n100a 212914 0.32 213235 0.53 223668 0.48 0.21 n100b 205948 0.13 213306 0.60 227920 0.49 0.22 n100c 207569 0.52 212597 0 222315 0.65 0.20 n200a 373712 0.48 383305 0.66 405305 0.34 0.53 n200b 376726 0.76 413417 0.84 413417 0.84 0.49 n200c 353991 0.96 381917 0.79 381917 0.79 0.50 n300 490601 0.43 507789 0.61 532582 0.44 0.75

Algorithm flow of PPTP Begin Step 1) Top-down partitioning algorithm Step 2) Bottom-up geometric formulation Step 3) Top-down recursive rotation/flipping End

*

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III. EMPIRICAL VALIDATIONS AND DISCUSSIONS PPTP is designed as a fixed-outline soft module

floorplanner with 1% utilization rate as whitespace is no more an objective but a constraint. PPTP was compiled using gcc on a Linux Ubuntu PC platform with Intel Pentium IV 2.4-GHz CPU and 256-MB memory. The HPWL and runtimes of PPTP are obtained after 25 simulation runs. The GSRC [21] benchmarks are used as the standard for comparisons. The maximum dimension ratio of a soft module is found by calculating the ratio of the maximum dimension to the minimum dimension of the particular module and the minimum dimension ratio is the reciprocal of the maximum dimension ratio. In this work, for the ease of understanding, some abbreviations are introduced below:

AR Aspect ratio WS Relative whitespace (%) HPWL Half-perimeter wirelength nWL Normalized HPWL Trun Runtime nTrun Normalized Trun

AR is the ratio of width to the height of the floorplan layout while WS is calculated by finding the ratio of the difference between the minimum area of the rectangle which covers all the modules and the summation of all the modules’ areas, to the minimum area of the rectangle which covers all the modules. To provide a relative comparison, normalization of results is used to calibrate and compare PPTP results with other benchmark algorithms and the normalization is defined as the ratio of the results of other floorplanning algorithms to the PPTP results.

In this work, the near optimal HPWL, relative whitespace and runtime of all the GSRC soft module problems in five different aspect ratio constraints are shown in Table I. Amongst all the 80 results, the relative whitespaces of all cases are less than 1% which is the whitespace tolerance being assigned to the floorplanner. Xilinx® had explained that FPGA-based platform design demands shorter period of time in physical design so that the designers can modify, apprehend, analyze and implement their design in FPGAs rapidly [22]. This indicates that modern EDA floorplanning tool requires not only robustness but short timeframe also. The low increment of HPWL with respect to the aspect ratio of the floorplan layout indicates the efficiency and low dependency of PPTP to the aspect ratio of the chip. The near optimal HPWLs as well as the fast runtimes show that PPTP is a robust floorplanner which can search for near optimal solution within a restricted period of time.

The HPWL comparisons are made based on the following state-of-the-art floorplanning/placement algorithms: Defer [14], PATOMA [16], UFO [17], and SAFFOA [18], as shown in Table II. The normalized values of HPWLs given in the table bring out the comparisons more vividly. From Table II, it is very obvious that PPTP outperforms in terms of HPWL as compared to other state-of-the-art algorithms. PPTP shows improved results in 36 cases in HPWL as compared to 48 cases of other floorplanning algorithms. It should be noted that in Table II, although UFO shows a slightly lower average normalized HPWL value of 0.99 as compared to PPTP, the normalized runtime of UFO indicates that PPTP performs much better in terms of runtimes ranging from 60 to 6290

times faster than UFO and this is illustrated in Table III. Fig. 3 runtime results of PPTP are compared with Defer and PATOMA as other floorplanning algorithms show excessive normalized runtimes as compared to PPTP. In terms of HPWL, PPTP shows comparable results as that of Defer, but it is obvious that Defer runtimes are relatively higher as compared to PPTP when the number of modules in the floorplanning problems increases and is shown in Fig. 3. It is because in PPTP, there is an ineluctable constant execution period for the floorplanner to do the Post-TP algorithms.

TABLE II. HPWL COMPARISONS ON GSRC SOFT MODULE BENCHMARKS.

Floorplanners Defer PATOMA UFO SAFFOA PPTP Circuits AR HPWL nWL HPWL nWL HPWL nWL HPWL nWL HPWL

n10a 1 - - 52258 1.48 36 398 1.04 - - 35140 2 - - - - - - - - 36022.23 - - - - - - - - 38046.8

n30a 1 - - 156921 1.50 102100 0.98 - - 1044432 - - - - - - - - 1051453 - - - - - - - - 112605

n50a 1 - - 180115 1.34 124300 0.93 - - 1339892 - - - - - - - - 1357703 - - - - - - - - 112605

n100a 1 196457 0.92 283452 1.33 195200 0.92 263200 1.24 2129142 217686 1.02 - - 214430 1.01 281509 1.32 2132353 235702 1.05 - - 235210 1.05 296228 1.32 223668

n200a 1 354885 0.95 505716 1.35 346660 0.93 480014 1.28 3737122 380470 0.99 - - 381320 0.99 520802 1.36 3833053 410464 1.01 - - 406610 1.00 536040 1.32 405305

n300 1 476508 0.97 566242 1.15 476560 0.97 554240 1.13 4906012 514764 1.01 - - 510020 1.00 615713 1.21 5077893 551610 1.04 - - 541240 1.02 617554 1.16 532582

Average Normalized

HPWL 1.00 1.36 0.99 1.26 1.00

TABLE III. RUNTIME COMPARISONS ON GSRC SOFT MODULE BENCHMARKS.

Floorplanners Defer PATOMA UFO SAFFOA PPTP Circuits AR Trun nTrun Trun nTrun Trun nTrun Trun nTrun Trun

n10a 1 - - 1 20 3 60 - - 0.05 2 - - - - - - - - 0.07 3 - - - - - - - - 0.08

n30a 1 - - 1 7.14 87 621.4 - - 0.14 2 - - - - - - - - 0.15 3 - - - - - - - - 0.13

n50a 1 - - 1 5.88 204 1200 - - 0.17 2 - - - - - - - - 0.20 3 - - - - - - - - 0.18

n100a 1 0.09 0.42 2 9.52 677 3223.8 158 752.4 0.21 2 0.09 0.41 - - - - - - 0.22 3 0.09 0.45 - - - - - - 0.20

n200a 1 0.18 0.33 3 5.66 3306 6237.7 690 1301.9 0.53 2 0.19 0.36 - - - - - - 0.49 3 0.19 0.39 - - - - - - 0.50

n300 1 0.78 1.04 4 5.33 4718 6290.7 1563 2084 0.75 2 0.96 1.30 - - - - - - 0.74 3 0.97 1.34 - - - - - - 0.72

Average Normalized

Trun 0.67 8.92 2938.9 1379.4 1.00

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Fig. 3. Normalized runtime comparisons with De

(a) (

(c)

Fig. 4. n300 soft module floorplan layout by PPTP= 1:1 and (c) AR = 1:1.

Table III shows the runtime comparisons

art floorplanning/placement algorithms: Defe[16], UFO [17], and SAFFOA [18] and normalized for ease of comparisons. It is PPTP is implemented on a PC with a sloweamongst all these state-of-the-art algorithmsshows a lower average normalized runtimePPTP, the runtimes of Defer is relatively hwhen the number of modules is increasing. proven that PPTP is capable of hanfloorplanning problems with shorter runtimebe implemented in industry as the optimizreduction of HPWL and runtimes is always industrial EDA tools. Fig. 4 shows the bebenchmark placement layouts using PPTP foratios.

IV. CONCLUSION VLSI floorplanning design will affect the

directly and thus it has high impact on thVLSI chip. In this paper, a fast and robnamely PPTP is proposed to handle fixed-oufloorplanning. Pre-Terminal Propagatio

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ACKNOWL

The authors would like to acknowlof Malaya, Kuala Lumpur, Malaysia fo

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