An Ultra low noise amplifier at X band S.Manohar and V.S.R Kirty

Astra Microwave Products Limited, Hyderabad

Abstract —The design and development of a low noise amplifier that exhibits sub dB noise figures at X band, using a commercially available pHEMT process is presented here. Novelties in our design include the use of stabilizing networks that don’t employ resistors and the use of transmission line based inductors that provide a higher Q alternative to spirals. These techniques serve to minimize the lowest achievable noise figure while allowing unconditional stability, a pre-requisite in commercial, monolithic LNAs. The designed low noise amplifier works from 9 to 11 GHz with roughly 30 decibels of gain over the band and sub decibel noise figures.

Index Terms — Resistive loading, Impedance matching, Low noise amplifiers

I. INTRODUCTION

Low noise amplifiers tend to be the first elements in the receive chain as the added noise from the initial stages tends to have the greatest bearing on the overall noise figure of the receiver. Heterojunction FETs have traditionally been preferred for low noise amplification; electron confinement in a two dimensional electron gas mitigates electron scattering and leads to a lowering of added noise. Very low noise figures are considered desirable in a range of wireless applications; the effort to push the envelope on NF in semiconductor ICs could eventually pave the way for low cost (semiconductor) solutions in niches where performance has been the primary barrier to entry. The development of a monolithic low noise amplifier realized on a 0.15 micron pHEMT process, which exhibits sub dB noise figures at X band is outlined here. Techniques used to accomplish the obtained performance are discussed and results summarized.

II. DESIGN CONSIDERATIONS

A pre-requisite for commercial amplifiers is unconditional stability. The amplifier must be stable regardless of how it is terminated in a system. Microwave FETs that exhibit only conditional stability over frequencies of interest must be resistively loaded so that the amplifying stage becomes unconditionally stable. The principle behind this (resistive loading) is the introduction of resistors to compensate for a negative resistance (looking into or out of the device) [1]. Negative resistance arises from feedback through intrinsic device capacitance (Cgd), which, for certain terminations can cause oscillations [2]. Resistors introduced in the circuit to damp the oscillations out introduce thermal noise that tends to degrade the overall noise figure. Narrow band LNA design using a common source stage also involves the use of gate and a source inductor to achieve a simultaneous noise/VSWR

match [3]. The use of spiral inductors, like resistors, introduces thermal noise into the circuit as the Q of the spirals is finite. Transmission line based inductors that tend to be inductive over a narrower band than spirals provide a higher Q alternative.

Fig. 1 Partial Schematic of a stabilized stage

Fig. 2 Stability factor (K) with inductive source feedback and with both source feedback and a transmission line to ground at the input to the device. K is greater than 1 from DC to 40 GHz for the latter case.

In the presented design, an all transmission line solution to the stabilization/matching problem at the device input yields the lowest possible noise figure from a designer’s stand point. Figure 1 is a partial schematic of the designed LNA that is illustrative of the principle. A small length of transmission line at the source of the FET (inductive feedback) creates a finite positive resistance looking into the device which compensates for the negative resistance generated through drain-gate feedback [2, 4]. A length of transmission line to ground (at the gate of the device) is additionally included in order to short low frequency gain out and ensure unconditionally stable operation from DC-40 GHz (Refer Figure 2). The values of the transmission-line based inductors are carefully optimized and the device appropriately sized in order to ensure unconditionally stable operation while allowing for a (near) simultaneous noise/VSWR match.

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Fig. 3 Complete Schematic of the designed LNA

III. AMPLIFIER DESIGN

A modern design flow commences with a feasibility study. Budget analysis allows a designer to decide the number of amplifying stages, and broadly, the gain and noise figure targets for each stage. Device size and bias points are decided based on DC and S parameter simulations. The circuit design involves the use of a commercial microwave circuit simulation tool into which a process design kit, containing cell layouts and accompanying compact models, can be ported. DFM (Design for Manufacturing) requirements impose additional constraints; the designed circuit has to be statistically centered so that circuit yield is sufficiently high. The circuit must also be analyzed on an electromagnetic solver and co-simulated with active elements before design closure.

If one may split microwave amplifier design into three portions, one could broadly say that the design involves mainly, biasing, stabilization and impedance matching. Based on initial simulations and a perusal of FoMs like MSG (maximum stable gain) and NFmin (minimum possible noise figure), 50x4 um devices were chosen for a design-to-spec requirement at X band. The devices were chosen from a PDK provided by WIN semiconductors, Taiwan, and the simulations performed on AWR’s Microwave office. The design requirement called for sub decibel noise figures at 10.25 GHz +/- 250 MHz with 30 dB gain and a P1dB of 10 dBm over the band. The transistors were firstly self-biased in order to minimize component count in system integration. A 15 ohm resistor was connected (in shunt with a bypass capacitor) to the source of a 200 um FET used in common source configuration in all stages. This was in order to source 20 mA of current from a drain voltage of 2V, an operating point where NFmin was lowest. A bank of resistors was placed at the source of the FETs to facilitate post-fabrication tuning. Drain bias was directly injected (without a choke) with

three levels of bypassing/decoupling, envisioned, to decouple the supply from the circuit.

Unconditional stability for individual stages ensures unconditional stability for the cascaded arrangement. This condition was ensured from DC to 40 GHz (for stage 1 and 2) by the techniques outlined in the previous section. The transmission line to ground at the input to the device presents finite impedance at the design frequency allowing for gain. As the first stage is most critical to the overall noise figure and as the technique used was experimental, the usage of the described technique was restricted to stabilizing only the initial stages. Conventional resistive loading was used to stabilize the final stage. Transmission line inductors were employed to obtain, close to a simultaneous noise/VSWR match over our band of interest. The simulated noise figures (for the LNA) tended to 0.7 dB, in-band. Interstage matching networks with a positive S21 slope were synthesized and introduced (in between stages) to compensate for gain roll-off and ensure flatter in-band gain. The first level of bypassing on the drain lines was realized on-chip. The drain voltage for the final stage was changed to 4V from 2V to meet output power requirements. The design was optimized to be more broadband than the spec keeping design for manufacturing requirements in mind. The complete circuit schematic is represented in Figure 3.

IV. STATISTICAL DESIGN & EM SIMULATIONS

In order to ensure a working design that meets specifications when replicated in volume, the designed circuit has to be statistically centered. Statistical design for the designed circuit was performed using tools available in Microwave office. Circuit yield analysis, in addition to process yield calculations allow the designer to estimate the number of chips that will eventually meet specs, which in turn facilitates pricing.

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Fig. 4 Micro-photograph of the fabricated LNA. As one may observe there are no spirals or resistors involved in the input networks of the first two stages.

In-house design flow involved schematic design/layout concurrency. As the designer steps through the design flow, design re-targeting often has to be resorted to. For instance, if the circuit yield is less than the targeted value and the analysis calls for a change in topology or element, changes have to be made and the circuit re-optimized. Standard cells in the PDK allowed for easier layout and routing; EM models for discontinuities and the aforementioned design flow (involving simultaneous schematic and layout entry), expedited design. Once a consolidated layout is arrived at, it is typically analyzed using a planar electromagnetic solver and co-simulated with active devices as a verification step before design closure. EMsight, the inbuilt MoM solver in Microwave office was used to perform this analysis for our design. A DRC check was also done to ensure that the design conformed to foundry rules, before the layout was converted to gds2 and sent to fab. Figure 4 is a micro-photograph of the fabricated LNA. As one may observe there are no spirals or resistors used for stabilization or matching at the input of the first two stages.

V. DESIGN VALIDATION

The services of a pure-play foundry (WIN semiconductors, Taiwan) were utilized to fabricate the designs. After wafer receipt and dicing, the chips were assembled on a test jig with bond wires used to interface the input/output pads (on chip) to 50 ohm lines on RT Duroid. SMA flanges at the input and output of the jig were soldered to the 50 Ohm lines before measurement. Additional levels of bypassing (100 pF and 1 uF) were included off chip to ensure stable low frequency operation.

Initial measurements using a dedicated noise figure analyzer indicated a higher noise figure and a lower gain than expected. A low ENR source (recommended for sub dB noise figure

measurements) had to be subsequently used to obtain more precise data [6]. Gain reduction is dealt with in the next section. Figure 5 is a plot of gain and NF over X band. Figure 5 indicates that the noise figure of the amplifier just dips below 1 dB in our band of interest (10.25+/- 250 MHz). As the noise figure measurement includes input fixture loss of the test jig we expect lower noise figures at the chip level. Measured return losses were better than 10 dB between 9 and 11 GHz. Table 1 is a comparative study of how the designed amplifier stacks up against other commercial products. In terms of noise figure the designed amplifier is among the best in its class.

Fig. 5 Gain and noise figure of the amplifier between 8 and 12 GHz.

TABLE I

Table. 1 A Comparison of commercial Low noise amplifiers at X band

VI. ELECTROMAGNETIC COUPLING

Experience informs us that the primary impediment to functional amplification in monolithic ICs is the presence of undesired oscillations. Initial tests on our low noise amplifier indicated an in-band gain that was 5 dB less than expected. As the design flow was simulation intensive and because compact models are measurement based and quite accurate, the degree of gain reduction caused us to rule model drift and mismatch issues out. DC probing on the low noise amplifiers indicated consistently higher currents than expected. Our theory was that the additional current consumption was the sign of a

Product Vendor NF Gain CHA-211098F UMS 1.2 dB 19 dB HMC 516 Hittite 1.8 dB 20 dB TGA 2511 Triquint 1.3 dB 20 dB AMT 2142022 Astra 1 dB 30 dB

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supported out-of-band oscillation. Oscillations are hard to detect in multi-stage amplifiers as the overall K factor of the amplifier can be greater than one even in the presence of inter-stage oscillations. Spectrum analysis yielded few clues; a close visual inspection of the layout, however, revealed that unaccounted electromagnetic coupling could have caused the observed problem. A gamma probe available on MWO was used to analyze the internal stability of the LNA stage-wise, with an estimated value of capacitance used to model the (mostly) capacitive coupling between a radiating stub and a via to ground, suspected to be the root source of our problem. The re-simulated circuit indicated potential instability; when the radiating stub was severed (using a manual operation) and the circuit re-tested, the circuit displayed an in-band gain that was in line with simulated data. This was also accompanied by a reduction in the DC current. Fig. 6 shows the location of the problem. The parasitic coupling problem has since been addressed in the prototype development cycle.

Fig.6. Layout of the designed low noise amplifier with the location of the parasitic coupling problem marked out.

VII. CONCLUSION

We have presented a low noise amplifier design at X band and discussed the techniques used to achieve sub decibel noise figures. We endeavor to lower noise figures on our LNAs, in order to facilitate the eventual use of semiconductor solutions in areas where (noise) performance has been the barrier to entry. Comparable in-house efforts have resulted in sub dB noise figure LNAs in the S and C bands.

ACKNOWLEDGEMENT

We wish to thank Mr. B. Malla Reddy, Managing Director, Mr. P.A Chitrakar, Chief Operating Officer, and Mr. M.V. Reddy, Director-Operations, Astra Microwave Products Limited, Hyderabad, for support and kind approval to publish this work. We also wish to acknowledge very useful

interactions with application engineers from AWR Corp. relating to MMIC design flow and planar electromagnetic simulations

REFERENCES

[1] Guillermo Gonzales, Microwave Transistor Amplifiers: Analysis and Design, 2nd edition, Prentice-Hall, New York, 1997

[2] I. Glover, S.R. Pennock, P.S. Shepard, Microwave devices Circuits and Sub-systems for Communication Engineering,Edition 1, March 2005.

[3] Trung-Kien Nguyen, Chung-Hwan Kim, Gook-Ju Ihm, Moon-Su Yang, and Sang-Gug Lee, “CMOS Low Noise Amplifier Design Optimization techniques”, IEEE transactions on microwave theory and techniques, Vol. 52, No.5, pp. 1433-1439, May 2004

[4] D. K. Schaeffer and T. H. Lee, “ A 1.5V, 15 GHz CMOS Low Noise Amplifier”, IEEE Journal of Solid State Circuits, Vol.32, No.5, May 1997, pp. 745-759

[5] Jack Sifri, “Making Designs More Robust Using a New Design Methodology and Powerful Tools to Resolve Yield Problems in Designs”, Microwave Product Digest, Oct 2011

[6] Eric Marsan, “Make Accurate Sub-1 dB Noise Figure Measurements”, High Frequency Design, Feb 2010

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