VLSI PROJECT ABSTRACTSNetwork Security & Cryptographic Sciences, Digital Signal Processing, Arithmetic Core and Digital Electronics, DigitalCommunications and Information theory, Digital Image Processing, Bus Protocols and System on Chip

Network Security & Cryptographic Sciences

1. Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed2. Efficient Implementation of Reconfigurable Warped Digital Filters With Variable Low-Pass, High-Pass, Bandpass, and

Bandstop Responses3. Off-Chip Memory Encryption and Integrity Protection Based on AES-GCM in Embedded Systems4. FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network5. High performance scalar multiplication for ECC 6. An efficient FPGA implementation of the Advanced Encryption Standard algorithm7. A compact 32-Bit AES design for embedded system8. An Implementation of AES Algorithm Based on FPGA9. Hardware efficiency comparison Of AES implementations10.A Novel Architecture for VLSI Implementation of RSA Cryptosystem11.A FPGA Design of AES Core Architecture for Portable Hard Disk12.A Novel Stream Cipher with Hash Function for the RFID Device

Digital Signal Processing

1. Low-Complexity Multiplier for GF(2m) Based on All-One Polynomials2. Low Latency Systolic Montgomery Multiplier for Finite Field Based on Pentanomials3. CORDIC Designs for Fixed Angle of Rotation4. CORDIC Based Fast Radix-2 DCT Algorithm 5. Low power and memory efficient FFT architecture using modified CORDIC algorithm 6. CORDIC Designs for Fixed Angle of Rotation 7. A survey of FPGA based Interference cancellation architectures for biomedical signals8. Optimized FIR filters for digital pulse compression of biphase codes with low sidelobes 9. Design and Implementation of Adaptive filtering algorithm for Noise Cancellation in speech signal on FPGA10. Implementation of generalized dft on field programmable gate array11. Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation12. Distributed Arithmetic LMS Adaptive Filter Implementation without Look-Up Table13. Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR

Algorithm14. Fully Parallel and Fully Serial architecture for realization of high speed FIR Filters with FPGA's15. A Dynamic Partial Reconfigurable FIR Filter Architecture16. Hardware Implementation of Discrete Fourier Transform and its Inverse Using Floating Point Numbers17. Implementation of Adaptive FIR Filter for Pulse Doppler Radar18. FPGA Implementation of an Adaptive Filter Robust to Impulsive Noise: Two Approaches19. FPGA Implementation of Digital Up/Down Convertor for WCDMA System20. Design and FPGA Implementation of Linear FIR Low-pass Filter Based on Kaiser Window Function21. FPGA Implementation of Adaptive LMS Filter22. An event-driven FIR filter: design and Implementation23. Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm

Arithmetic Core and Digital Electronics

1. Low-Power and Area-Efficient Carry Select Adder2. Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection3. Design and implementation of demodulation technique with complex dpll using cordic algorithm 4. A New Approach for High Performance and Efficient Design of CORDIC Processor5. Design of Plural-Multiplier Based on CORDIC Algorithm for FFT Application6. Hardware Efficient Architecture for Generating Sine/Cosine Waves7. FPGA Design of a Fast 32-bit Floating Point Multiplier Unit8. Design & Implementation of Floating point ALU9. A FPGA IEEE-754-2008 DECIMAL64 FLOATING-POINT ADDER/SUBTRACTOR

VLSI PROJECT ABSTRACTSNetwork Security & Cryptographic Sciences, Digital Signal Processing, Arithmetic Core and Digital Electronics, DigitalCommunications and Information theory, Digital Image Processing, Bus Protocols and System on Chip

10. FPGA Implementation of Sine and Cosine Value Generators using Cordic Algorithm for Satellite Attitude Determination and Calculators

11. Design and Implementation of CORDIC Processor for Complex DPLL12. Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection13. FPGA Implementation of a chaotic oscillator using RK4 method14. An Efficient Implementation of Floating Point Multiplier

Digital Communications and Information theory

1. Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes2. Reconfigurable FFT using CORDIC based architecture for MIMO-OFDM receivers 3. Speed optimization of a FPGA based modified viterbi decoder4. Faulty Node Detection in Distributed Systems Using BCH Code 5. Optimizing Chien Search Usage in the BCH Decoder for High Error Rate Transmission 6. BPSK System on Spartan 3E FPGA7. FPGA Implementation of Encoder for (15, k) Binary BCH Code Using VHDL and Performance Comparison for Multiple

Error Correction Control8. Design of a Mixed-Signal Cartesian Feedback Loop for a Low Power Zero-IF WCDMA Transmitter9. Design and implementation of demodulation technique with complex dpll using cordic algorithm 10. Implementation of generalized dft on field programmable gate array11. Design and Implementation of Reed Solomon Decoder for 802.16 Network using FPGA12. Hardware Implementation of Discrete Fourier Transform and its Inverse Using Floating Point Numbers13. Implementation of Adaptive FIR Filter for Pulse Doppler Radar14. FPGA Implementation of Modified Architecture for Adaptive Viterbi Decoder15. An Efficient All-Digital Phase-Locked Loop with Input Fault Detection16. A Novel Hardware-Based All-Digital Phase-Locked Loop Applied to Grid-Connected Power Converters17. Mixed Cartesian Feedback for Zero-IF WCDMA Transmitter 18. FPGA Implementation of Digital Up/Down Convertor for WCDMA System19. Analysis of 32-bit Fault Tolerant ALU Methods

Digital Image Processing

1. A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise2. An FPGA-Based Hardware Implementation of Configurable Pixel-Level Color Image Fusion3. Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT4. HD Resolution Intra Prediction Architecture for H.264 Decoder

Bus Protocols and System on Chip

1. FPGA based implementation of a double precision IEEE floating-point adder 2. Design and Functional Verification of I2C Master Core using OVM