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363 978-1-4799-5296-0/14/$31.00 © 2014 IEEE PROC. 29th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2014), BELGRADE, SERBIA, 12-14 MAY, 2014 A 3-10 GHz Ultra Wideband 130 nm CMOS Low Noise Amplifier A. Pajkanovic, M. Videnovic-Misic Abstract — An ultra wideband (UWB) low nose ampli- fier (LNA) is presented in this paper. It is designed to operate in the complete range (3-10 GHz) as defined by the US Federal Communications Commission (FCC) us- ing the 130 nm CMOS technology process. The main goals of the design are low noise, high linearity and low variance of the gain over the operating frequency range. To achieve this, the two stage topology is used that yields the following results: input reffered intercept point (IIP3) of up to 2.30 dBm and forward gain (S 21 ) of 14.73 dB with the variation of ±1.15 dB over the men- tioned range. Maximum noise factor (NF) is less than 4 dB and the input return loss (S 11 ) is less than -10 dB. The power dissipation is 32.50 mW for the supply voltage of 1.20 V. The process, voltage and temperature (PVT) variations are analysed and the results are discussed in the paper. The results given are obtained through the schematic level simulations using Spectre Simulator from Cadence Design System. I. Introduction The UWB system employs a frequency spectrum spanning 3.1-10.6 GHz, with a minimum channel band- width of 500 MHz or fractional bandwidth greater than 20%. The UWB is a low-power technology that utilizes a power level for transmission that is below the FCC limit on spurious emissions (<-41.3 dBm/MHz). Even though the standard appeared more than a decade ago (defined by US FCC), the UWB still represents a new technology. It is a perfect match for high rate WPAN (IEEE 802.15.3a) with data rates of up to 480Mb/s providing seamless connectivity between consumer elec- tronics for transmission of video, audio and other high bandwidth data [1], [2]. Moreover, another implemen- tation of this technology, IR-UWB, finds its application in low rate WPANs (IEEE 802.15.4a) and WBANs, for precision ranging and telemedicine, respectively [1]. In recent years, CMOS has advanced significantly and today is a standard solution for RF applications, such as GPS [3], WLAN [4], 4G communication [5] and K- band [6], including UWB [2], [7], [8], [9] etc. Regardless of the UWB application, the front-end wideband LNA is obligatory as the first stage of the receiver. Such amplifier must meet several strignent requirements, e.g. broadband input matching, sufficient gain with wide bandwidth, low noise figure, etc. [1], [2]. In designing a wideband LNA, the most challenging A. Pajkanovic and M. Videnovic-Misic are with the Faculty of Technical Sciences, University of Novi Sad, Trg Dositeja Obradovica 6, 21 000 Novi Sad, Serbia, e-mail: {apaj, mirjam}@uns.ac.rs. tasks are impedance and noise matching over a wide band. There are several conventional approaches to the design of an UWB LNA, the basic principles of which are sketched in Fig. 1. Bandwidth can be increased using the distributed amplifiers - however, their power consumption is high, chip area is large and, also, they have higher NF (Fig. 1a). An LC ladder filter can be placed at the input of a common-source (CS) am- plifier, which does increase the power gain, but, at the same time, degrades the NF (Fig. 1b). A negative feedback technique can yield wider band through the gain-bandwidth trade, while preserving the NF , (Fig. 1c). The common-gate (CG) topology yields wideband input matching, the typical example given in Fig. 1d. However, a single-stage CG LNA my not have enough gain and cascading additional stages might be required. Of course, different combinations and variations of these techniques: with and without cascaded stages, inter- stage matching networks, inductive peaking, etc. can be found across literature [8], [10]. Fig. 1. Approaches to UWB LNA design: distributed amplifiers (a), LC ladder (b), resistive feedback (c) and common-gate (d) In this work, a 130 nm CMOS technology is used for design of a 3-10 GHz UWB LNA that meets up-to-date targeted performance overviewed in [8]. II. Proposed Architecture The proposed solution schematic is shown in Fig. 2. The low noise amplifier circuit can be divided in three sub-circuits: a CG (first stage), a CS (second stage) and a matching circuit between the first and the second stage. It has been shown that CG based LNA has some ad- vantages over a CS based, e.g. reduced consumption and improved linearity [9]. The CG is adopted as the

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363978-1-4799-5296-0/14/$31.00 © 2014 IEEE

PROC. 29th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2014), BELGRADE, SERBIA, 12-14 MAY, 2014

A 3-10 GHz Ultra Wideband130 nm CMOS Low Noise Amplifier

A. Pajkanovic, M. Videnovic-Misic

Abstract—An ultra wideband (UWB) low nose ampli-fier (LNA) is presented in this paper. It is designed tooperate in the complete range (3-10 GHz) as defined bythe US Federal Communications Commission (FCC) us-ing the 130 nm CMOS technology process. The maingoals of the design are low noise, high linearity andlow variance of the gain over the operating frequencyrange. To achieve this, the two stage topology is usedthat yields the following results: input reffered interceptpoint (IIP3) of up to 2.30 dBm and forward gain (S21) of14.73 dB with the variation of ±1.15 dB over the men-tioned range. Maximum noise factor (NF) is less than 4dB and the input return loss (S11) is less than -10 dB.The power dissipation is 32.50 mW for the supply voltageof 1.20 V. The process, voltage and temperature (PVT)variations are analysed and the results are discussed inthe paper. The results given are obtained through theschematic level simulations using Spectre Simulator fromCadence Design System.

I. Introduction

The UWB system employs a frequency spectrumspanning 3.1-10.6 GHz, with a minimum channel band-width of 500 MHz or fractional bandwidth greater than20%. The UWB is a low-power technology that utilizesa power level for transmission that is below the FCClimit on spurious emissions (<-41.3 dBm/MHz). Eventhough the standard appeared more than a decade ago(defined by US FCC), the UWB still represents a newtechnology. It is a perfect match for high rate WPAN(IEEE 802.15.3a) with data rates of up to 480Mb/sproviding seamless connectivity between consumer elec-tronics for transmission of video, audio and other highbandwidth data [1], [2]. Moreover, another implemen-tation of this technology, IR-UWB, finds its applicationin low rate WPANs (IEEE 802.15.4a) and WBANs, forprecision ranging and telemedicine, respectively [1].In recent years, CMOS has advanced significantly and

today is a standard solution for RF applications, suchas GPS [3], WLAN [4], 4G communication [5] and K-band [6], including UWB [2], [7], [8], [9] etc. Regardlessof the UWB application, the front-end wideband LNAis obligatory as the first stage of the receiver. Suchamplifier must meet several strignent requirements, e.g.broadband input matching, sufficient gain with widebandwidth, low noise figure, etc. [1], [2].In designing a wideband LNA, the most challenging

A. Pajkanovic and M. Videnovic-Misic are with the Facultyof Technical Sciences, University of Novi Sad, Trg DositejaObradovica 6, 21 000 Novi Sad, Serbia, e-mail: apaj,[email protected].

tasks are impedance and noise matching over a wideband. There are several conventional approaches to thedesign of an UWB LNA, the basic principles of whichare sketched in Fig. 1. Bandwidth can be increasedusing the distributed amplifiers - however, their powerconsumption is high, chip area is large and, also, theyhave higher NF (Fig. 1a). An LC ladder filter canbe placed at the input of a common-source (CS) am-plifier, which does increase the power gain, but, at thesame time, degrades the NF (Fig. 1b). A negativefeedback technique can yield wider band through thegain-bandwidth trade, while preserving the NF , (Fig.1c). The common-gate (CG) topology yields widebandinput matching, the typical example given in Fig. 1d.However, a single-stage CG LNA my not have enoughgain and cascading additional stages might be required.Of course, different combinations and variations of thesetechniques: with and without cascaded stages, inter-stage matching networks, inductive peaking, etc. canbe found across literature [8], [10].

Fig. 1. Approaches to UWB LNA design: distributed amplifiers(a), LC ladder (b), resistive feedback (c) and common-gate(d)

In this work, a 130 nm CMOS technology is used fordesign of a 3-10 GHz UWB LNA that meets up-to-datetargeted performance overviewed in [8].

II. Proposed Architecture

The proposed solution schematic is shown in Fig. 2.The low noise amplifier circuit can be divided in threesub-circuits: a CG (first stage), a CS (second stage)and a matching circuit between the first and the secondstage.

It has been shown that CG based LNA has some ad-vantages over a CS based, e.g. reduced consumptionand improved linearity [9]. The CG is adopted as the

364

Fig. 2. The proposed circuit schematic, including the bypascapacitors and biasing (the RF pads influence is also takeninto account, but these are omitted for simplicity)

input stage of this LNA since its input impedance over awide band is 1/Gm (where, Gm is the effective transcon-ductance, equal to gm for the trivial CG circuit). Thisdoes enable the input to be set very close to 50Ω. How-ever, NF is also proportional to 1/Gm [8], so this valuemust be chosen very carefully, since it represents a verydelicate trade-off between input matching and NF .

Adding the CS as the second stage of the circuit in-creases power consumption and degrades linearity. Nev-ertheless, since CG by itself does not provide sufficientgain at higher frequencies, cascaded stage is needed.Wide enough band can be achieved by choosing a CSstage as the second stage, designed so that it operatesat the resonant frequency of the matching circuit [8].

At frequencies higher than the resonant frequency ofthe CS the noise performance worsens, i.e. NF in-creases rapidly. Also, CG yields very little gain at thehigher end of specturm and the mismatch between theload impedance of the CG and the input impedance ofthe CS results in passband ripples [11]. In order to avoidsuch behaviour, a bandpass filter is used for impedancematching. The matching circuit is designed so that theparallel LC and the series LC network resonate at thesame frequency, i.e. LpCp = LsCs [8].

In a typical CG topology (Fig. 1d), Cp would be theparasitic capacitance of CG transistor. In that case,the magnitude of Cp is adjusted by changing the size ofthe transistor given, which also affects the magnitude ofits transconductance. Hence, input matching and gainare simultaneously achieved over a wide band, while in-creasing NF [8]. Adding the transistor M2 creates acascode CG topology (Fig. 2), which yields improvedisolation and increased low frequency gain by about 2-3dB. However, the parasitic capacitances of M2 degradesgain, linearity, and NF at high frequency [9]. Never-theless, the cascode CG topology is adopted as the firststage of this LNA, since it enables, to some extent, sep-arate design of input matching and NF .

The input impedance of the circuit in Fig. 2 is givenas [9]:

Zin (s) =s/Cgs1

s2 + s gm1

Cgs1+ 1

LSCgs1

. (1)

In this circuit, Lp is the load inductance LD1 andCp is the transistor M2 gate-drain parasitic capacitanceCgd2, whereas Ls is given by L and Cs is given bythe series connection of the capacitor C and the tran-sistor M3 gate-source parasitic capacitance Cgs3, i.e.Cs = C · Cgs3 / (C + Cgs3). Setting the values of theseelements allows fine-tuning of both the S-parametersand the NF in the range of interest. The resistor Rlowers the Q-factor of the resonating circuit.

During schematic level design, pad influence on LNAperformance (especially on Γ(ω)) is taken into account(even though the pads are ommited from Fig. 2). Also,as shown Fig. 2, bypas capacitors are included in thesimulations. All three transistors work in the stronginversion region. The circuit is also adaptable, whichis enabled through two control inputs provided, VK1

and VK2. These are intended to allow compensation ofthe potential process variations. Body of each transis-tor is grounded with a high resistivity resistor (bodyfloating). In this way substrate current noise referredto drain node is reduced, resulting in overall NF re-duction of about 0.5 dB [8]. The transistors M1 andM2 are each implemented as two transistors in paral-lel. Thus, more fingers are available to reduce effectivegate resistance [8]. All components, including coils, areon-chip.

III. Simulation Results

The mentioned figures of merit performance is to beretained over a much larger bandwidth than in the nar-row band applications. Therefore, different parametervalues represent a standard in UWB case [8]. For ex-ample, according to Bode-Fano criterion [12], it is notpossible to achieve arbitrary low reflection coefficientΓ(ω) in the arbitrary wide bandwidth, if there is a re-active component in the load. That is the reason whywideband amplifiers must show higher reflection coef-ficient than their narrow band counterparts with thesame transistor dimensions.

In Fig. 3 the S-parameters and the NF are shownin 2-11 GHz frequency range. The mean value of gain(S21) is 14.73 dB, with small variations within ±1.15dB over the wide range of 7 GHz. Also the input re-turn loss (S11) is less than -10 dB, while the outputreturn loss (S22) is higher in the lower range - but stillacceptable [8]. Due to the gate induced noise (signifi-cant at higher frequencies), the maximum noise factoris at the higher end of frequency range NFmax < 4dB. The stability µ-test results show that the cir-cuit is unconditionally stable. The consumed power

365

Fig. 3. Scattering parameters and noise factor of the LNA shownversus frequency with values within the operating range

is PD = IDDVDD = 32.50 mW for the supply voltageVDD = 1.20 V.Neglecting ro, the LNA noise figure of this circuit can

be modified from [8] and [9] as:

F = 1 +γ

αgm1RS

+δα

5gm1RS

(

ω

ωT

)2

+

+RD

(ω2L2D +R2

D) g2m1RS

(

Zin(s)Zin(s)+RS

)2 +

+F2 − 1

A1(2)

from which noise factor can be obtained as NF =20logF . In Eq. (2) A1 is the available power gainof the CG stage, while F2 is the noise factor of thefollowing one. The parameters associated with transis-tor M1 include the frequency of unity current gain ωT ,the coefficient of channel thermal noise γ, the ratio αof the transconductance gm1 and the channel conduc-tance gds01 at zero drain-to-source bias and the gatenoise coefficient δ [10]. Zin is as defined by Eq. (1).Even though M2 introduces additional noise, its con-tribution remains much less than that of M1 even atrelatively high frequencies. Just like in [9], the ther-mal noise (in Eq. (2) represented by the second term),mainly frequency-independent, also dominates noise ofthe circuit in this work.While ωT increases with technology scaling, linear-

ity worsens due to lower supply voltage and high fieldmobility effects [5]. An LNA must maintain linear op-eration when receiving a weak signal in the presenceof a strong interfering one. The consequences of suchintermodulation distortion include desentisization (i.e.blocking) and cross-modulation. To implement a highlylinear amplifier, large values of transistor overdrive volt-ages (VOD = VGS − VT ) are required [10]. In this case,the presence of the cascode transistor M2 reduces volt-age headroom of M1. Furthermore, transistors draincurrents are large and consumption increases. The lin-

TABLE I

Linearity measurements

f [GHz]IIP3 IIP3

P1dB[dBm]

@200 MHz @50 MHz[dBm] [dBm]

3 -1.70 -1.40 -14.564 -0.72 -0.96 -14.525 1.34 1.05 -13.656 2.45 2.34 -12.907 2.52 2.54 -12.708 1.52 1.69 -13.099 -1.10 -0.71 -14.0610 -3.30 -3.20 -14.92

earity of the circuit is analysed through the measure-ment of the 3rd order input refered intercept point(IIP3) and 1 dB compression point (P1dB). The resultsof these measurements for the circuit in question aregiven in Table I at eight different frequencies, coveringthe whole frequency range (3-10 GHz). Even thoughit is reported that this linearization method provides alinearity boost only for a fairly narrow range of inputamplitude [9], in the case of this work, the yielded re-sults are in accordance with those overviewed in [8] forthe same bandwidth.

PVT variations are shown in Fig. 4. For process vari-ations the results are obtained through corner analysis.Aside from the already seen, the typical case (Fig. 3),two most interesting cases for S-parameters andNF areshown: slow (Fig. 4a) and fast (Fig. 4a). At slow, theresistances are set to the highest values, the transistorto the slowest, and so on. Thus, process variations ofall devices within the LNA, both active and pasive, aretaken into account. Therfore, these two cases representthe worst case scenarios.

Besides the nominal temperature (T=27 C), twomore temperatures of interest are analysed. In Figs.4c and 4d the behaviour of the circuit at T=-40 C andat T=105 C is shown, respectively.

The supply voltage variation influence is analysed byobserving the behaviour of the circuit at ±10% of theVDD nominal value. Therefore, in Figs. 4e and 4f, theS-parameters and the NF are shown at VDD = 1.08 Vand VDD = 1.32 V, respectively.

The input and output return loss values are accepablein all these cases. The critical case for noise figure as athigh temperatures, where it reaches very high values,NFmax = 6.5 dB. Since in all other considerationsshown in Fig. 4 the NF values remained in acceptablelimits, this proves what the Eq. (2) predicts - this cir-cuit’s noise is dominated by the thermal noise. Thereexists another cricital case - namely, at corner slow,forward gain, S21 fails to cover the complete operatingrange, which now becomes 3 to 9 GHz.

366

Fig. 4. The PVT variations analysis for S-parameters and NF of the LNA at: slow (a) and fast (b) corners; temperature of -40 C(c) and 105 C (d); supply voltage VDD = 1.08 V (e) and VDD = 1.32 V (f)

IV. Conclusion

In this work a complete schematic level LNA solu-tion is presented. Cascode CG topology is used to en-able separate design of input matching and noise factor.Body floating resistors further lower the noise and highlinearity is achieved by boosting the overdrive voltage.Through scattering parameters, noise figure, linearity,process, temperature and voltage analysis, it is shownthat this circuit yields up-to-date performance over acomplete UWB spectrum (3 to 10 GHz).

Acknowlegment

This research is done within the project: SENSEIVER-ITN - Low-cost and energy-efficient LTCC sensor/IR-UWB transceiver solutions for sustainable healthy en-vironment, 2012-2015 a part of the FP7 Marie CurieInitial Training Network funded by the European Com-mission, contract number 289481.

References

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