231978-1-4799-5296-0/14/$31.00 © 2014 IEEE

PROC. 29th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2014), BELGRADE, SERBIA, 12-14 MAY, 2014

Optimization of Bridged-Grain polysilicon Thin-Film Transistor (BG-TFT)

D. Tassis

Abstract – Polycrystalline silicon thin-film transistors (p-TFTs) can significantly be improved in terms of their performance with the bridged grain structure (BG TFTs) by forming lines with higher doping concentration (5x1015–1016cm-3) across the active channel, equally spaced at a distance close to the average grain size.

I. INTRODUCTION

Polycrystalline silicon thin-film transistor (p-TFT) technology is a rapidly growing field with applications in active matrix liquid-crystal displays and 3D electronics. While n-channel and p-channel single-gate (top or bottom) p-TFTs have now reached a high degree of maturity, using various amorphous silicon crystallization techniques (field-effect mobility lying in the range of 50-200 cm2/Vs and high on-off ratio >107), presently we are at the end of a dormant period in the development of the TFT industry, where the next frontier of expansion rides on the successful implementation of new fundamental p-TFT structures. The aim of this study is the optimization of novel p-TFT architectures, the Bridged-Grain (BG) structure (Fig. 1) by forming n+ or p+ lines across the active channel for n-channel and p-channel TFTs, respectively.

Preliminary TCAD simulation and experimental

results [1] – [3] demonstrated that the on-state current is

increased due to bridging of grains, the off-state current is decreased due to formation of n+pn+ junctions, while the carrier mobility and subthreshold slope are also improved (Fig. 2 as of [1]). These findings indicate that BG p-TFTs are very attractive for driving organic light emitting diode (OLED) and other displays, offering simple processing and excellent device properties and uniformity.

II. DEVICE SIMULATION A. The Effect of one GB

In this paper, initially, we investigated the effect of one grain boundary (GB) within the channel, with simulation parameter the position of the grain boundary. The trap density distribution in the grain boundary contains an acceptor and a donor like distribution that is the result of an exponential function (near the band edge) and a Gaussian distribution with peak near the middle of the forbidden energy gap, similar to [4]. The grain boundary affects the electrical behaviour of the devices dramatically, as it approaches to the drain. When the grain is close to the drain, there is a lack of saturation to the output characteristics. Also, an inclination of the GB makes the influence of the GB smaller. Stronger impact exists for GBs vertical to the channel.

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Gate oxide: 100nm LTOW/L=30m/10m

Ids

(A)

Vgs (V)

BG-ELA@Vds=0.1V BG-ELA@Vds=5V ELA@Vds=0.1V ELA@Vds=5V

Vds=5V

Vds=0.1V

Fig. 2 Transfer characteristics of typical single-gate TFTs, fabricated on polysilicon film with or without BG lines [1].

D. Tassis is in the Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece, e-mail: tassis@physics.auth.gr

Fig. 1 The BG-structure.

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We compared the single crystalline structure (gate length LG= 400 nm) with a structure containing a single GB perpendicular to the direction of the current, near the drain (at position x=350 nm, source is at x=0 nm) Fig. 3(a). Then we added also two BG lines around the GB (12.5 nm apart in each side of the GB) as in Fig. 3(b). We can see the alteration of the potential (Fig. 4) and the free electron distribution (Fig. 5) along the channel when adding a grain boundary and the conductive lines (BG lines). For the same cases, we can see the effects on the input characteristic of the device at VD = 100 mV and 2 V (Fig. 6).

The improvement of the device's electrical behaviour with the BG-lines compared to the one without is obvious, especially in the on-current (about 1.5 to 5 times). In a real device the position of the GB and the orientation can be random, moreover, more GBs will be present. We can perform a Monte Carlo simulation varying the position and the inclination of the GBs or we can choose a pattern that mimics the real case. The grains should better not be rectangular, because in this case their edges would be only either parallel or perpendicular to the channel. In a realistic simulation we must also consider the average size of the grains (150 nm) and the GBs (1-5 nm) in p-TFTs ([2], [4]).

B. Simulation of the p-TFT

By considering different patterns to mimic the behavior of the GBs, in a realistic simulation of the p-TFT, we finally preferred a hexagonal shape of the grain having a net length ρ1, an extra length ρ3 and height ρ2 (Fig. 7). These dimensions can be chosen independently in order to fill the channel with grains properly. In a device with gate length LG= 415 nm and channel width 40 nm, we chose ρ1= 105 nm, ρ2= 20 nm, ρ3= 20 nm and GBs of 2.5 nm. Thus the channel is filled by 2x3 grains (Fig. 7). While the

Source

Si- substrate SiO2

Drain Channel Gate oxide

Gate

GB(a)

Source

Si- substrate SiO2

Drain Channel Gate oxide

Gate

GB

BG lines

(b)

Fig. 3 Schematic of the device after adding the GB (a) and also two BG lines (b).

0 100 200 300 4000.0

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ntia

l (V)

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s in gle crysta llin e s tru ctu re w ith sin gle GB w ith G B a nd tw o BG -lin es

Fig. 4 Potential distribution along the channel under different combinations of the GB and BG lines (at VD= 2 V and VG= 1 V).

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15

20lo

g10(

elec

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single crystalline structure with single GB with GB and two BG-lines

Fig. 5 Free electron concentration along the channel under different combinations of the GB and BG lines (at VD= 2 V and VG= 1 V).

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single crystalline structure with single GB with GB and two BG-lines

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nt I D

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Gate voltage VG (V)

Fig. 6 Transfer characteristics of the device with and without GB and BG lines at VD=100 mV and 2 V.

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silicon in the channel is intrinsic, the BG-lines have a doping concentration of 5x1015 cm-3.

We simulated devices having N=2 to 15 BG-lines

(each one has width 10 nm) and compared the results with the initial device (N=0). The BG-lines are equally distributed along the channel. We can see the input characteristics of devices with N=0 to 15 in Fig. 8. The result depends on whether the BG-lines overlap with the "vertical" GBs. The device with N=4 corresponds to BG-lines that overlap as much as possible with these BGs, by moving them over these GBs. We can see that although the input characteristics are improved the higher the N, the device with optimized position of the BG-lines has the best performance (except for the leakage current), even with substantially less BG-lines. Thus, the optimum displacement of the BG-lines is equal to the average grain size. We can quantify the improvement of the BG p-TFT by comparing the values of the threshold voltage Vt = 1.38 V and the Subthreshold Swing SS= 179 mV/dec (at VD= 100 mV) with the ones for the p-TFT (without BG-lines): Vt = 1.89 V and SS= 219 mV/dec.The improvement in the currents is about 2 to 8 times and in the Ion/Ioff: 8 - 21 times.

In the device with N=7 we compared the results for various doping concentrations of the BG-lines in the range 5x1015 – 1x1019 cm-3 (Fig. 9). The characteristics for concentrations 5x1015 and 1x1016 cm-3 coincide. At higher concentrations while the Ion is improved, all the rest parameters are worse. So, the optimum concentration is 5x1015 – 1x1016 cm-3 and at higher concentrations the behaviour of the device gradually tends to be almost ohmic.

III. CONCLUSIONS

GBs deteriorate strongly the performance of the p-TFTs. By adding BG-lines perpendicular to the channel of the device at a spacing about the size of the GBs and with doping concentrations 5x1015 – 1x1016 cm-3 the p-TFTs can be significantly improved. Thus BG TFTs can be an inexpensive and attractive alternative to the single crystaline TFTs for driving OLEDs and other displays.

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in c

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nt, I

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)

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Number of BG lines

No lines 2 3 4 5 7 10 15

VD = 2 V

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VD = 0.1V

Dra

in c

urre

nt, I

D (A

)Gate Voltage, VG (V)

Number of BG lines

No lines 2 3 4 5 7 10 15

Fig. 8 Transfer characteristics of BG p-TFTs, with N = 2 – 15 BG-lines and without BG-lines (N=0).

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VD = 2 V

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in c

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nt, I

D (A

)

Gate Voltage, VG (V)

BG line dopingconcentration (cm-3)

5x10 15

1x10 16

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VD = 0.1V

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in c

urre

nt, I

D (A

)

Gate Voltage, VG (V)

BG line dopingconcentration (cm-3)

5x10 15

1x10 16

1x10 17

1x10 18

1x10 19

Fig. 9 Transfer characteristics of BG p-TFTs, with doping concentration of the BG-lines 5x1015 – 1x1019 cm-3.

Source

Si- substrate

SiO2

Drain

Gate oxide

Gate

GB

BG lines

Channel

ρ1

ρ3 ρ2

Fig. 7 Schematic of the simulated p-TFT device.

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ACKNOWLEDGEMENT

This work has been performed under the finance of

the research committee of the Aristotle University of Thessaloniki.

REFERENCES

[1] H.S. Kwok et al., “Bridged-grain and other

polycrystalline TFTs”, TFT-ULSI Conference, 2011.

[2] W. Zhou et. al., “Bridged-Grain Solid-Phase-Crystallized Polycrystalline-Silicon Thin-Film Transistors”, IEEE Electron Dev. Letters, vol. 33, pp. 1414-1416, 2012.

[3] W. Zhou et. al., “Fabrication of bridged-grain polycrystalline silicon thin film transistors by nanoimprint lithography”, Thin Solid Films, vol. 535, 6360639, 2013.

[4] P.M. Walker, S. Uno and H. Mizuta, “Simulation Study of the dependence of Submicron Polysilicon Thin-Film Transistor output Characteristics on Grain Boundary Position”, Jap. Journal of Applied Physics, vol. 44, pp 8322-8328, 2005.