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PROC. 29th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2014), BELGRADE, SERBIA, 12-14 MAY, 2014

Fabless ASIC Design, Opportunities for Everybody

D. Manić

Abstract – Chips are everywhere. Silicon content is ever increasing. Many applications get a real added value with a dedicated, optimized integrated circuit. A lot of opportunities are around. The fabless semiconductor model is „democratic”. Foundries are accessible. So, take your chance, be innovative, master your design cost and succeed with your own silicon ASIC.

The first part of the paper gives the motivation for the ASIC designs, the advantages & challenges of the fabless model. The second part presents an overview of some of CSEM’s recent ASIC realizations.

I. INTRODUCTION Silicon content in our life is ever increasing.

Thousands of billions of silicon chips are produced each year. They are everywhere. We find them in smart phones, tablets, PCs, TVs, cars, toys, and soon even smart homes. We find them also in many industrial, medical, health and other applications. The need for microchips is growing and will strongly continue to grow. New trends and technology drivers are appearing, for instance, Internet of Things (IoT), which is already driving the demand for more smart and connected sensors, more chips in very different domains and everyday applications.

The semiconductor industry, the industry dealing with microchips has seen rapid growth over the last 30-40 years and is today worth more than $300billion. Naturally the greatest portion of this “semiconductor pie” is taken by the big players such as Intel, Samsung Electronics, Texas Instruments etc. Semiconductor products can be roughly divided into the three categories standard integrated circuits, ASSPs and ASICs. An Application Specific Integrated Circuit (ASIC) is a chip that is custom designed for a specific application/customer rather than a general-purpose chip such as a microprocessor. An Application Specific Standard Part (ASSP) is an ASIC chip that is designed as a generic device for a particular market. Whereas an ASIC is typically used only by its creator, ASSPs are used by many different companies in the design of their products. The ASSP is one of the key directions in the semiconductor industry today.

Although the competition is strong, there is still a lot of room for smaller players and newcomers to serve ever increasing needs for electronics and chips. “Fabless” chip makers, design houses, IP providers, R&D centers etc. have a large palette of opportunities in front of them. The fabless semiconductor model is the design and sale of chips while outsourcing the fabrication or "fab". "Fabless" chip companies have high growth potential because they are not

burdened by the overhead associated with manufacture. The fabless model opens the door to chip innovation to many players. This model offers access to the state-of-the-art foundry technologies. CMOS technologies continue the progress along Moore’s law and dominate foundry offer and. However, many ASIC developments, in particular for analog processing, do not need the most advanced and the most expensive CMOS processes. Many ASICs can meet the customer’s needs with a mature, widely available and lower cost process such as 0.18µm CMOS.

II. ASIC DESIGN OPPORTUNITIES

An ASIC offers an optimal implementation of the electronics for many applications, in particular if high or specific performances are required such as ultra-low power, high speed, high precision, high complexity or small & specific form factor. An ASIC can integrate as much functionality as needed in a single chip thereby allowing miniaturization of the system, while optimizing performance and power consumption. Many applications get a real added value with an ASIC[1]. The ASIC added value/differentiation, the development costs vs return on investment and time to market are critical commercial parameters in the ASIC success equation

The fabless ASIC model offers the possibility of using the most suitable foundry technologies, IP & partners for a particular ASIC application. The right CMOS technology including the most suitable technology flavors can be selected, along with the packaging and testing services, meeting the performance and cost targets[2]. However, the challenge of managing different partners, getting and assuring access and supply for low-volume and low-cost production remains significant for fabless ASIC suppliers.

Regarding ASIC development costs, an example of the investment breakdown is given in Fig. 1[3].

Fig. 1 Example of a mixed-signal System-on-Chip (SoC) ASIC development cost breakdown.

D. Manić is with the Integrated & Wireless Systems Division, CSEM (Swiss Center for Electronics and Microtechnology), Rue Jaquet-Droz 1, CH-2002 Neuchâtel, Switzerland, E-mail: Dragan.MANIC@csem.ch

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The costs are split into four main items: design, IP, foundry and industrialization. Under the design costs, the costs of specifications, system and block design as well as redesign are included. The IP cost consists of the silicon IP acquisition required for the design, such as a processor core, non-volatile memory, interface (e.g. USB), battery manager & LCD driver. The foundry cost includes the 0.18µm CMOS prototype (MPW) run and full production mask set including engineering foundry run. Finally, the industrialization costs include packaging, test and qualification.

As illustrated in the example above, the design costs often represent the dominant part of the development cost. Controlling design costs by design re-use and accumulated team experience in the field, is of greatest importance. Selection of existing IP can be of help too. Obviously, the emerging design service companies in the geographical regions with qualified design engineers but low cost of labor have their opportunity in the overall IC design space.

The following section provides an overview of some of CSEM’s recent ASIC developments and illustrates some potential ASIC realizations and opportunities.

III. ASIC ILLUSTRATIONS

Five CSEM ASIC developments are presented. These examples are very different circuits serving different markets from consumer, industrial and security to medical. The ASIC illustrations presented range from lower complexity fully optimized small size, low-power mixed-signal analog-digital SoC to a rather complex ECG ADC full RF transceiver SoC. Another group of successful ASIC realizations presented here is related to optical ASICs, in one case a smart vision SoC and in another example an ultra-high-speed, dedicated industrial imager. A. Ultra-low Power SoC dedicated to Social Networking Products

CSEM was approached to design a SoC for Poken, a Swiss start-up commercializing products for social networking. Poken’s first generation product was made with off-the-shelf low-power components. Poken devices facilitate social networking by exchanging URLs in a modern day equivalent of the traditional business card exchange. The objectives of the project were to significantly extend the battery life over the existing product, to add an optional near field communication (NFC) functionality and to optimize the design for high volume production and very low cost[4].

The SoC manages three different communication modes:

• Wireless communication between Poken devices - the SoC exchanges data (URLs) using a proprietary communication protocol patented by Poken.

• NFC communication with a non-Poken device such as a cell phone - the SoC exchanges data via an external NFC transceiver.

• USB 2.0 full-speed communication - the SoC uploads user data to the Poken servers.

CSEM know-how in ultra-low power design and its prior IP (including the icyflex2 processor [5] and several other digital and analog blocks) made a design possible which mostly runs on less than 2 μA at 3 V, excluding brief wireless connections and less critical USB communication accesses. The ASIC is in volume production.

As shown in Fig. 2, the SoC developed by CSEM contains three main parts. First, a digital part includes the icyflex2 processor, interrupt request controller, bus controller, timers, watchdog, GPIOs, real time clock, RAM and ROM and clock and reset management, most of which is CSEM IP. Second, a USB 2.0 full-speed part is part of the system. Third, the analog part contains clock and reset generation, a 48 MHz RC oscillator and a 32 kHz crystal oscillator, power management, LED drivers and the 13.56 MHz protocol implementation.

Fig. 2 Poken ASIC sytem overview. B. An ECG Sensor Interface in a SoC

With the increase of population aging, healthcare costs become a real issue. Tele-healthcare is seen as an answer for reducing hospitalization costs and to offer more autonomy to impaired people. The major concern for tele-healthcare systems is to achieve this purpose with a high accuracy and a long autonomy while being noninvasive. The objective of the IcyHeart project [6] is to investigate and demonstrate a highly integrated and power efficient microelectronic solution for remote monitoring of a subject’s electrocardiogram (ECG) signals [7] (see Fig. 3).

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Fig. 3 IcyHeart analog ECG signal processing front-end.

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A complete SoC has been developed based on the icycom circuit[8]. To our knowledge, it is the first realization of a SoC that embeds an ultra-low-power ADC-based ECG sensing jointly with low-power 32 bits DSP[9] and low-power 868-915MHz radio on a single silicon die.

The SoC runs off a 1 V supply, compatible with a single alkaline cell, and is optimized for long battery life, consuming less than 4 mA in receiving active mode, 40 mA for 10 dBm transmission and 1 μA in standby with RTC running. It enables the development of tiny battery powered smart portable ECG systems with on chip ECG signal acquisition and processing.

A photograph of the chip with the different blocks along with the silicon surface distribution is given in Fig. 4.

Fig. 4 IcyHeart SoC silicon photography with surface distribution. The Icyheart project is an EU FP7 project, supported

by the funding scheme Capacities, Research for the Benefit of SMEs.

C. High Dynamic Range Sensor for Smart Vision Systems

The image sensor market is a fast growing segment of semiconductors. Within this segment, for many niche applications, a custom optical sensor design represents a real differentiator and a real added value solution. A good example is the DVsense ASIC. The photo of the chip is shown in Fig. 5.

Fig. 5 Photograph of the DVSense SoC in a ceramic package for characterization purposes.

The DVSense circuit is a 320 x 240 pixels (QVGA) CMOS digital image sensor providing a high dynamic range and an intensity resolution independent of the illumination. It combines on a single chip image capture and processing such as contrast magnitude and direction. The DVSense circuit has been integrated in a 0.18 µm optical process and implements all the classical production tests necessary for mass production[10].

The main features of the SoC are: • In addition to the luminance information, the

readout path extracts on-the-fly the local contrast magnitude and direction to reduce the processing power required to analyze a visual scene.

• Correctly exposed HDR images without any need to adapt to the illumination level.

• A programmable region of interest (ROI) valid for luminance, contrast and direction features.

• Several image acquisition modes: free run mode with programmable frame rate or external trigger.

• On-chip ambient light sensing in order to enable or disable external LED illumination.

A high dynamic range image from the laboratory coming out from the DVsense circuit is given in Fig. 6.

Fig. 6 High dynamic range visual scene (luminance). D. An Ultra High Speed 4-Line Optical Sensor

An optical line sensor capable of acquiring simultaneously and in a single shot white, red, green and blue (WRGB) lines at an ultra-high rate (4x 200’000 lines per second) was developed. Such a sensor fits perfectly to high power white LED illuminations, which are now finding widespread use in many applications. The sensor is implemented in a 0.18-µm optical CMOS process[11].

The scanning of the 4 lines is implemented with a rolling shutter, as in a conventional area-scan sensor. The readout of each column consists of a correlated double sampling (CDS) stage (amplifier) followed by a 10bit SAR ADC, both running at 1.2 μs rate. This short readout time still allows very reasonable 4.5 μs exposure time per line when the sensor operates at 200’000 lps (5 μs rate). The ADC digital outputs are subsequently stored in a line

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register before being multiplexed to the output ports. The packaged optical sensor and its layout are shown in Fig. 7.

Fig. 7 Ultra High Speed 4-Line Optical Sensor in custom 161-pin CLGA ceramic package (on the left) and chip layout (on the right). E. A 1-1.5mW Tx-Rx 2.45GHz 200kbit/s System-in-Package in less than 13mm3

The WiserBAN[12] EU FP7 project coordinated by CSEM aims at the realization of an ultra-low-power miniaturized System-in-Package targeting wearable and implanted devices for healthcare, biomedical and lifestyle applications. Contrary to the first fours examples of the ASIC developments done for direct industrial customers, the WiserBAN is a research project exploring technology foundations for the future wearable and implantable radio microsystems. The WiserBAN consortium federates some of the leading European research institutes and universities in the fields of low-power radio, SoC/SiP integration, antenna and propagation. It includes also several major industrial partners and SMEs covering a wide range of end-user applications.

The dominant functional block, regarding the energy consumption as well as volume, because of associated passive components, is the radio transceiver. Classical architecture implementations are always a trade-off between overall volume and performances. This is especially the case concerning the energy consumption and particularly for the targeted applications for which all aspects are extremely tight because of limited battery capacity. In addition, the budget link needs to remain optimized because of very small antennas, disturbed propagation environment, etc.

For these reasons, a novel radio transmitter architecture has been implemented in 65nm standard CMOS technology, taking advantage of MEMS piezoelectric components, for further miniaturization (e.g. to get rid of quartz crystal), reduced energy consumption (e.g. to reduce star-up overhead) while conserving high end radio performances (e.g. low noise fine step fully programmable frequency synthesis). For the targeted datarate of 200 kbit/s, the power consumption is close to 1 mW[13].

The WiserBAN SoC (see Fig. 8) also implements a CSEM-proprietary low-power (75 μA/V/MHz) DSP for control, protocol and processing, with 96 kB RAM, RTC, SPI, GPIOs, etc. A WiserBAN microsystem is developed with all passives using a System-in-Package approach (illustrated also in Fig. 8).

Fig. 8 Wiseban chip (left) and 4.25 x 4.25x 0.77mm system in package (right).

IV. CONCLUSION It is obvious that silicon chip content is ever

increasing in the today’s world. Optimized, dedicated, application specific chip designs can offer a clear differentiator and can have a role to play in the great variety of different market opportunities. The fabless model offers the possibility of using the most suitable foundry technologies, IP & partners for a particular ASIC application. The ASIC added value, the development costs and time to market are critical commercial parameters in the ASIC success equation. The emerging design service companies in the geographical regions with qualified designers and low cost of labor have also their opportunity in the overall design space.

Finally, the recent CSEM ASIC developments, described here, are only brief illustrations of the large palette of applications and ASIC types that can be addressed today.

So, why not take your chance by being innovative, mastering your design cost and succeeding with your own silicon ASIC?

ACKNOWLEDGEMENT

Many thanks to the whole team of Integrated and Wireless System Division for its continuous contribution to the world recognized CSEM low-power/low-voltage IC design competence and successful ASIC realizations in the recent years.

REFERENCES [1] D. Manic et al “System-On-Chip Solutions For Portable Medical

Devices”, in Medical Device Technology Magazine, vol. 19, pp. 38–40, March/April 2008.

[2] D. Manic “Fabless ASIC model experience from the perspective of the specialized IC design centers”, in Successful Fabless Semiconductor 2013 Conference, Paris, France, 2013.

[3] Bas Dorren “Cost efficient ASICs for fabless SME’s”, in Successful Fabless Semiconductor 2013 Conference, Paris, France, 2013.

[4] S. Gyger et al “Design of an Ultra-low Power SoC dedicated to Social Networking Products”, in CSEM Scientific and Technical Report 2010, pp.35, Neuchâtel, Switzerland, 2010.

[5] J.-L. Nagel et al “The icyflex2 Processor Architecture”, in CSEM Scientific and Technical Report 2009, pp.35, Neuchâtel, Switzerland, 2009.

[6] http://www.icyheart-project.eu/ [7] F. Giroud et al “IcyHeart, an ECG Sensor Interface in a

SoC”, in CSEM Scientific and Technical Report 2012, pp.90, Neuchâtel, Switzerland, 2012.

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[8] E. Le Roux et al “A 1V RF SoC with an 863-to-928MHz 400kb/s radio and a 32b Dual-MAC DSP core for Wireless Sensor and Body Networks“, Int. Solid-State Circ. Conf. Dig. of Tech. Papers (ISSCC), pp. 464-465, February 2010.

[9] C. Arm et al “Low-power 32-bit dual-MAC 120 μW/MHz 1.0 V icyflex DSP/MCU core”,in Proc. ESSCIRC 2008.

[10] A. Corbaz et al “HDR Sensor for Smart Vision Systems”, in CSEM Scientific and Technical Report 2012, pp.104, Neuchâtel, Switzerland, 2012.

[11] P. Buchschacher et al “An Ultra-high Speed 4-line Optical Sensor”, in CSEM Scientific and Technical Report 2012, pp.101, Neuchâtel, Switzerland, 2012.

[12] http://www.wiserban.eu [13] E. Le Roux et al “A 1-1.5 mW Tx-Rx 2.45 GHz 200 kbit/s

System-in-Package in Less than 13 mm3”, in CSEM Scientific and Technical Report 2012, pp.96, Neuchâtel, Switzerland, 2012.