205978-1-4799-5296-0/14/$31.00 © 2014 IEEE

PROC. 29th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2014), BELGRADE, SERBIA, 12-14 MAY, 2014

Moderate Inversion: Analog and RF Benchmarkingwith the EKV3 Compact Model

K. Papathanasiou, N. Makris, A. Antonopoulos, M. Bucher

Abstract — In this paper the validity of the EKV3 advanced compact MOSFET model is verified with DC and RFmeasurements of a 90 nm CMOS low-power (LP) process. The model is capable of describing the edge conduction effect, mainly occurring in moderate levels of channel inversion. Non-linearities are extracted from DC measurements and the robustness of the model is also proven, in terms of RF figures of merit (FoM) suitable for RFIC design, for both n- and p-type MOS devices.

I. INTRODUCTION

With the continuous scaling of CMOS down to the deca-nanometer regime, the need for reliable compact models, providing validity over a wide range of bias, scaling and frequency and accurately incorporating short-channel effects (SCE), becomes imperative. In this work the EKV3 advanced compact model [1] is benchmarked with measurements of a 90 nm CMOS process from TSMC. Various aspects of analog/RF CMOS performance are investigated with respect to channel length scaling and bias, expressed by normalized drain current. The edge conduction effect is a parasitic effect present in many CMOS processes, contributing significantly to increasing leakage, however, compact models usually ignore this effect. As will be shown here, the same effect has a drastic incidence on “analog” quantities particularly in moderate inversion. Classical benchmark tests, regarding the drain current and MOSFET capacitances prove the accuracy of the model up to the third derivative of drain current and for all investigated capacitances.

A great discrepancy on the behavior of MOSFET non-linearities with respect to channel length scaling and inversion level has been reported in literature [2], [3].Specifically, in [2], VIP3 is shown to obtain its optimum value at lower overdrive voltages with channel length scaling. However, in [3], the same group reports that maximum VIP3 is achieved at higher current densities, and thus inversion levels, with technology scaling. In this work, we show that non-linearity metrics, such as third order input intercept points and 1 dB compression point achieve their optimum values at lower inversion levels as channel length decreases. These values are obtained within moderate inversion. The same behavior has recently been reported for

the minimum noise figure of MOSFETs [4]. Certain Figures of Merit (FoM), such as noise and non-linearity, improve with technology scaling and operation at lower inversion levels. Hence this should also be the case for compositeFoM, incorporating individual FoM. Indeed, we show here that performance metrics, such as transconductance frequency product (TFP, Gm·fT) as well as transconductance efficiency multiplied by gate transconductance (Gm

2/ID), standing as FoMs for low-noise amplifier design, achieve their peak values within moderate inversion. This is of great significance as the need for ultra-low-power, high-performance radio-frequency integrated circuits (RFICs)becomes more and more intense [5].

II. MODEL VALIDATION

A. Gummel Symmetry Test

A frequently used benchmark tests for compact models is the source (S) – drain (D) symmetry test, called GummelSymmetry Test (GST) [6] – [8]. GST employs symmetrical biasing of S and D terminals with voltages: VD = V0 + Vxand VS = V0 - Vx, with Vx being swept. An improved GST has been proposed in [9], in which the limitation of bulk zero bias in GST, is surpassed. All derivatives must be symmetric. Odd-order derivatives should be continuous around Vx = VDS = 0V, and even derivatives should be equal to zero [8]. Fig. 1(a) shows that EKV3 has the desired behavior for an n-MOS device of L=100nm, and W=5um,biased in moderate inversion. No discontinuities at Vx = 0Vare present. The 2nd derivative of ID w.r.t. Vx cross the zero point at VDS = 0V. It is strongly recommended to test GST near threshold voltage to avoid discontinuities due to the transition between weak to moderate inversion. EKV3 proves symmetrical to the 3rd derivative of ID. EKV3 has also been tested for capacitance symmetry using [9]. This is shown in Fig. 1(b), where source-drain capacitance (Csd)and gate capacitance (Cg) are also plotted versus Vx.

B. Edge Conduction Effect

The edge conduction effect is an unpleasant effect in modern technologies. It is caused by a parasitic resistance andparasitic conductance in series and in parallel with the intrinsic device, respectively [10].

K. Papathansiou, N. Makris, A. Antonopoulos and M. Bucher are with the School of Electronic and Computer Engineering, Technical University of Crete, Chania 73100, Greece.

206

(a)

(b)

Fig. 1. (a) Improved source-drain current symmetry test (VG = 0.45 V) and (b) capacitances symmetry, for a short n-MOS, with EKV3model.

The impact of the edge effect on the degradation ofMOSFETs threshold voltage [11] has driven fabrication techniques for suppressing it [12]. Ignoring the edge effect may result in gross inaccuracies for analog circuits as shown in Fig. 2, where drain current (Fig. 2a), and normalized gate transconductance to drain current ratio (Fig. 2b) aredemonstrated versus gate voltage and inversion coefficientIC, respectively. The latter is the drain current normalized with the specific current, Ispec, as IC=ID/Ispec [1]. Values of IC=0.1 and IC=10 define the transition from weak to moderate and moderate to strong inversion regions, respectively. Biasing of the specific device in the moderate inversion region where the edge effect is dominant can have dramatic consequences. EKV3 efficiently describes this device limitation, unlike most – if not all – other currently used compact MOSFET models.

(a)

(b)

Fig. 2. (a) Drain current versus gate voltage and (b) Normalized Gm·UT/ID versus inversion coefficient for an NMOS device of L = 2 um and W = 3 um, biased at VDS = 1.2 V and for variable VBS.Markers: measurements, solid lines: EKV3 model with edge effect, dashed lines: EKV3 model without edge effect.

III. MOSFETS NON-LINEARITIES

Non-linearities are usually described by the 1 dB compression point and the 3rd-order input intercept point (PIP3). A way to extract these performance metrics is through DC measurements of drain current with respect to gate-source voltage by calculating the 1st, 2nd and 3rd

derivatives, Gm, Gm2, and Gm3 [13] (1). Fig. 3(a) demonstrates Gm, Gm2, and Gm3 versus IC, whereas Fig. 3(b) presents the corresponding PIP3, calculated via (2), for the shortest and longest available NMOS devices.

2 3

2 32 3, ,D D D

m m m

GS GS GS

I I IG G G

V V V

∂ ∂ ∂= = =∂ ∂ ∂

(1)

3

3

2

3m

IP

m S

GP

G R= (2)

207

(a)

(b)Fig. 3. (a) Gm, Gm2, Gm3 and (b) PIP3 versus inversion coefficient,

for n-MOS devices of W=40x2 um, biased at VDS=1V.

Since for low distortion operation all linearity FoMs should be as high as possible, it is worth noticing that moving towards shorter length devices, the peak value of linearity metrics is moving to lower inversion levels, experiencing the same shift as other FoM previously presented, which for L=100 nm approaches the center of M.I. region (IC=1). The model results are in close agreement with measurements and recent published work [2], [5], [14].

IV. RF FIGURES OF MERIT FOR RFIC DESIGN

Shameli et al. [15] were, to the best of our knowledge, the first to combine Gm/ID and transit frequency fT in a unique FoM for MOS transistors. This FoM is called transconductance frequency product, TFP = (Gm/ID)·fT, thatis used to optimize ultra-low power RF circuits. Taris et al.[16] further investigated TFP in terms of RFIC design. They concluded that TFP stands as a FoM for LNA design, incorporating all individual FoM, namely voltage gain (Gv), operating frequency (f), noise factor (F) and powerconsumption (Pcons), in a single one, according to (3). Their analysis was applied to a common-source LNA, but it can

(a)

(b)

Fig. 4. (a) TFP versus inversion coefficient for an n-MOS and p-MOS device of L=100nm. (b) (Gm)2/ID versus inversion coefficient for n-MOS device of W=40x2 um, and channel length ranging from 240 to 100nm, biased at VDS=1V.

( 1)v m

LNA T

cons D

G f GFoM f

F P I= ∝

−, (3)

2

( 1)mP

LNA

cons D

GGFoM

F P I= ∝

−. (4)

also be extended to the cascode topology. Fig. 4 a)demonstrates the behavior of TFP versus inversion coefficient for the shortest available n-MOS and p-MOS devices of L=100 nm and W=40x2 um, biased at VDS=1V. The p-MOS device has a much lower TFP, due to its lower cut-off frequency. This value is achieved at higher inversion levels, compared to the n-MOS device, though still within the moderate inversion region.

Song et al. [17] proposed an even simpler way to describe the overall LNA performance. Based on the cascode topology they analyzed the FoM expressed in (3), without including the frequency of operation and ended up with (4). GP in (4) is the power. The important point with this simpler

208

expression is that DC measurements are sufficient to describe the RF performance of an LNA, via the ratio in (4). Previous work had shown the width dependence on(Gm)2/ID, with respect to gate-source voltage VGS. The length dependence of the FoM, versus inversion coefficientis shown in Fig. 4 b), for n-MOS devices of channel length ranging from 240 to 100 nm. The FoM experiences the samebehavior with TFP: that is, its peak value is obtained close to the center of M.I.

V. CONCLUSION

In this work, analog benchmarks are used to validate the EKV3 advanced compact in the context of classical symmetry tests for drain current and capacitances. The model verifies DC and RF measurements of a 90 nm LP process, efficiently describing the edge effect, which appears in moderate inversion for the investigated devices. The importance of the moderate inversion region is proven through RF figures of merit, essential for RFIC design, particularly LNA design. All figures of merit are shown to achieve their optimum values within moderate inversion, revealing its great capabilities in the realization of high performance RFICs operating under minimum power consumption.

ACKNOWLEDGEMENT

We acknowledge the partial financial support of the "NexGenMiliWave" project (ΜΙΚΡΟ2-ΣΕ-Β/Ε-ΙΙ), co-financed by the European Regional Development Fund (ERDF) and Greek national funds, and of the Heracleitus II program co-financed by the European Social Fund (ESF) and Greek national funds.

REFERENCES

[1] J.-M. Sallese, M. Bucher, F. Krummenacher, P. Fazan,"Inversion Charge Linearization in MOSFET Modeling and Rigorous Derivation of the EKV Compact Model", Solid-State Electronics, vol. 47, no. 4, pp. 677-683, April 2003.

[2] R. van Langevelde, L. Tiemeijer, R. Havens, M. Knitel, R. Ores, P. Woerlee, and D. Klaassen, "RF-distortion in deep-submicron CMOS technologies", in Tech. Dig., Int. Electron Devices Meeting (IEDM), pp. 807–810, 2000.

[3] P. H. Woerlee, M. Knitel, R. van Langevelde, D. Klaassen, L. Tiemeijer, A. Scholten, and A. Zegers-van Duijnhoven, "RF-CMOS performance trends", IEEE Trans. on Electron Devices, vol. 48, no. 8, pp. 1776–1782, 2001.

[4] A. Antonopoulos, M. Bucher, K. Papathanasiou, N. Mavredakis, N. Makris, R. Sharma, P. Sakalas, and M. Schroter, "CMOS small-signal and thermal noise modeling at high frequencies", IEEE Trans. on Electron Devices, vol. 60, no. 11, pp. 3726–3733, 2013.

[5] A. Antonopoulos, M. Bucher, K. Papathanasiou, N. Makris, R. K. Sharma, P. Sakalas, M. Schroter, "CMOS RF Noise, Scaling and Compact Modeling for RFIC Design", IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 53-56, Seattle, Washington, June 2-4, 2013.

[6] G. Gildenblat, Compact Modeling: Principles, Techniques and Applications. New York, NY, USA: Springer - Verlag, 2010.

[7] Y. S. Chauhan, S. Venugopalan, M.-A. Chalkiadaki, M. A. U. Karim, H. Agarwal, S. Khandelwal, N. Paydavosi, J. P. Duarte, C.C. Enz, A. M. Niknejad, C. Hu, "BSIM6: Analog and RF Compact Model for Bulk MOSFET," IEEE Trans. on Electron Devices, vol. 61, no. 2, pp. 234-244, Feb. 2014.

[8] P. Bendix, P. Rakers, P. Wagh, L. Lemaitre, W. Grabinski, C. C. Mcandrew, X. Gu, G. Gildenblat, "RF Distortion Analysis with Compact MOSFET Models". Proc. IEEE Custom Integrated Circuits Conference (CICC), pp. 9-12, Oct. 2004.

[9] C. C. McAndrew, "Validation of MOSFET model source-drain symmetry", IEEE Trans. on Electron Devices, vol. 53, no. 9, pp. 2202-2206, Sep. 2006.

[10] M. J. Deen, Z. P. Zuo, "A physical model for the edge effects in narrow-width MOSFETs", Solid-State Electronics, vol. 36, no. 11, pp. 1557-1562, Nov. 1993.

[11] T. Oishi, K. Shiozawa, A. Furukawa, Yuji Abe, Y. Tokuda,"Isolation edge effect depending on gate length of MOSFETs with various isolation structures", IEEE Trans. on Electron Devices, vol. 47, no. 4, pp. 822-827, Apr. 2000.

[12] W. Ningjuan et al., "Fabrication of improved FD SOI MOSFETs for suppressing edge effect", IEEE Conference on Solid State and Integrated-Circuit Technology (ICSICT ), pp. 231- 234, 20-23 Oct. 2008.

[13] I. Kwon and K. Lee, "An Accurate Behavioral Model for RF MOSFET Linearity Analysis", IEEE Microwave Wireless Compon. Letters, vol.17, no.12, pp.897-899, Dec. 2007.

[14] K. Lee, I. Nam, I. Kwon, J. Gil, K. Han, S. Park, and B.-I. Seo, "The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application", IEEE Trans. on Electron Devices, vol. 52, no. 7, pp. 1415–1422, 2005.

[15] A. Shameli and P. Heydari, "Ultra-low power RFIC design using moderately inverted MOSFETs: an analytical/experimental study", IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 470–473, 2006.

[16] T. Taris, J. Begueret, Y. Deval, "A 60 uW LNA for 2.4 GHz wireless sensors network applications", IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 1-4, June 2011.

[17] I. Song, J. Jeon, H.-S. Jhon, J. Kim, B.-G. Park, J.-D. Lee, and H. Shin, "A simple figure of merit of RF MOSFET for low-noise amplifier design", IEEE Electron Device Letters, vol. 29, no. 12, pp. 1380–1382, 2008.