35978-1-4799-5296-0/14/$31.00 © 2014 IEEE

PROC. 29th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2014), BELGRADE, SERBIA, 12-14 MAY, 2014

Lanthana and Its Interface with Silicon

Hei Wong

Abstract – In couple of years, the CMOS devices will be

scaled down to the decananometer range and the gate dielectric

thickness, in the sense of oxide equivalent thickness (EOT), will

be shrunk into the subnanometer scale. A higher dielectric

constant material must be introduced. Lanthanum oxide or

lanthana has been considered to be one of the promising next

generation gate dielectric materials. However, it was found that

when lanthana is brought into contact with the silicon substrate,

several undesirable effects, leading to significant device

characteristic degradations, occur. In this review, some issues

related to the material interaction at the lanthana/Si interface will

be discussed. Some measures for overcoming the adverse effects

of lanthana film, such as chemical doping and oxygen chemical

potential control, will be highlighted.

I. CHALLENGES OF SUBNANOMETER GATE

DIELECTRICS

The CMOS technology has empowered the

information technology revolution for several decades. The

feature sizes of the CMOS devices are now approaching

the decananometer scale and that calls for a sub-nanometer

EOT (equivalent oxide thickness) gate dielectric material

[1-2]. The present hafnium-based, or other transition metal

(TM) oxides, gate high-k gate dielectrics will be no longer

suitable for this crucial requirement. Gate dielectric

materials with dielectric constant (k) of over 25 will be

indispensable. It was demonstrated that the rare earth (RE)

lanthanum oxide or lanthana should be a promising

candidate in questing this ultimate challenge [3-4].

Lanthana (La2O3), having a dielectric constant of 27 and a

large conduction band offset of 2.3 eV with silicon, is well

suitable for this application [1]. However as similar to other

high-k metal oxides, there are several fundamental

problems associated with the lanthana. Beside the higher k

value, all the other aspects of high-k materials are poorer

than the conventional silicon based dielectric materials [1-

2]. Table 1 compares various aspects of TM/RE based

high-k dielectrics with silicon-based dielectrics. In

particular, the metal oxide is an extrinsic material to the

substrate silicon. Most TM/RE metal can react with silicon

at elevated temperatures [5-7]. As will be discussed in later

part, the chemical reactions at the high-k/silicon interface

cause most of the performance degradation issues.

Conventional MOS layout for large scale integration is in a

surface structure. The channel mobility of the transistors is

predominately governed by the dielectric/silicon interface.

Improvement of the SiO2/Si interface property had been

one of the major concerns since the invention of MOS

transistor regardless the SiO2/Si interface is almost perfect

as it is grown thermally in a self organization way from the

intrinsic material [8-11]; whereas the quality of high-k

metal/Si interface was found to be much poor.

II. LANTHANA AND LANTHANA/SILICON

INTERFACE

Lanthanum has low valance electron energy, larger

oxygen chemical potential, and larger electronegativity [1,

12-13], these fundamental properties also lead to poorer

material properties than the conventional silicon dioxide.

For example, lanthana has a hygroscopic nature; it is

marginal stable on silicon oxide and that cause the growth

of low-k interfacial layer at normal processing temperature

of the standard CMOS process. Lanthanum can readily

react with the Si substrate. Thermal annealing of high-k

oxides has several impacts on the high-k/Si interfaces and

makes the interface quality poorer than that of the SiO2/Si

interface. Table 2 lists some key properties of lanthanum

and lanthana. Corresponding properties of silicon and

silicon oxide are also listed for comparison. Possible

material interactions amongst these four materials are also

given. Details of the major material interactions and their

consequences will be discussed in the remaining part of

this section.

A. Instability of Lanthana

Lanthana has much higher amount of bulk oxide traps

[1, 4]. The major origin of the bulk traps is the oxygen

vacancies [1]. The vacancies cause large gate leakage

current as a result of trap-assisted tunneling [14-15], and

induce threshold voltage shift because of charge trapping.

The oxygen vacancies also play an important role in the

silicate formation [15]. Similar to other TM oxides and RE

oxides, lanthana is unable upon high temperature treatment.

Fig. 1. Possible thermal instabilities occurred in the bulk of high-k

metal oxides and at the high-k/Si interface [1].

Hei Wong is with the Department of Information Sciences and

Electronic Engineering, Zhejiang University, China; and

Department of Electronic Engineering, City University of Hong

Kong, Hong Kong. E-mail: heiwong@ieee.org

36

TABLE 2. SOME FUNDAMENTALS OF SILICON, LANTHANUM, SILICA, AND LANTHANA AND THEIR POSSIBLE MATERIAL

INTERACTIONS.

TABLE 1. COMPARISON OF KEY PROPERTIES AND ISSUES OF CONVENTIONAL SILICON-BASED DIELECTRICS WITH

HIGH-K DIELECTRICS. NOTE THAT A NUMBER OF ISSUES ARE RELATED TO THE INTERFACE BETWEEN HIGH-K AND

SILICON.

37

Fig. 2 (a) La 3d XPS spectra at different depths of the La2O3/Si

structure. (b) The interfacial La 3d XPS spectrum can be

decomposed into four peaks due to silicate and silicide bonding

[15].

Fig. 3. Lanthana in contact with silicon, especially after thermal

treatment of the as-deposited film, will lead to the formation of a

thick silicate layer.

Figure 1 illustrates the possible thermal instabilities

occurred at the high-k/Si interface and in the bulk of high-k

materials. As illustrated in Fig.1, depending on the

temperature, materials, and processing conditions, thermal

treatment of high-k metal oxides may have several

consequences [1-2]. A low-temperature treatment such as

post-metallization annealing (PMA) will help to release the

interface strain created during previous processing steps.

Higher temperature treatment will result in partial (in the

nanometer scale) crystallization although the crystallization

temperatures bulk-type metal oxides were reported to be

much higher. Thermal processing above 500 oC will result

in interface oxidation and the formation of interfacial

silicate layer. At temperatures higher than 900 oC, serious

crystallization as well as phase separation of silicate will be

possible [1, 16].

B. Lanthana/Silicon Interface

There are several instability issues associated with the

lanthana/silicon interface. Lanthana is more ionic, the

interface bonding turns out to be more unstable when

compared with the conventional silicon-based dielectrics.

When lanthanum atoms react with the substrate silicon, a

relatively low-k interfacial silicate layer will be formed [6].

A silicate layer of about 1 nm thick with dielectric constant

in the range of 8-14 [3] was found. That layer is too thick

and the k value is too low for present technology node. The

composition and bonding structures of the silicate layer

were studied using x-ray photoelectron spectroscopy (XPS)

measurements [15]. Figure 2(a) shows the La 3d3/2 XPS

spectra at different depths of a typical La2O3 film [15]. A

double peak feature with energy of 851.4 eV-855.7 eV in

the bulk represents the oxide bonding. At the interface, the

main peak shifts to higher energy side to 853.2 eV and the

intensity of the satellite peak decreases. This observation is

ascribed to the presence of silicates [15]. Figure 2(b)

should the decomposed interface spectra. Four peaks of

two bonding were found for the La atoms. The main peak

at 853.2 eV and the small satellite peak at 858.3 eV is

attributed to the La-O-Si bonding. The second doublet

(849.8 eV and 856.4 eV) is due to the metallic La-Si

bonding. Note that the lanthanum silicates are not only

found at the interface, it was found in the bulk also. The

interface silicate region may be further broken down into

three sub-layers (see Fig.3). At the bottom of the silicate/Si

interface, a higher amount of La-Si bonds were found. The

middle layer has a high Si content and the major

compositions of this layer are silicon oxide and silicide

phases. The top layer is a silicate layer composed of both

lanthana and silica phases.

This interfacial silicate layer becomes the lower bound

of the achievable EOT. For a high-k dielectric layer with an

Binding Energy (eV)

845 850 855 860 865

Inte

nsity (

Arb

. U

nits)

0

20x103

40x103

60x103

80x103

100x103

120x103

Bulk

Interface

(a)

Binding Energy (eV)

845 850 855 860 865

Inte

nsity (

Arb

. U

nits)

0

5x103

10x103

15x103

20x103

25x103

30x103

La-O-Si

La-Si

La-Si

La-O-Si

(b)

38

silicate interlayer (IL) of tIL thick, the minimum EOT will

be given by

khigh

khigh

ox

IL tk

tEOT

(1)

Fig. 4. Proposed interface interaction between La2O3 and SiO2

and that leads to the formation of interface silicate layer.

EC, Si

EV, Si

EC, Poly

EV, Poly

B1

B2

t2 t1

Si

Fig. 5. Band diagram of a dual layer dielectric with different

values of film thicknesses and band gaps [14].

It is noted that the La2O3-SiO2 system is marginally

unstable with respect to the formation of silicates. Thus, the

forming of interface silicate layer will be easier when there

is a thin silicon oxide layer. Figure 4 depicts the proposed

mechanism for the interfacial silicate layer formation. Even

without an native silicon oxide layer, free oxygen are still

available from various sources: from the ambient, from the

metal or even from the decomposed La2O3; if free oxygen

exists, the most favorable reaction should be the oxidation

of the La2O3/Si interface. These silicon oxide phases then

react with the lanthana via the calcinations process. The

final product of La2O3-SiO2 calcination is a random mixing

La2SixOy phases. It is noted that the bonding structure at the

lanthana/Si interface should be much complicated than the

SiO2/Si case. In the lanthana case, the surface silicon

dangling bonds can be terminated by both oxygen and

lanthanum. Similar to the SiO2 case, if the surface is

terminated with oxygen, a good interface property can be

obtained. However, if the silicon dangling bonds are

terminated with lanthanum, silicide bonds (La-Si) are

formed. The silicide bonds do not have insulating feature

and they are the major precursors of the interface traps [1].

The La-Si bonds are more polar and turn out to be a much

longer bond length. The Si atoms in the La-Si bonds are

negatively charged. These features cause the La-Si to be

broken easier.

C. Effects of Interface Layer on Current Conduction

The low-k interface layer would result in an interface

barrier lowering and then a larger leakage current. A model

was developed by considering a dual-layer structure with

different dielectric constants (see Fig.5) [14]. In this

structure, a larger portion of electric field will be

effectively applied on the low-k region and that gives rise

to the interface barrier lowering. The electric field

distribution on the high-k/low-k stack will be governed by

both thicknesses and dielectric constants of both layers.

According to Ref.[14], the effective barrier can be

modeled by,

(2)

where B1 and B1 are the barrier heights as defined in

Fig.5. The parameter w is defined as:

(3)

where k1, k2, t1, and t2 are, respectively, the dielectric

constants and film thickness of low-k layer and high-k

layer.

As shown in Fig.6, the amount of lowering can be

quite significant and the thicker of the high-k layer, the

severer of the effective barrier lowering. Besides, the

current conduction in high-k materials is very complicated.

Many conduction mechanisms may involve. The possible

mechanisms include [1, 17]:

1) Fowler-Nordheim (FN) tunneling,

2) Poole-Frenkel (PF) effect,

3) Poole-Frenkel with multi-phonon trap ionization.

4) direct tunneling,

5) field ionization of trapped electrons,

6) hopping of thermally excited electrons,

7) trap-assisted tunneling, shallow trap-assisted

tunneling,

8) space charge limited current (SCLC),

9) phonon-assisted tunneling, and

10) grain boundary conduction.

21

1

/1

)1(

BB

Beff

w

w

12

21

tk

tkw

39

Fig.6. An example of effective barrier lowering of a dual-layer

dielectric with different film thicknesses. The high-k layer was

hafnia. Severer lowering is expected for lanthana case because of

it higher k value [14].

Fig. 7. The influence of nanocrystalline phases on the leakage

current mechanisms and parameters on the high-k thin film.

Most of the charge transport mechanisms listed above

are governed by the carrier effective masses and the

interface barrier height [17]. In addition to the barrier

lowing effect, the film crystalline structure would also

affect the barrier height and effective masses [18]. As

mentioned, lanthana has a low crystallization temperature,

nano- or micro- crystallites may exist in different

modifications which may lead to significant difference in

bandgap values, valence band structures, and effective

masses [18]. Fig.8 illustrates the scenarios of a complicated

current conduction involving some nanocrystalline phases

in a high-k dielectric film.

III. SOME MEASURES FOR IMPROVING

LATHANA/SILICON INTERFACE PROPERTIES

There are several methods were proposed to improve

the bulk materials and interface properties of the lanthana

and lathana/silicon structure [15, 19-24]. The key trick is

the reduction of the amount of oxygen vacancies. It was

found that a trace amount of doping with nitrogen or

aluminum atoms does not change the electronic structure of

bulk lanthana but can significantly improve the both the

electrical and material properties of the host material [15,

19-20]. The introduced nitrogen atoms fill up or disable the

oxygen vacancies in the lanthana film. Figure 8 compares

the high-frequency (1 MHz) capacitance-voltage (C-V)

characteristics of the as-deposited lanthana film and the

lanthana films with nitrogen doping using plasma

immersion ion implantation (PIII) [15]. The C-V results

indicate a significant reduction in the bulk and interface

trap densities which are attributed, respectively, to the

consequences of the bulk vacancies and La-Si bonds

reduction and oxidation taking place at the interface after

the nitrogen implantation.

Fig. 8. Capacitance-voltage characteristics of as-deposited La2O3

film and La2O3 film with a trace amount of nitrogen doping [15].

Fig. 9. Schematic diagram showing the idea of oxygen chemical

potential control using the multivalent cerium oxide for

suppressing the amount of oxygen vacancy in the La2O3 film [22].

Thickness of Hafnia Layer (nm)

0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Effe

ctive

Ba

rrie

r H

eig

ht (e

V)

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

tox

= 0.7 nm

tox

= 1.0 nm

40

It was reported that capping the La2O3 film with a

multivalent cerium oxide is an effective way to suppress

the level of oxygen vacancies in the lanthana film [21-22].

The cerium oxide (CeO2), having a smaller value of oxygen

chemical potential, serves as an oxygen reservoir. When it

is brought into contact with the lanthana, some of the CeO2

phases will reduce to Ce2O3 and the released oxygen will

diffuse into the lanthana film and fill up there the oxygen

vacancies. This mechanism is depicted in Fig. 9.

Fig. 10. Comparison of current-voltage characteristics for n-

channel MOS transistors using different gate dielectrics. In device

with CeO2/La2O3 stack, the threshold voltage was reduced and the

transconductance was improved as results of the oxygen vacancy

suppression and the interface roughness reduction [22].

Fig. 11. A TEM picture showing the cross-sectional view of

W/CeOx/La2O3/Si stack. An excellent La2O3/Si interface is

observed and there are some crystallites in the CeOx/La2O3 stack.

Figure 10 compares the current-voltage (I-V)

characteristics of NMOS transistors using the single layer

lanthana and CeO2/La2O3 stack as the gate dielectrics. It

can be seen that the device with CeO2/La2O3 stack has a

smaller threshold voltage as a result of smaller amount of

oxygen vacancy [24]. The transconductance value in the

linear region is also improved. In addition to the reduction

of both bulk trap and interface trap densities, we further

observed a sharp and smooth interface between La2O3 and

silicon. Fig.11 depicts the cross-sectional view of the

W/CeOx/La2O3/Si structure. In this structure, no silicate

layer was found at the interface, and the surface roughness

is much smaller than that for the single layer La2O3/Si

interface (see the result reported by Kawanago)[3]. Thus,

the surface roughness scattering at the interface is

suppressed and that leads to the higher channel mobility

and then the larger transconductance value. The

suppression of oxygen vacancies also help to reduce the

growth of interface silicate layer [23]. Unfortunately, the

TEM picture given in Fig. 11 shows that there are some

crystalline phases exist at the CeO2/La2O3 interface and in

the CeO2 layer. As mentioned in Sec. II, crystalline phases

have several adverse effects on the current conduction over

the dielectric layer. Further investigation on the crystallite

growth mechanisms and process for minimizing the

crystallite growth of this dielectric stack are required.

IV. CONCLUSION

In the next technology node, the gate dielectric

thickness of the CMOS devices will be scaled down to the

subnanometer range. Lanthana has been considered to be a

suitable candidate for this application. However, a number

of instability issues were still found in the lanthana film

and at the lanthana/silicon interface. Yet the most

challenging issue is the material interaction at the

lanthana/Si interface, not only because it causes the

significant degradation on the channel mobility, leads to

pronounced interface charge trapping, but also because the

low-k interfacial silicate layer imposes a limit on the

thinnest EOT to be achievable which may be well above

the requirements of our future technology nodes. There are

still a lot of issues, including the chemistry of interface

material interaction, the interface physics, as well as the

optimal fabrication process for best bulk trap and interface

layer control, need to be explored further.

ACKNOWLEDGEMENT

This work is supported by National Natural Science

Foundation of China under grant No. 61376111.

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