345978-1-4799-5296-0/14/$31.00 © 2014 IEEE

PROC. 29th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2014), BELGRADE, SERBIA, 12-14 MAY, 2014

Robustness Validation in Qualification Activities of Integrated Circuits for Automotive Industry

M. Blyzniuk

Abstract - Robustness validation results aimed at achieving lower ppm-failure rates by ensuring adequate guard band between the “real life” operation range of devices and the points at which device fails are presented. One of the main attentions was paid to package reliability (especially to bonding system reliability as major limitation factor) with combination of used different Bill of Material (BOM), different wafer technologies and different products. I. “AEC Q100 QUALIFIED” – IS IT ENOUGH?

In our reliability assurance activities we are driven by

automotive quality system AEC-Q100. It is defined by the Automotive Electronics Council as a “Stress Test for Qualification for Integrated Circuits” [1]. Successful completion and documentation of the test results from requirements outlined in this document allows us to claim that the part is “AEC Q100 qualified”.

AEC-Q100 contains a number of tests on sample-base which are applied for the device and package qualification and a number of so-called screening tests which are run during production (see Figure 1) [1,9].

Fig. 1. Automotive Quality System.

In reliability activities we adhere to a modular and

failure mode driven product qualification approach for enhanced robustness validation [2,9]. The product qualification consists of compliance testing using JEDEC standards for device qualifications, wafer technology qualifications, package technology qualifications, post processing qualifications, component qualifications, and system level qualifications. For qualification and product development, a wide range of “Stresses”, “Tests” and “Data Analysis Methodologies” are considered in order to cover mission profile related application requirements. Stress & Test types, conditions and sequences are defined

in accordance to Failure Mechanism driven qualifications, which are described in the SAE J1879 standard. This approach complements and exceeds traditional AEC-Q100 requirements. We have to do it according to up-to-date requirements for reliability [4,9,11] because:

• The AECQ-100 Qualification Procedure has accentually remained unchanged over the years:

• AEC founded 1994; • Reliability Qualification Need for Change:

• Adaptation of the qualification process to today’s needs;

• Established qualification procedures aimed at high reliability level but intrinsic topics oriented do not guarantee required by today low level of ppm:

• It pushes for improved procedures. For instance, high customer requirements to ppm, e.g.

less than 2ppm, are grounded and force to change approach. If we look inside a car however (Figure 2) with all its electronic components, we can see, that even for 1 ppm the number of defect cars is high [4,9]:

Fig. 2. The complexity of a car with its high number of electronic components makes a zero-defect strategy necessary.

At the same time using of sample size 77 each out of three lots (according to AEC-Q100) confirms much less quality level even in case of pass [5].

So, we definitely have to be adapted to nowadays zero ppm strategy [2,4,9,11]. It means that:

• AEC-Q100 standardized set tests should not be used indiscriminately:

o Do not use it as cookbook approach; • Paradigm shift in Qualification:

o From test to PASS to test till FAIL; o From Stress-Tests Driven Qualification

to Knowledge-Based Qualification; • Do even more than requested in customer specific

requirements for qualification:

M. Blyzniuk is with the Department of Reliability Assurance of Global Development , Branch Establishment "Melexis-Ukraine", 4, Kotelnikova St., 03115, Kyiv, Ukraine, E-mail: mbl@melexis.com

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o Robustness validation tests; o Knowledge-Based Qualification

It is common trend in automotive industry which indicates that in order to guarantee highest safety we need Zero Defect Strategy [4]. Our Zero Defect program induces multiple aspects like Chip Design, Wafer Process, Wafer Level Test, Packaging Process, Package Level Test, Application, Solution Finding and People aspects as well. One of the main aspects in product (device, wafer, and package) level test is applying of robustness validation approach with taking into account up-to-date methodologies [3,6-8,10].

In presented paper we are focused on presentation of results of implemented robustness validation methodology aimed at achieving lower ppm-failure rates by ensuring adequate guard band between the “real life” operation range of devices and the points at which device fails.

II. ROBUSTNESS VALIDATION

To be focused in qualification on intrinsic topics of products and technologies, requiring only small sample sizes, we extend duration of reliability tests up to fail in order to define how far we are from qualification target. Idea is simple (see Figure 3) – more robust selected sample size – higher probability that full population is robust as well:

Fig. 3. Strength to finish w/o fails

Robustness validation activities include extended over AEC-Q100 Grade 0 requirements and specific customer requirements HTOL/HTSL (up to 10000h) and tests at elevated temperature (up to +175degC), TC tests (e.g. up to 2000c at -65degC/+175degC) and AC/HAST/UHAST (e.g. up to 500h) environmental tests. Main PASS criteria are:

0 electrical fails at ATE verification at Grade 0 operation temperatures range, e.g. for all sample size all parameters are in spec limits according to data sheet at ATE verification at -40degC, +25degC and +150degC/+175degC;

No Critical Parametric Drift observed; Special attention has been paid to package reliability,

including bonding system. Main PASS criteria are:

PASS criteria of IV (Internal Visual Inspection) , WBP (Wire Bond Pull Strength) and WBS (Wire Bond Shear) according to MIL 883;M.2013, MIL 883;M.2011 and AEC-Q100-001 accordingly;

Additional PASS Criteria for WBP Tests as main test which reflects bonding system reliability and robustness level:

o Mean Value of Pull Force over three times of minimum individual value according to MIL 883;M.2011;

o +/- 20% of Stability of Mean Value of Pull Force over life time;

o Acceptance only Wire Break, Brocken Neck and Wedge Break Failure Modes (Lifted Ball/Stitch Modes are not accepted even if minimum pull force is over MIL standard requirements):

Fig. 4. Accepted Failure Modes at WBP Test

Different products (e.g. Product 1, 2, 3, etc.) produced with different technologies (e.g. 1.0um, 0.8um, 0.6um, 0.35um, 0.18um) by different Silicon Foundries (e.g. SF-1, SF-2, etc.) and packaged by different Assembly Houses (e.g. AH-1, AH-2, etc.) in different Packages (e.g. SOIC, SSOP, TSSOP, QFN, etc. Package Families) with used certain BOM (e.g. BOM-1, BOM-2, etc.) had been involved in Robustness Validation Investigations in Melexis-Ukraine Reliability Laboratories in Kyiv.

As example Figure 5 demonstrates data related to WBP tests results at robustness validation phase for products produced with 0.35um CMOS Technology and packaged in Green Mold TSSOP/QFN/SOIC package families with different BOMs:

Figure 6 demonstrates data related to WBP tests results at robustness validation phase for products produced with 0.35um, 0.6um and 1.0um Technologies and packaged in SOIC/SSOP/TSSOP package families with Green BOM assembled by the same Assembly House. E.g. results of robustness validation had shown good stability of pull force over life time for combination of 1.0 um technology and Green Mold SSOP Package. First ball bond lift was observed after 3000h of HTOL: 1500h of HTOL at +150degC plus 1500h of HTOL at +160degC, what is equivalent ~3830h of HTOL at +150degC (see Figure 7). After continuation of HTOL till 6000h (equals to 8500h of HTOL at +150degC) 16% of pulled wires shown ball lift.

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Fig. 5. WBP Test results for products produced with 0.35um Technology

Fig. 6. WBP Test results at validation phase for products produced with 0.35/0.6/1.0 um Technologies and assembled in Green Mold Packages Families

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Fig. 7. Stability of wire pull force over life time

Validation phase for product of 0.35um technology in Green SOIC Package shown first ball lift after 6000h of HTOL at +155degC: equivalent to 7500h of HTOL at +150degC. However, continuation of HTOL till 8000h (equals to 10000h of HTOL at +150degC) did not shown not acceptable failure modes, and, what is more important, did not shown degradation of pull force.

III. CONCLUSION Obtained results at robustness validation phases shown that products have sufficient reliability margin of safety versus Grade 0 requirements of AEC-Q100. E.g. required minimum 1000h of HTOL at +150degC is overreached minimum in four times even according to set additional PASS/FAIL criteria (which are over the requirements of standard). Results also shown that not accepted additional criteria “lifted ball” does not lead to reliability issue if there is no degradation of pull force. Results are statistically significant and are based on investigations of robustness for more than 20 products in different technologies and packages (e.g. WBP tests statistics are based on more than 100 WBP Tests for more than 20 lots of different products, for which more than 400 parts had been exposed to destructive analysis with pulling of more than 3700 wires).

Fig. 8. Limits of bonding reliability for products in 0.35um Technology and GM Packages: Post HTOL WBP Tests Results for Product 7.

Another product/package combination (namely QFN GM Package) for 0.35um technology start to show lifted balls only after 3000h of HTSL at +175degC (equivalent to ~8745h of HTSL at +150degC). Decreasing of mean value of pull force on more than 20% had been observed. However, it should be noted, that in spite on these facts 0 electrical fails at ATE verification had been found for all samples.

REFERENCES

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